Austin AS8F512K32Q-70/883C 512k x 32 flash flash memory array Datasheet

FLASH
AS8F512K32
Austin Semiconductor, Inc.
512K x 32 FLASH
PIN ASSIGNMENT
FLASH MEMORY ARRAY
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
•
•
68 Lead CQFP (Q & Q1)
SMD 5962-94612
MIL-STD-883
FEATURES
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•
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•
•
•
•
•
•
•
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Fast Access Times: 70, 90, 120 and 150ns
Operation with single 5V (±10%)
Theta JC= 1.00°C/w
User configurable as 512Kx32, 1Mx16, or 2Mx8
Eight Equal Sectors of 64K Bytes for each 512Kx8
Compatible with JEDEC EEPROM command set
Any Combination of Sectors can be Erased
Supports Full Chip Erase
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
Built in decoupling caps for low noise operation
Suspend Erase/Resume Function
Individual Byte Read/ Write Control
Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
OPTIONS
•
•
Timing
70ns
90ns
120ns
150ns
Package
Ceramic Quad Flat pack
Ceramic Quad Flatpack
Pin Grid Array
66 Lead PGA (P)
MARKINGS
-70
-90
-120
-150
Q
Q1
P
No. 702
No. 904
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8F512K32 is a 16 Megabit
CMOS FLASH Memory Module organized as 512Kx32 bits. The
AS8F512K32 achieves high speed access (70 to 150 ns), low power
consumption and high reliability by employing advanced CMOS memory
technology.
An on-chip state machine controls the program and erase functions. The embedded byte-program and sector/chip erase functions are
fully automatic. Data-protection of any sector combination is accomplished using a hardware sector-protection feature.
The Erase/Resume function allows the sector erase operation to
read data from, or program to a non-erasing sector, then resume the
erase operation.
Device operations are selected by using standard commands into
the command register using standard microprocessor write timings. The
command register acts as an input to an internal state machine that
interprets the commands, controls the erase and programming operations, outputs the status of the device, and outputs data stored in the
device. On initial power-up operation, the device defaults to the read
mode.
AS8F512K32
Rev. 5.2 09/07
For more products and information
please visit our web site at
www.austinsemiconductor.com
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sequence transpires. The command register does not fill an
addressable memory location. The register is used to store the
command sequence, along with the address and data needed
by the memory array. Commands are written by setting CE\=VIL
and OE\= VIH and bring WE\ from logic-high to logic-low. Addresses are latched on the falling edge of WE\ and data is
latched on the rising edge of WE\. Holding WE\ =VIL and
toggling CE\ can be used as an alternative.
OPERATIONS
Read Mode
A low-level logic signal is applied to CE\ and OE\ pins to
read the output of the AS8F512K32. The CE\ is power control
and is used for device selection.
The delay from stable address to valid output data is the
address access time (tAVQA). The delay from CE\ equals logic
low and stable addresses to valid output data is the chip-enable access time (tELQV). The output-enable access time
(tGLQV) is the delay from OE\ =low logic to valid output data,
when CE\ =low logic and addresses are stable for at least tAVQAtGLQV.
Read/Reset Command
The read/reset mode is activated by writing either of the
two read/reset command register. The device remains in this
mode until one of the other valid command sequences is input
into the command register. Memory data can be read with standard microprocessor read-cycle timing in the read mode.
On power up, the device defaults to the read/reset mode.
A read/reset command sequence if not required and memory
data is available.
Standby Mode
Icc supply current is reduced by applying a logic-high on
the CE\ to enter the standby mode. In the standby mode, the
outputs are placed in the high impedance state.
If the device is deselected during erasure or programming,
the device continues to draw active current until the operation
is complete.
Algorithm-Selection Command
The algorithm-selection command allows access to binary
code that matches the device with the proper programming and erase-command operations. After writing the three bus
cycle command sequence, the first byte of the algorithm-selection code (01) can be read from address XX00. The second
byte of the code (A4) can be read from address XX01. This
mode remains in effect until another valid command sequence
is written to the device.
Output Disable
OE\= VIL or CE\=VIH, output from the device is disabled
and the output pins (DQ0 - DQ7) are placed in the high-impedance state.
Erasure and Programming
Erasure and programming of the AS8F512K32 are accomplished by writing a sequence of commands using standard
microprocessor write timings. The commands are written to a
command register and input to the command state machine.
The command state machine interprets the command entered
and initiates program, erase, suspend, and resume operations
as instructed. The command state machine acts as the interface between the write-state machine and external chip operations. The write-state machine controls all voltage generation,
pulse generation, preconditioning and verification of the contents of the memory. Program and block/chip-erase functions
are fully automatic. Once the end of a program or erase operation has been reached, the device internally resets to the read
mode. If Vcc drops below the low-voltage-detect level (VLKO),
any operation in progress is aborted and the device resets to
the read mode. If a byte-program or chip-erase operation is in
progress, additional program/erase operations are ignored until the operation completes.
Byte-Program Command
Byte-programming is a four-bus-cycle-command sequence.
The first three bus cycles put the device into the programsetup state. The fourth bus cycle loads the address location
and the data to be programmed into the device. The addresses
are latched on the falling edge of WE\ and the data is latched
on the rising edge of WE\ in the fourth cycle. The raising edge
of WE\ starts the byte-program operation. The embedded
byte-programming function automatically provides needed
voltage and timing to program and verify the cell margin. Any
further commands written to the device during the program
operation are ignored.
Programming can be preformed at any address location in
any order. When erased, all bits are in a logic state 1. Logic 0s
are programmed into the device. Attempting to program logic 1
into a bit that has been previously programmed to logic 0 causes
the internal pulse counter to exceed the pulse-count limit. This
sets the exceed-timing-limit indicator (DQ5) to a logic high state.
Only an erase operation can change bits from logic 0 to logic 1.
The status of the device during the automatic programming operation can be monitored for the completion using the
data-polling feature or the toggle-bit feature . See the “operation status” for the full description.
Command Definitions
Operating modes are selected by writing particular address
and data sequences into the command register Command Sequence Table . The device will reset to read mode if an incorrect address and data value or writing them in the incorrect
AS8F512K32
Rev. 5.2 09/07
AS8F512K32
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The embedded sector erase function automatically
provides voltage and timings needed to program and verify all
the memory cells prior to electrical erase and then erases and
verifies the cell margin automatically. The user is not required
to program the memory cells prior to erase. The status of the
device during the automatic sector erase operation can be monitored for completion using the data-polling feature or the toggle
bit feature. See the "operation status" section for a full description.
Erase-Suspend Command
Sector-erase operations may be interrupted by the erasesuspend command (B0) , in order to read data from an unaltered
sectors of the device. Erase-suspend is a one-bus-cycle command. The addresses can be VIL or VIH and the erase-suspend
command (B0) is latched on the rising edge of WE\. Once the
sector-erase operation is in progress, the erase-suspend command request the internal write-state-machine to halt operation
at predetermined break points. The erase-suspend command is
valid only during the sector-erase operation and is valid only
during the byte-programming and chip-erase operations. The
sector-erase delay timer expires immediately if the erase-suspend command is issued while the delay is active.
After erase-suspend is issued, the device takes between
0.1ms and 15 ms to suspend the operation. The toggle bit must
be monitored to determine when the suspend has been executed. When the toggle bit stops toggling, data can be read
from sectors that are not selected for erase. See the “operation
status” section for a full definition. Reading from a sector
marked for erase can result in invalid data.
Once the sector-erase operation is suspended, further
writes of the erase-suspend command are ignored. Any command other than erase-suspend (B0) or erase-resume (30H)
written to the device during the erase-suspend mode causes
the device to exit the suspend mode. To complete the sectorerase operation, reissue the sector-erase command sequence.
Chip Erase Command
Chip-erase is a six-bus-cycle command sequence. The first
three bus cycles put the device into the erase-setup state. The
next two bus cycles unlock the erase mode. The sixth bus cycle
loads the chip erase command. This command sequence is
required to ensure that the memory contents are not erased
accidentally. The rising edge of WE\ starts the chip erase operation. Any further commands written to the device during
the chip erase operation is ignored.
The embedded chip erase function automatically provides
voltage and timings needed to program and verify all the memory
cells prior to electrical erase. It then erases and verifies the cell
margin automatically. The user is not required to program the
memory cells prior to erase. The status of the device during the
automatic chip erase operation can be monitored for completion using the data-polling feature. See the "operation status"
section for a full description.
Sector-Erase Command
Sector erase is a six-bus-cycle command sequence. The
first three bus cycles put the device into the erase-setup state.
The next two bus cycles unlock the erase mode. The sixth bus
cycle loads the sector erase command and the sector address
location to be erased. Any address location within the desired
sector can be used. The addresses are latched on the falling
edge of WE\ in the sixth bus cycle. After a delay of 100-ms
from the rising edge of WE\, the sector erase operation begins
in the selected source.
Sectors can be selected to be erased concurrently during
the sector-erase command sequence. For each additional sector selected for erase, another bus cycle is issued. The bus
cycle loads the next sector-address location and the sectorerase command. The time between the end of the previous bus
cycle and the start of the next bus cycle must be less than 100
ms-other wise, the new sector location is not loaded. A time
delay of 100 ms from the raising edge of the last WE\ starts the
sector erase operation. If there is a falling edge of WE\ within
the 100 ms time delay, the timer is reset.
One to eight sector address locations can be loaded in any
order. The state of the delay timer can be monitored using the
sector-erase-delay indicator (DQ3). If DQ3 is logic low, the time
delay has not expired. See the “operation status” for the full
description.
Any commands other than erase-suspend (B0) or sector
erase (30) written to the device during the sector erase operation causes the device to exit the sector erase mode. The contents of the sector(s) selected for erase is not valid. To complete the sector-erase operation, reissue the sector erase command.
AS8F512K32
Rev. 5.2 09/07
AS8F512K32
Erase-Resume Command
The erase-resume command (30H) restarts a suspended
sector erase operation from where it was halted to completion.
Erase-resume is a one-bus-cycle command. The addresses can
be VIL or VIH and the erase-resume command (30H) is latched
on the rising edge of WE\. When an erase-suspend/ eraseresume command combination is written, the internal pulse
counter (exceed timing limit) is reset. The erase-resume command is valid only in the erase-suspend state. After the eraseresume command is executed, the device returns to the valid
sector-erase state and further writes of the erase-resume commands are ignored. After the device has resumed the sectorerase operation, another erase-resume command can be issued
to the device.
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AS8F512K32
Operation Status Flags1 Table
Device Operations2
Byte-programming in progress
Byte-programming exceed time limit
Byte-programming complete
Sector/chip erase in progress
Sector/chip erase exceed time limit
Sector/chip erase complete
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
T
0
X
0
X
X
X
D\
T
1
X
0
X
X
X
D\
D
D
D
D
D
D
D
D
0
T
0
X
1
X
X
X
0
T
1
X
1
X
X
X
1
1
1
1
1
1
1
1
NOTES:
1. T= toggle, D=data, X=data undefined
2. DQ4, DQ2, DQ1, DQ0 are reserved for future use.
OPERATION STATUS
bit DQ6 stops toggling after two consecutive reads to the same
address, the operation is complete. The toggle-bit is only
available during the byte-programming, chip-erase, and sectorerase timing delay. Toggle-bit data is valid after the raising
edge of ?W/E in the last bus cycle of the command sequence
loaded into the command register. Depending on the read timing, DQ6 can stop toggling while other DQ pins are still invalid.
A subsequent read of the device is valid.
Status Bit Definition
During operation of the automatic embedded program and
erase functions, the status of the device can be determined by
reading the data state of designated outputs. The data-polling
bit (DQ7) and toggle-bit (DQ6) require multiple successive reads
to observe a change in the state of the designated output.
Operation Status Flags Table defines the values of the Flag
status.
Exceed Time Limit DQ5
The program and erase operations use an internal pulse
counter to limit the number of pulses applied. If the pulse count
limit is exceeded, DQ5 is set to a 1 data state. This indicates that
the program or erase operation has failed. DQ7 will not change
from complemented data to true data and DQ6 will not stop
toggling when read. To continue operation, the device must be
reset.
This condition occurs when attempting to program a logic
1 state into a bit that has been programmed previously to a
logic 0. Only an erase operation can change bits from 0 to 1.
After reset, the device is functional and can be erased and
reprogrammed.
Data-Polling DQ7
The data-polling status outputs the complement of the data
latched into the DQ7 data register while the write-state machine
is engaged in a program or erase operation. Data bit DQ7 changing from complement to true indicates the end of an operation.
Data-polling is available only during the byte-programming,
chip-erase, sector-erase, and sector-erase timing delay. Datapolling is valid after the rising edge of ?W/E in the last bus cycle
of the command sequence loaded into the command register.
During a byte-program operation, reading DQ7 outputs
the complement of the DQ7 data to be programmed at the selected address location. Upon completion, reading DQ7 outputs the true DQ7 data loaded into the program data register.
During the erase operations, reading DQ7 outputs a 0. Upon
completion, reading DQ7 outputs a 1. Also, data polling must
be performed at a new sector address that is within a sector
being erased; otherwise the status is not valid. When using
data-polling, the address should remain stable throughout the
operation.
During a data-polling read, while ?W/E is low, data bit DQ7
can change asynchronously. Depending on the read timing,
the system can read valid data on DQ7, while other DQ pins are
still invalid. A subsequent read of the device is valid.
Sector-Load- Timer DQ3
DQ3 is the sector-load timer status bit it determines if the
time to load additional sector addresses has expired. DQ3 remains a logic low for 80 µs after completion of a sector-erase
sequence. This indicates another sector-erase command sequence can be issued. If DQ3 is at logic high, it indicates that
the delay has expired and attempts to issue additional sectorerase commands are ignored.
The data polling bit and toggle bit are valid during the 100
µs time delay and can be used to determine if a valid sector
erase command has been issued. To ensure additional sector
erase commands have been accepted, the status of DQ3 should
be read before and after each additional sector-erase command.
If DQ3 is at a logic low on both reads, then the additional sector-erase was accepted.
Data-Polling DQ6
The function of toggle-bit status, is to output data on
DQ6 that toggles between 1 and 0 while the write-state machine is engaged in a program or erase operation. When toggleAS8F512K32
Rev. 5.2 09/07
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AS8F512K32
DATA PROTECTION
Hardware-Sector Protection Feature
This feature disables both programming and erase operations on any combination of one to eight sectors. Commands
to program or erase a protected sector do not change the data
contained in the sector. The data-polling and toggle bits operate for 2ms to 100ms and then return to valid data. This feature
is enabled using high-voltage VID (11.5V to 12V) on address
pin A9 and control pin OE\ and VIL on control pin CE\.
The device is delivered with all sector unprotected.
Sector-unprotected mode is available to unprotect protected
sectors.
Sector Unprotect
Prior to sector unprotected, all sectors should be protected
using the sector unprotect mode. The sector unprotect is activated when WE\=VIH, and control pin CE\, OE\, and address
pin A9 are forced to VID. Address pins A6, A12, and A16 are
set to VIH. The sector select address pins A18, A17, and A16
can be VIL or VIH. All eight sectors are unprotected in parallel.
Once the inputs are stable, WE\ is pulsed low for 10ms. The
unprotect operation begins on the falling edge of WE\ and
terminates on the raising edge of WE\.
Sector Unprotect Verify
Verification of the sector unprotected is activated when
WE\ = VIH, OE\ = VIL, CE\ = VIL, and address pin A9 = VID.
Select the sector to be verified. Address A1 and A6 are set to
VIH and A0 to VIL. The other addresses can be VIL or VIH. If
the sector selected is protected, the DQs output a 01, if sector
selected is unprotected the DQs output a 00. Sector unprotect
can also be read using the algorithm selection command.
Sector Protect Operation
The sector protect mode is activated when WE\=VIH,
CE\=VIL , and address pin A9 and control pin OE\ are forced to
VID. The sector-select address pins A18, A17, and A16 are
used to select the sector to be protected. Address pins A0-A15
and I/O pins DQ0- DQ7 must be stable and can be VIL or VIH.
Once the addresses are stable, WE\ is pulsed low for 100 ms.
The operation begins on the falling edge of WE\ and terminates
on the raising edge of WE\.
Low VCC Write Lock Out
During power-up and power-down , are locked out for VCC
less than VLKO If VCC<VLKO, the command inputs is disabled and the device is reset to the read mode. On power-up, if
CE\=VIL, WE\= VIL, and OE\=VIH, the device does not accept
commands on the raising edge of WE. The device automatically powers up in the read mode.
Sector Protect Verify
Verification of sector protection is activated when
WE\=VIH, CE\=VIL , OE\=VIL , and address pin A9 is VID.
Address pins A0 and A6 are set to VIL , and A1 is set to VIH.
The sector address pins A18, A17, and A16 select the sector to
be verified. The other addresses can be VIH or VIL. If the
sector selected if protected, the DQs output O1. If the sector
selected is unprotected the DQs output is 00.
Sector protection can also be verified using the algorithmselection command. After issuing the three bus-cycle command
sequence, the sector protection status can be read on DQ0. Set
address pins A0 = VIL, A1 = VIH, and A6 = VIL. Sector
address pins A18, A17, and A16 select the sector to be verified.
The remaining addresses are set to VIL. If the sector selected is
protected. DQ0 outputs a 1 state, and if the sector selected is
unprotected DQ0 outputs a 0 state. This mode remains in effect
until another valid sequence is written to the device.
AS8F512K32
Rev. 5.2 09/07
Glitiching
Pulses of less than 5ns (typical) on WE\, OE\, and CE\ will
not issue a write cycle.
Power Supply Consideration
Each device should have as a maximum of 0.1 mF ceramic
capacitor connected between Vcc and Vss to suppress circuit
noise. Printed circuit traces to Vcc should have be appropriate
to handle the current demand and minimize inductance.
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AS8F512K32
Austin Semiconductor, Inc.
Flow Chart 1.
Sector Protect Algorithm
Start
Select Sector Address
A18,A17,A16
X=1
OE and, A9=VID
CE=VIL
Apply One
100 µs Pulse
OE, A0 and A6 = VIL
A1 = VIH
X = X+1
Select Sector Address
A18, A17, A16 = VIL
Read Data
No
No
X = 25
?
Data = 01
?
Yes
Yes
Protect
Additional
Sector
?
Sector-Protect Failed
Yes
Yes
A9=VIH or VIL
Write Reset Command
End
AS8F512K32
Rev. 5.2 09/07
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AS8F512K32
Flow Chart 2.
Sector Unprotect Algorithm
Start
Protect All Sectors
X=1
CE,OE,A9=VID
A6, A12, A16=VIH
Apply One
10 ms Pulse
CE, OE, A0 = VIL
A6, A1 = VIH
X = X+1
Select Sector Address
A18, A17, A16 = VIL
Read Data
No
No
X = 1000
Next Sector Address
Data = 00
Yes
Yes
No
Sector-unprotect Failed
Last Sector?
Yes
A9=VIH or VIL
Write Reset Command
End
AS8F512K32
Rev. 5.2 09/07
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AS8F512K32
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc Supply Relative to Vss
Vcc (Note 1) .......................................................-2.0V to +7.0V
A9 (Note 2)…...............................................…. -2.0V to +14V
All Other Pins (Note 1)................…….............-2.0V to +7.0V
Operating Temperature, TA (Ambient)...........55°C to +125°C
Storage Temperature .....................................-65°C to +150°C
Power Dissipation…………………........................…...1.5W
Short Circuit Output Current (Note 3)…......................200mA
Lead Temperature (soldering 10 seconds)..................+300°C
Junction Temperature................................................+165°C
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operation section of this specification is not implied, Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
NOTES:
1. Minimum DC voltage on input or I/O pins is -0.5V. During Voltage transitions, inputs may overshoot Vss to -2.0V for periods
of up to 20 ns. Maximum DC voltage on input or I/O pins is Vcc +0.5V. During Voltage transitions, inputs may overshoot Vcc
to +2.0V for periods of up to 20 ns.
2. Minium DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 pins may overshoot Vss to -2.0V for periods of up
to 20 nS. Maximum DC input voltage on A9 is +12.5V inputs which may overshoot to +13.5V for periods of up to 20 ns.
3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
Capacitance Table
VIN = 0V, f = 1MHz, TA =25º C
AS8F512K32
Rev. 5.2 09/07
Symbol
Parame te r
Maximum
Units
CADD
A0-A18 Capactiance
50
pF
COE
OE\ Capactiance
50
pF
CWE, CCE
WE\ and CE\ Capactiance
20
pF
CIO
I/O 0 - I/O 31 Capactiance
20
pF
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AS8F512K32
Austin Semiconductor, Inc.
User Bus Operations
Operation
CS\ 1-4
Read
L
Output Disable
L
Standby and Write Inhibit
H
Write
L
Sector Protect
L
Verify Sector Protect
L
See Chart 1
Sector Unprotect
Verify Sector Unprotect
L
Erase Operations
L
OE\
L
H
X
H
VID
L
See Chart 1
L
H
WE\ 1-4
H
H
X
L
L
H
L
H
A0
X
X
X
A0
X
L
L
L
A1
X
X
X
A1
X
H
H
H
A6
X
X
X
A6
X
L
H
H
A9
X
X
X
A9
VID
VID
See Chart 1
VID
See Note 1 See Note 1 See Note 1 See Note 1 See Note 1
I/O
Data Out
HIGH Z
HIGH Z
Data In
X
Data Out
Data Out
Data Out
See Note 1
LEGEND:
L = VIL, H = VIH, X = Don't Care, VID = 12V, See DC Charateristics for voltage levels
NOTE:
1. See Chip/Sector Erase Operation Timings and Alternate CE\ Controlled Write Operation Timings.
Sector Address Table
SECTOR
A18
A17
A16
ADDRESS RANGE
SA0
0
0
0
00000-0FFFF
SA1
0
0
1
10000-1FFFF
SA2
0
1
0
20000-2FFFF
SA3
0
1
1
30000-3FFFF
SA4
1
0
0
40000-4FFFF
SA5
1
0
1
50000-5FFFF
SA6
1
1
0
60000-6FFFF
SA7
1
1
1
70000-7FFFF
Pin Description
Pin
A0-A18
I/O 0-31
CE\ 1-4
WE\ 1-4
OE\
VSS
VCC
AS8F512K32
Rev. 5.2 09/07
Function
Address Inputs
Data Input/Outputs
Chip Enable
Write Enable
Output Enable
Device Ground
Device Internal Power Supply (5.0 V+/- 10%)
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Cycles
Command Denfinitions Table
Command Sequence
Reset
Read
Algorithm Selection
Program
Chip Erase
Sector Erase
Sector Erase Supend
Sector Erase Resume
1
4
4
4
6
6
Bus Cycles
First
Fifth
Sixth
Second
Third
Fourth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
XXXX F0
5555 AA 2AAA
55
5555
F0
RA
RD
5555 AA 2AAA
55
5555
90
RA
RD
5555 AA 2AAA
55
5555
A0
PA
PD
5555 AA 2AAA
55
5555
80
5555 AA 2AAA
55
5555
10
5555 AA 2AAA
55
5555
80
5555 AA 2AAA
55
SA
30
XXXX B0 Erase-supend vaild during sector-erase operation
XXXX 30 Erase-resume vaild only after erase supend
LEGEND:
RA = Address of the location to be read
PA = Address of the location to be programed
SA = Address of the sector to erased
Addresses A18, A17, A16 select 1 of 8 sectors
RD = Data to be read at selected address location
PD = Data to be programmed at selected address location
*Address pin A18, A17, A16, A15 = VIL or VIH for al bus cycle addresses except for program address (PA),
sector address(SA), and read address (RA).
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V +5%/-10%)
! ! ) *+ - .
%
0 .
$ %&
"# "# $ %&
"# $ %&
' ' µΑ
µΑ
µΑ
'
(
'
,
'
/
(
% 0 . . $ ) 1 - . "# "# / NOTES:
1. Icc active while Embedded Program or Embedded Erase Algorithm is in progress.
2. Not 100% tested.
3. Applies to 32 bit operations.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
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AS8F512K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V -5%/+10%)
Parameter
Symbol
JEDEC Std.
Speed Options
Test Setup
CE\=VIL,
OE\=VIL
Parameter Description
-70
-90 -120 -150
Min
70
90
120
150
ns
Max
70
90
120
150
ns
Units
tAVAV
tRC
Read Cycle Time (Note 3)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable Low to Output Valid
Max
70
90
120
150
ns
tGLQV
tOE
Output Enable to Output Delay
Max
30
35
50
55
ns
Read
Output Enable Hold Time
Toggle and
(Note 3)
Data\Polling
Chip Enable High to Output High Z
(Note 2, 3)
Output Enable to Output High Z
(Note 2,3)
Output Hold Time from Addresses, CE\
or OE\, Whichever Occurs First
Min
0
0
0
0
ns
Min
10
10
10
10
ns
Max
20
20
30
35
ns
20
20
30
35
ns
0
0
0
0
ns
tOEH
tEHQZ
tHZ
tGHQZ
tDF
tAXQX
tOH
CE\=VIL,
OE\=VIL
Min
NOTES:
1. See Test Specification for test conditions.
2. Output driver disable time.
3. Guaranteed but not Tested.
Read Operation Timings
t
RC
Addresses Stable
Addresses
t
ACC
CE\
t
t
CE
OE\
DF
t
OEH
t
CE
WE\
High-Z
Outputs
t
OH
Output Valid
High-Z
OV
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
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AS8F512K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V +/- 10%)
Erase and Program WE\ Controlled
Parameter
Symbol
JEDEC
Std.
tWC
tAVAV
tAS
tAVWL
tAH
tWLAX
tDS
tDVWH
tDH
tWHDX
tOES
tGHWL
tGHWL
tELWL
tWHEH
tWLWH
tWHWL
tWHWH1
tWHWH2
tWHWH3
tVCHEL
tCS
tCH
tWP
tWPH
AS8F512K32
Rev. 5.2 09/07
tWHWH1
tWHWH2
tWHWH3
Parameter Description
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Write Enable High to Input Transition
Output Enable Setup Time
Read Recover time Before Write
(OE\ high to WE\ low)
CE\ Setup Time
CE\ Hold Time
Write Pulse Width
Write Pulse Width High
Programming Operation
Sector Erase Operation
Chip Erase Operation
VCC Setup Time
Chip Program Time
Min
Min
Min
Min
Min
Min
-70
70
Speed Options
-90
-120
90
120
0
Units
-150
150
0
0
ns
ns
ns
ns
ns
ns
Min
0
ns
Min
Min
Min
Min
Min
0
0
20
16
ns
ns
ns
ns
us
30
120
50
50
sec
sec
us
sec
Max
Max
Min
Max
45
30
35
45
45
50
50
45
50
50
50
50
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
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AS8F512K32
Austin Semiconductor, Inc.
Program Operation Timings
t
t
WC
555h
Addresses
AS
12345
11234
12345
12
12345
11234
12345
12
12345
11234
12345
12
12345
11234
12345
12
PA
t
PA
PA
AH
CE\
t
t
GHWL
CH
OE\
t
t
WP
WHWH1
WE\
t
CS
Data
t
DS
AOh
t
WPH
DH
t
Status
PD
DOUT
t
VCS
Vcc
NOTE: PA= Program Address, PD= Program data, DOUT is the true data at the program address.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
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AS8F512K32
Austin Semiconductor, Inc.
Chip/Sector Erase Operation Timings
t
t
WC
AS
2AAh
Addresses
555h for Chip Erase
CE\
123456
1234
12
12345
11
123456
1234
12
12345
1234
123456
12
12345
1
1234
123456
12
12345
1
SA
t
VA
VA
AH
t
t
CH
GHWL
OE\
t
t
WP
WHWH2
WE\
t
CS
Data
t
DS
55h
t
t
t
WPH
DH
In
Progress
30th
Complete
10 for Chip Erase
VCS
Vcc
NOTE: SA= Sector Address. VA = Valid Address for reading status data.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
14
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AS8F512K32
Austin Semiconductor, Inc.
Data Polling Timings (During Embedded Algorithms)
t
RC
Addresses
VA
t
12345
1234
12345
1
11
12345
1234
12345
1234
1
12345
1 12345
1
12345
1234
12345
1 12345
1
12345
1234
123456
1234
12345
12
11
123456
1234
12345
1234
12
123456
1212345
1
123456
1234
12345
12
1
123456
1234
12345
VA
VA
ACC
t
CE
CE\
t
CH
t
OE
OE\
t
t
OEH
WE\
t
DQ7
DQ0-DQ6
DF
OH
Complement
Complement
True
Valid Data
High-Z
Status Data
Status Data
True
Valid Data
High-Z
NOTE: VA=Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array
data read cycle.
Toggle Bit Timings ( During Embedded Algorithms)
t
RC
Addresses
VA
t
12345
123456
12
1
12
12345
123456
12
1
12
12345
123456
12
1
12
12345
123456
12
1
12
12345
123456
12
1
12
123456
123456
123456
123456
123456
VA
VA
VA
ACC
t
CE
CE\
t
CH
t
OE
OE\
t
WE\
DQ6/DQ2
t
OEH
t
DF
OH
Valid Status
Valid Status
Valid Status
Valid Status
(first read)
NOTE: VA=Valid address; not required for DQ6. Illustration shows first two status cycles after command sequence, last
status read cycle, and array data read cycle.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
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AS8F512K32
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55°C < TA < 125°C; VCC = 5V +/- 10%)
Erase and Program CE\ Controlled (Alternate CE\ Controlled Writes)
Parameter
Symbol
JEDEC
Std.
tAVAV
tWC
tAS
tAVEL
tAH
tELAX
tDS
tDVEH
tDH
tEHDX
tGHEL
tGHEL
tWS
tWLEL
tWH
tEHWH
tCP
tELEH
tCPH
tEHEL
tWHWH1 tWHWH1
tWHWH2 tWHWH2
AS8F512K32
Rev. 5.2 09/07
Parameter Description
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Max
Max
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recover time Before Write
Setup Time, WE\
Hold Time, WE\
Pulse Duration CE\ Low
Pulse Duration CE\ High
Byte Programming Operation
Sector Erase Operation
Chip Erase
Chip Programming
-70
70
45
30
Speed Options
-90
-120
90
120
0
Units
-150
150
20
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
30
120
50
sec
sec
sec
45
45
50
50
50
50
50
50
0
0
0
0
35
45
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
FLASH
Austin Semiconductor, Inc.
AS8F512K32
Alternate CE\ Controlled Write Operation Timings
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
FLASH
AS8F512K32
Austin Semiconductor, Inc.
AC TEST CONDITIONS
IOL
Current Source
Device
Under
Test
-
+
Vz = 1.5V
(Bipolar
Supply)
+
Ceff = 50pf
IOH
Current Source
NOTES:
Vz is programable from -2V to + 7V.
IOL and IOH programmable from 0 to 16 mA.
Vz is typically the midpoint of VOH and VOL.
IOL and IOH are adjusted to simulate a typical resistive load circuit.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
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AS8F512K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #702 (Package Designator Q)
SMD 5962-94612, Case Outline M
D2
D1
DETAIL A
D
R
1o - 7o
B
b
L1
e
SEE DETAIL A
A
A2
E
SMD SPECIFICATIONS
SYMBOL
A
A1
A2
B
b
D
D1
D2
E
e
R
L1
MIN
0.123
0.118
0.005
MAX
0.200
0.186
0.015
0.010 REF
0.013
0.017
0.800 BSC
0.870
0.980
0.936
0.890
1.000
0.956
0.050 BSC
0.010 TYP
0.035
0.045
*All measurements are in inches.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
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Austin Semiconductor, Inc.
AS8F512K32
MECHANICAL DEFINITIONS*
ASI Case (Package Designator Q1)
SMD 5962-94612, Case Outline A
SYMBOL
A
A1
b
B
c
D/E
D1/E1
D2/E2
e
L
R
SMD SPECIFICATIONS
MIN
MAX
--0.200
0.054
--0.013
0.017
0.010 TYP
0.009
0.012
0.980
1.000
0.870
0.890
0.800 BSC
0.050 BSC
0.035
0.045
0.010 TYP
*All measurements are in inches.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
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AS8F512K32
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #904 (Package Designator P)
SMD 5962-94612, Case Outline 4
4xD
D1
A
A1
D2
Pin 56
φb1
Pin 1
(identified by
0.060 square pad)
E
E1
e
φb
Pin 66
e
φb2
Pin 11
L
SMD SPECIFICATIONS
SYMBOL
A
A1
φb
φb1
φb2
D
D1/E1
D2
E
e
L
MIN
0.135
0.025
0.016
0.045
0.065
1.064
MAX
0.195
0.035
0.020
0.055
0.075
1.086
1.000 BSC
0.600 BSC
1.020
1.060
0.100 BSC
0.145
0.155
*All measurements are in inches.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
21
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AS8F512K32
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS8F512K32Q-120/XT
Device Number
AS8F512K32
AS8F512K32
AS8F512K32
AS8F512K32
Package
Type
Q
Q
Q
Q
Speed
ns
-70
-90
-120
-150
EXAMPLE: AS8F512K32Q-150/883C
Process
Device Number
/*
/*
/*
/*
AS8F512K32
AS8F512K32
AS8F512K32
AS8F512K32
Package
Type
Q1
Q1
Q1
Q1
Speed
ns
-70
-90
-120
-150
Process
/*
/*
/*
/*
EXAMPLE: AS8F512K32P-70/IT
Device Number
AS8F512K32
AS8F512K32
AS8F512K32
AS8F512K32
Package
Type
P
P
P
P
Speed
ns
-70
-90
-120
-150
Process
/*
/*
/*
/*
*AVAILABLE PROCESSES
CT = Commercial Temperature Range
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
AS8F512K32
Rev. 5.2 09/07
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22
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Austin Semiconductor, Inc.
AS8F512K32
ASI TO DSCC PART NUMBER*
CROSS REFERENCE
ASI Package Designator Q
ASI Part #
SMD Part #
AS8F512K32Q-150/883C
AS8F512K32Q-120/883C
AS8F512K32Q-90/883C
AS8F512K32Q-70/883C
AS8F512K32Q-150/883C
AS8F512K32Q-120/883C
AS8F512K32Q-90/883C
AS8F512K32Q-70/883C
5962-9461201HMX
5962-9461202HMX
5962-9461203HMX
5962-9461204HMX
5962-9461201HMX
5962-9461202HMX
5962-9461203HMX
5962-9461204HMX
ASI Package Designator Q
ASI Part #
SMD Part #
AS8F512K32Q1-150/883C
AS8F512K32Q1-120/883C
AS8F512K32Q1-90/883C
AS8F512K32Q1-70/883C
AS8F512K32Q1-150/883C
AS8F512K32Q1-120/883C
AS8F512K32Q1-90/883C
AS8F512K32Q1-70/883C
5962-9461201HMX
5962-9461202HMX
5962-9461203HMX
5962-9461204HMX
5962-9461201HMX
5962-9461202HMX
5962-9461203HMX
5962-9461204HMX
ASI Package Designator P
ASI Part #
SMD Part #
AS8F512K32P-150/883C
AS8F512K32P-120/883C
AS8F512K32P-90/883C
AS8F512K32P-70/883C
AS8F512K32P-150/883C
AS8F512K32P-120/883C
AS8F512K32P-90/883C
AS8F512K32P-70/883C
5962-9461201H4X
5962-9461202H4X
5962-9461203H4X
5962-9461204H4X
5962-9461201H4X
5962-9461202H4X
5962-9461203H4X
5962-9461204H4X
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
AS8F512K32
Rev. 5.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
23