TI1 CDCVF2505DG4 3.3-v clock phase-lock loop clock driver Datasheet

SCAS640E − JULY 2000 − REVISED MARCH 2005
D Phase-Lock Loop Clock Driver for
D
D
D
D
D
D
D
D
D
D
D
Synchronous DRAM and General-Purpose
Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-cycle): <|150 ps| Over the
Range 66 MHz−200 MHz
Distributes One Clock Input to One Bank of
Five Outputs (CLKOUT Is Used to Tune the
Input-Output Delay)
Three-States Outputs When There Is no
Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
Consumes Less Than 100 µA (Typically) in
Power Down Mode
Internal Feedback Loop Is Used to
Synchronize the Outputs to the Input Clock
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates
the Need for External Components
D OR PW PACKAGE
(TOP VIEW)
CLKIN
1Y1
1Y0
GND
1
8
2
7
3
6
4
5
CLKOUT
1Y3
VDD 3.3 V
1Y2
description
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the output clocks (1Y[0−3] and CLKOUT) to the input clock
signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that
make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50
percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input
signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop
filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000 − 2005, Texas Instruments Incorporated
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1
SCAS640E − JULY 2000 − REVISED MARCH 2005
FUNCTION TABLE
OUTPUTS
INPUT
CLKIN
1Y (0:3)
CLKOUT
L
H
<10 MHz†
L
H
Z
L
H
Z
† Typically, below 2 MHz the device goes in power-down mode in
which the PLL is turned off and the outputs enter into Hi-Z mode. If
a >10-MHz signal is applied at CLKIN the PLL turns on, reacquires
lock, and stabilizes after approximately 100 µs. The outputs will then
be enabled.
functional block diagram
8
CLKIN
1
PLL
25 Ω
3
25 Ω
2
Power Down
25 Ω
5
25 Ω
7
25 Ω
Edge Detect
Typical <10 MHz
2
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CLKOUT
1Y0
1Y1
1Y2
1Y3
SCAS640E − JULY 2000 − REVISED MARCH 2005
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
1Y[0−3]
2, 3, 5, 7
O
Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25-Ω
series damping resistor.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver.
CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once
the circuit is powered up and a valid signal is applied, a stabilization time (100 µs) is required for the
PLL to phase lock the feedback signal to CLKIN.
CLKOUT
8
O
Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is
made inside the chip and an external feedback loop should NOT be connected. CLKOUT can be
loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs.
GND
4
Power
Ground
VDD3.3V
6
Power
3.3-V Supply
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.3 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous total output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.5°C/W
PWR package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230.5°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.3 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
Supply voltage, VDD
High-level input voltage, VIH
MIN
NOM
MAX
3
3.3
3.6
0.7 VDD
Low-level input voltage, VIL
Input voltage, VI
0
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
−40
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• DALLAS, TEXAS 75265
UNIT
V
V
0.3 VDD
V
VDD
−12
V
mA
12
mA
85
°C
3
SCAS640E − JULY 2000 − REVISED MARCH 2005
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
fclk
Clock frequency
Input clock duty cycle
NOM
24
24 MHz − 85 MHz (see Note 4)
30%
86 MHz − 200 MHz
40%
MAX
UNIT
200
MHz
85%
50%
Stabilization time (see Note 5)
60%
100
µs
NOTES: 4. Ensured by design but not 100% production tested.
5. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does
not apply for input modulation under SSC application.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
VOL
TEST CONDITIONS
Input voltage
II = −18 mA
IOH = −100 µA
High-level output voltage
Low-level output voltage
VDD
3V
MIN to MAX
MIN
IOH = −12 mA
IOH = −6 mA
3V
VDD−0.2
2.1
3V
2.4
IOL = 100 µA
IOL = 12 mA
MIN to MAX
MAX
UNIT
−1.2
V
V
0.2
3V
0.8
IOL = 6 mA
VO = 1 V
3V
0.55
VO = 1.65 V
VO = 2 V
3.3 V
3.3 V
40
4.2
3V
IOH
High-level output current
IOL
Low-level output current
II
Ci
Input current
VO = 1.65 V
VI = 0 V or VDD
Input capacitance
VI = 0 V or VDD
3.3 V
Co
Output capacitance
VI = 0 V or VDD
3.3 V
3V
V
−27
mA
−36
27
mA
±5
Yn
CLKOUT
TYP†
µA
pF
2.8
pF
5.2
† All typical values are at respective nominal VDD and 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 25 pF, VDD = 3.3 V ± 0.3 V (see Note 5)
PARAMETER
TEST CONDITIONS
tpd
tsk(o)
Propagation delay (normalized (see Figure 3)
CLKIN to Yn, f= 66 MHz to 200 MHz
Output skew (see Note 6)
Yn to Yn
tc(jit_cc)
Jitter (cycle to cycle) (see Figure 5)
odc
Output duty cycle (see Figure 4)
TYP†
−150
MAX
UNIT
150
ps
150
ps
f = 66 MHz to 200 MHz
70
150
f = 24 MHz to 50 MHz
200
400
f = 24 MHz to 200 MHz at 50% VDD
tr
Rise time
VO = 0.4 V to 2 V
tf
Fall time
VO = 2 V to 0.4 V
† All typical values are at respective nominal VDD and 25°C.
NOTE 6: The tsk(o) specification is only valid for equal loading of all outputs.
4
MIN
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• DALLAS, TEXAS 75265
ps
45%
55%
0.5
2
ns
0.5
2
ns
SCAS640E − JULY 2000 − REVISED MARCH 2005
ESD information
ESD MODELS
LIMIT
Human Body Model (HBM)
2.0 kV
Machine Model (MM)
300 V
Charge Device Model (CDM)
1 kV
thermal information
THERMAL AIR FLOW (CFM)
CDCVF2505 8-PIN SOIC
0
150
250
500
UNIT
RθJA
High K
97
87
83
77
°C/W
RθJA
Low K
165
126
113
97
°C/W
RθJC
High K
39
°C/W
RθJC
Low K
42
°C/W
THERMAL AIR FLOW (CFM)
CDCVF2505 8-PIN TSSOP
UNIT
0
150
250
500
149
142
138
132
°C/W
230
185
170
150
°C/W
RθJA
High K
RθJA
Low K
RθJC
High K
65
°C/W
RθJC
Low K
69
°C/W
TYPICAL CHARACTERISTICS
tpd, PROPAGATION DELAY TIME
vs
DELTA LOAD (TYPICAL VALUES @ 3.3 V, 25°C)
CLOCK FREQUENCY, f = 100 MHz
tpd, PROPAGATION DELAY TIME
vs
FREQUENCY (TYPICAL VALUES @ 3.3 V, 25°C)
500
1400
Yn = 25 pF
Yn = 3 pF
CLKOUT = Yn =
25 pF || 500 Ω
3 pF || 500 Ω
700
t pd− Propagation Delay Time − ps
t pd− Propagation Delay Time − ps
1050
350
CLKOUT
3 pF to 25 pF
0
−13
−4
−350
−700
CLKOUT
3 pF to 25 pF
Load: CLKOUT = 12 pF || 500 Ω,
Yn = 25 pF || 500 Ω
400
300
200
100
−1050
−1400
−30
−20
−10
0
10
Delta Load − pF
20
30
0
25
50
75
100
125
150
f − Frequency − MHz
175
200
Figure 2
Figure 1
NOTE: Delta Load = CLKOUT Load − Yn Load
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5
SCAS640E − JULY 2000 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
tpd, TYPICAL PROPAGATION DELAY TIME
vs
FREQUENCY(TUNED FOR MINIMUM DELAY)
DUTY CYCLE
vs
FREQUENCY
55
Load: CLKOUT = 12 pF || 500 Ω,
Yn = 25 pF || 500 Ω
Load: CLKOUT = 21 pF || 500 Ω,
Yn = 25 pF || 500 Ω
100
52.5
Duty Cycle − %
t pd− Propagation Delay Time − ps
150
50
0
50
−50
47.5
−100
45
25
−150
0
50
150
100
200
50
75
100
125
150
f − Frequency − MHz
f − Frequency − MHz
Figure 3
ICC, SUPPLY CURRENT
vs
FREQUENCY
500
120
Typical Values @ 3.3 V,
TA = 25°C
Worst Case @ VCC = 3.6 V, TA = 85°C,
Load: Y and CLKOUT = 25 pF || 500 Ω
100
400
I CC − Supply Current − mA
t c(jit_CC) − Cycle−Cycle Jitter − ps
200
Figure 4
CYCLE−CYCLE JITTER
vs
FREQUENCY
300
200
100
80
60
40
20
0
25
50
75
100
125
150
f − Frequency − MHz
175
200
0
0
20
Figure 5
6
175
40
60 80 100 120 140 160 180 200
f − Frequency − MHz
Figure 6
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• DALLAS, TEXAS 75265
SCAS640E − JULY 2000 − REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500 Ω
Yn = 25 pF || 500 Ω
CLKOUT = 12 pF || 500 Ω
Figure 7. Test Load Circuit
3V
50% VDD
CLKIN
0V
tpd
1Y0 − 1Y3
2V
0.4 V
50% VDD
tr
VOH
2V
0.4 V
VOL
tf
Figure 8. Voltage Threshold for Measurements, Propagation Delay (tpd)
Any Y
50 % VDD
tsk(o)
Any Y
50 % VDD
Figure 9. Output Skew
tc1
tc2
tc(jit_CC) = tc1 − tc2
Figure 10. Cycle-to-Cycle Jitter
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7
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CDCVF2505D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCVF2505DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCVF2505DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCVF2505DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCVF2505PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
CDCVF2505PWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
CDCVF2505PWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Jun-2010
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CDCVF2505 :
• Automotive: CDCVF2505-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCVF2505DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
CDCVF2505PWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCVF2505DR
SOIC
D
8
2500
367.0
367.0
35.0
CDCVF2505PWR
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
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