NSC COP411L Single-chip n-channel microcontroller Datasheet

COP410L/COP411L/COP310L/COP311L
Single-Chip N-Channel Microcontrollers
General Description
Features
The COP410L and COP411L Single-Chip N-Channel Microcontrollers are members of the COPSTM family, fabricated
using N-channel, silicon gate MOS technology. These Controller Oriented Processors are complete microcomputers
containing all system timing, internal logic, ROM, RAM and
I/O necessary to implement dedicated control functions in a
variety of applications. Features include single supply operation, a variety of output configuration options, with an instruction set, internal architecture and I/O scheme designed to facilitate keyboard input, display output and BCD
data manipulation. The COP411L is identical to the
COP410L, but with 16 I/O lines instead of 19. They are an
appropriate choice for use in numerous human interface
control environments. Standard test procedures and reliable
high-density fabrication techniques provide the medium to
large volume customers with a customized Controller Oriented Processor at a low end-product cost.
The COP310L and COP311L are exact functional equivalents but extended temperature versions of COP410L and
COP411L respectively.
The COP401L should be used for exact emulation.
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Low cost
Powerful instruction set
512 x 8 ROM, 32 x 4 RAM
19 I/O lines (COP410L)
Two-level subroutine stack
16 ms instruction time
Single supply operation (4.5V – 6.3V)
Low current drain (6 mA max)
Internal binary counter register with MICROWIRETM serial I/O capability
General purpose and TRI-STATEÉ outputs
LSTTL/CMOS compatible in and out
Direct drive of LED digit and segment lines
Software/hardware compatible with other members of
COP400 family
Extended temperature range device
Ð COP310L/COP311L (b40§ C to a 85§ C)
Block Diagram
TL/DD/6919 – 1
FIGURE 1. COP410L
COPSTM and MICROWIRETM are trademarks of National Semiconductor Corporation.
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation
TL/DD/6919
RRD-B30M105/Printed in U. S. A.
COP410L/COP411L/COP310L/COP311L
Single-Chip N-Channel Microcontrollers
March 1992
COP410L/COP411L
Absolute Maximum Ratings
Power Dissipation
COP410L
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 0.5V to a 10V
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature
(Soldering, 10 seconds)
0.75W at 25§ C
0.4W at 70§ C
COP411L
0.65W at 25§ C
0.3W at 70§ C
Total Source Current
120 mA
Total Sink Current
100 mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
0§ C to a 70§ C
b 65§ C to a 150§ C
300§ C
DC Electrical Characteristics 0§ C s TA s a 70§ C, 4.5V s VCC s 6.3V unless otherwise noted
Parameter
Conditions
Standard Operating Voltage (VCC)
Power Supply Ripple (Notes 1, 4)
Peak to Peak
Operating Supply Current
All Inputs and Outputs Open
Min
Max
Units
4.5
6.3
V
0.5
V
6
mA
3.0
2.0
b 0.3
0.4
V
V
V
0.7 VCC
b 0.3
0.6
V
V
0.7 VCC
b 0.3
0.6
V
V
2.0
2.5
V
3.0
2.0
b 0.3
3.6
b 0.3
0.8
V
V
V
V
V
7
pF
b1
a1
mA
0.4
V
V
0.2
V
V
Input Voltage Levels
CKI Input Levels
Ceramic Resonator Input ( d 8)
Logic High (VIH)
Logic High (VIH)
Logic Low (VIL)
VCC e Max
VCC e 5V g 5%
Schmitt Trigger Input ( d 4)
Logic High (VIH)
Logic Low (VIL)
RESET Input Levels
Logic High
Logic Low
(Schmitt Trigger Input)
SO Input Level (Test Mode)
(Note 2)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
VCC e Max
With TTL Trip Level Options
Selected, VCC e 5V g 5%
With High Trip Level Options
Selected
Input Capacitance (Note 4)
Hi-Z Input Leakage
1.2
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (VOL)
VCC e 5V g 10%
IOH e b25 mA
IOL e 0.36 mA
2.7
CMOS Operation (Note 3)
Logic High
Logic Low
IOH e b10 mA
IOL e a 10 mA
VCC b 1
Note 1: VCC voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: SO output ‘‘0’’ level must be less than 0.8V for normal operation.
Note 3: TRI-STATEÉ and LED configurations are excluded.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
2
COP410L/COP411L
DC Electrical Characteristics 0§ C s TA s a 70§ C, 4.5V s VCC s 6.3V unless otherwise noted (Continued)
Parameter
Conditions
Min
Max
Units
Output Current Levels
Output Sink Current
SO and SK Outputs (IOL)
L0 – L7 Outputs, G0 – G3 and
LSTTL D0 – D3 Outputs (IOL)
VCC e 6.3V, VOL
VCC e 4.5V, VOL
VCC e 6.3V, VOL
VCC e 4.5V, VOL
e 0.4V
e 0.4V
0.4
0.4
mA
mA
D0 – D3 Outputs with High
Current Options (IOL)
VCC e 6.3V, VOL e 1.0V
VCC e 4.5V, VOL e 1.0V
11
7.5
mA
mA
D0 – D3 Outputs with Very
High Current Options (IOL)
VCC e 6.3V, VOL e 1.0V
VCC e 4.5V, VOL e 1.0V
VCC e 4.5V, VIH e 3.5V
VCC e 4.5V, VOL e 0.4V
22
15
mA
mA
2
0.2
mA
mA
CKI (Single-Pin RC Oscillator)
CKO
e 0.4V
e 0.4V
1.2
0.9
mA
mA
Output Source Current
e 2.0V
e 2.0V
b 75
b 30
e 2.4V
e 1.0V
b 1.4
b 1.2
LED Configuration, L0 – L7
Outputs, Low Current
Driver Option (IOH)
VCC e 6.0V, VOH e 2.0V
b 1.5
b 13
mA
LED Configuration, L0 – L7
Outputs, High Current
Driver Option (IOH)
VCC e 6.0V, VOH e 2.0V
b 3.0
b 25
mA
TRI-STATE Configuration,
L0 – L7 Outputs, Low
Current Driver Option (IOH)
VCC e 6.3V, VOH e 3.2V
VCC e 4.5V, VOH e 1.5V
b 0.8
b 0.9
mA
mA
TRI-STATE Configuration,
L0 – L7 Outputs, High
Current Driver Option (IOH)
VCC e 6.3V, VOH e 3.2V
VCC e 4.5V, VOH e 1.5V
b 1.6
b 1.8
mA
mA
VCC e 5.0V, VIL e 0V
b 10
Standard Configuration,
All Outputs (IOH)
Push-Pull Configuration
SO and SK Outputs (IOH)
VCC e 6.3V, VOH
VCC e 4.5V, VOH
VCC e 6.3V, VOH
VCC e 4.5V, VOH
b 480
b 250
mA
mA
mA
mA
b 140
mA
1.5
mA
a 2.5
mA
Total Sink Current Allowed
All Outputs Combined
D Port
L7 – L4, G Port
L3 – L0
Any Other Pin
100
100
4
4
2.0
mA
mA
mA
mA
mA
Total Source Current Allowed
All I/O Combined
L7 – L4
L3 – L0
Each L Pin
Any Other Pin
120
60
60
25
1.5
mA
mA
mA
mA
mA
Input Load Source Current
CKO Output
RAM Power Supply Option
Power Requirement
VR e 3.3V
TRI-STATE Output Leakage
Current
b 2.5
3
COP310L/COP311L
Absolute Maximum Ratings
Power Dissipation
COP310L
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 0.5V to a 10V
Voltage at Any Pin Relative to GND
Ambient Operating Temperature
Ambient Storage Temperature
Lead Temperature
(Soldering, 10 seconds)
0.75W at 25§ C
0.25W at 85§ C
COP311L
0.65W at 25§ C
0.20W at 85§ C
Total Source Current
120 mA
Total Sink Current
100 mA
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
b 40§ C to a 85§ C
b 65§ C to a 150§ C
300§ C
DC Electrical Characteristics b40§ C s TA s a 85§ C, 4.5V s VCC s 5.5V unless otherwise noted
Parameter
Conditions
Standard Operating Voltage (VCC)
Power Supply Ripple (Notes 1, 4)
Peak to Peak
Operating Supply Current
All Inputs and Outputs Open
Min
Max
Units
4.5
5.5
V
0.5
V
8
mA
3.0
2.2
b 0.3
0.3
V
V
V
0.7 VCC
b 0.3
0.4
V
V
0.7 VCC
b 0.3
0.4
V
V
2.2
2.5
V
3.0
2.2
b 0.3
3.6
b 0.3
0.6
V
V
V
V
V
7
pF
b2
a2
mA
0.4
V
V
0.2
V
V
Input Voltage Levels
Ceramic Resonator Input ( d 8)
Crystal Input
Logic High (VIH)
Logic High (VIH)
Logic Low (VIL)
VCC e Max
VCC e 5V g 5%
Schmitt Trigger Input ( d 4)
Logic High (VIH)
Logic Low (VIL)
RESET Input Levels
Logic High
Logic Low
(Schmitt Trigger Input)
SO Input Level (Test Mode)
(Note 2)
All Other Inputs
Logic High
Logic High
Logic Low
Logic High
Logic Low
VCC e Max
With TTL Trip Level Options
Selected, VCC e 5V g 5%
With High Trip Level Options
Selected
Input Capacitance (Note 4)
Hi-Z Input Leakage
1.2
Output Voltage Levels
LSTTL Operation
Logic High (VOH)
Logic Low (VOL)
VCC e 5V g 10%
IOH e b20 mA
IOL e 0.36 mA
2.7
CMOS Operation (Note 3)
Logic High
Logic Low
IOH e b10 mA
IOL e a 10 mA
VCC b 1
Note 1: VCC voltage change must be less than 0.5V in a 1 ms period to maintain proper operation.
Note 2: SO output ‘‘0’’ level must be less than 0.6V for normal operation.
Note 3: TRI-STATE and LED configurations are excluded.
Note 4: This parameter is only sampled and not 100% tested. Variation due to the device included.
4
COP310L/COP311L
DC Electrical Characteristics
(Continued)
b 40§ C s TA s a 85§ C, 4.5V s VCC s 5.5V unless othewise noted
Parameter
Conditions
Min
Max
Units
SO and SK Outputs (IOL)
VCC e 5.5V, VOL e 0.4V
VCC e 4.5V, VOL e 0.4V
1.0
0.8
mA
mA
L0 – L7 Outputs, G0 – G3 and
LSTTL D0 – D3 Outputs (IOL)
e 0.4V
e 0.4V
0.4
0.4
mA
mA
D0 – D3 Outputs with High
Current Options (IOL)
VCC e 5.5V, VOL
VCC e 4.5V, VOL
VCC e 5.5V, VOL
VCC e 4.5V, VOL
e 1.0V
e 1.0V
9
7
mA
mA
D0 – D3 Outputs with Very
High Current Options (IOL)
VCC e 5.5V, VOL e 1.0V
VCC e 4.5V, VOL e 1.0V
18
14
mA
mA
CKI (Single-Pin RC Oscillator)
CKO
VCC e 4.5V, VIH e 3.5V
VCC e 4.5V, VOL e 0.4V
1.5
0.2
mA
mA
Standard Configuration,
All Outputs (IOH)
VCC e 5.5V, VOH e 2.0V
VCC e 4.5V, VOH e 2.0V
b 55
b 28
Push-Pull Configuration
SO and SK Outputs (IOH)
VCC e 5.5V, VOH e 2.0V
VCC e 4.5V, VOH e 1.0V
VCC e 5.5V, VOH e 2.0V
b 1.1
b 1.2
b 0.7
b 15
mA
LED Configuration, L0 – L7
Outputs, High Current
Driver Option (IOH)
VCC e 5.5V, VOH e 2.0V
b 1.4
b 30
mA
TRI-STATE Configuration,
L0 – L7 Outputs, Low
Current Driver Option (IOH)
VCC e 5.5V, VOH e 2.7V
VCC e 4.5V, VOH e 1.5V
b 0.6
b 0.9
mA
mA
TRI-STATE Configuration,
L0 – L7 Outputs, High
Current Driver Option (IOH)
VCC e 5.5V, VOH e 2.7V
VCC e 4.5V, VOH e 1.5V
b 1.2
b 1.8
mA
mA
Input Load Source Current
VCC e 5.0V, VIL e 0V
b 10
CKO Output
RAM Power Supply Option
Power Requirement
VR e 3.3V
Output Current Levels
Output Sink Current
Output Source Current
LED Configuration, L0 – L7
Outputs, Low Current
Driver Option (IOH)
b 600
b 350
mA
mA
mA
mA
b 200
mA
2.0
mA
a5
mA
All Outputs Combined
100
mA
D Port
100
mA
4
mA
4
mA
1.5
mA
TRI-STATE Output Leakage
Current
b5
Total Sink Current Allowed
L7 – L4, G Port
L3 – L0
Any Other Pins
Total Source Current Allowed
All I/O Combined
120
mA
L7 – L4
60
mA
L3 – L0
60
mA
Each L Pin
25
mA
Any Other Pins
1.5
mA
5
AC Electrical Characteristics
COP410L/411L: 0§ C s TA s 70§ C, 4.5V s VCC s 6.3V unless otherwise noted
COP310L/311L: b40§ C s TA s a 85§ C, 4.5V s VCC s 5.5V unless otherwise noted
Parameter
Conditions
Instruction Cycle Time Ð tC
CKI
Input Frequency Ð fI
d 8 Mode
d 4 Mode
Duty Cycle
Rise Time (Note 1)
Fall Time (Note 1)
fI e 0.5 MHz
CKI Using RC ( d 4)
(Note 1)
R e 56 kX g 5%
C e 100 pF g 10%
Min
Max
Units
16
40
ms
0.2
0.1
30
0.5
0.25
60
500
200
MHz
MHz
%
ns
ns
16
28
ms
Instruction Cycle Time
CKO as SYNC Input
tSYNC
400
ns
INPUTS
G3 – G0, L7 – L0
tSETUP
tHOLD
8.0
1.3
ms
ms
2.0
1.0
ms
ms
SI
tSETUP
tHOLD
OUTPUT PROPAGATION DELAY
Test Condition:
CL e 50 pF, RL e 20 kX, VOUT e 1.5V
SO, SK Outputs
tpd1, tpd0
4.0
ms
All Other Outputs
tpd1, tpd0
5.6
ms
Note 1: This parameter is only sampled and not 100% tested.
Connection Diagrams
DIP
DIP
TL/DD/6919 – 3
Top View
TL/DD/6919–2
Top View
Order Number COP311L-XXX/D or COP411L-XXX/D
See NS Hermetic Package Number D20A
Order Number COP310L-XXX/D or COP410L-XXX/D
(D Pkg.Ðfor Prototypes Only)
See NS Hermetic Package Number D24C
(D Pkg.Ðfor Prototypes Only)
Order Number COP311L-XXX/N or COP411L-XXX/N
See NS Molded Package Number N20A
Order Number COP310L-XXX/N or COP410L-XXX/N
See NS Molded Package Number N24A
FIGURE 2
Pin Descriptions
Pin
L 7 – L0
G 3 – G0
D 3 – D0
SI
SO
SK
Pin
CKI
CKO
Description
System oscillator input
System oscillator output (or RAM power supply or
SYNC input) (COP410L only)
RESET System reset input
VCC
Power supply
GND
Ground
Description
8 bidirectional I/O ports with TRI-STATE
4 bidirectional I/O ports (G2 – G0 for COP411L)
4 general purpose outputs (D1 – D0 for COP411L)
Serial input (or counter input)
Serial output (or general purpose output)
Logic-controlled clock (or general purpose output)
6
Timing Diagrams
TL/DD/6919 – 4
FIGURE 3. Input/Output Timing Diagrams (Ceramic Resonator Divide-by-8 Mode)
TL/DD/6919 – 5
FIGURE 3a. Synchronization Timing
Functional Description
A block diagram of the COP410L is given in Figure 1 . Data
paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. Positive logic is
used. When a bit is set, it is a logic ‘‘1’’ (greater than 2V).
When a bit is reset, it is a logic ‘‘0’’ (less than 0.8V).
All functional references to the COP410L/COP411L also
apply to the COP310L/COP311L.
may also be loaded into the Q latches or loaded from the L
ports. RAM addressing may also be performed directly by
the XAD 3,15 instruction. The Bd register also serves as a
source register for 4-bit data sent directly to the D outputs.
The most significant bit of Bd is not used to select a RAM
digit. Hence each physical digit of RAM may be selected by
two different values of Bd as shown in Figure 4 below. The
skip condition for XIS and XDS instructions will be true if Bd
changes between 0 and 15, but NOT between 7 and 8 (see
Table III).
PROGRAM MEMORY
Program Memory consists of a 512-byte ROM. As can be
seen by an examination of the COP410L/411L instruction
set, these words may be program instructions, program data
or ROM addressing data. Because of the special characteristics associated with the JP, JSRP, JID and LQID instructions, ROM must often be thought of as being organized into
8 pages of 64 words each.
ROM addressing is accomplished by a 9-bit PC register. Its
binary value selects one of the 512 8-bit words contained in
ROM. A new address is loaded into the PC register during
each instruction cycle. Unless the instruction is a transfer of
control instruction, the PC register is loaded with the next
sequential 9-bit binary count value. Two levels of subroutine
nesting are implemented by the 9-bit subroutine save registers, SA and SB, providing a last-in, first-out (LIFO) hardware subroutine stack.
ROM instruction words are fetched, decoded and executed
by the Instruction Decode, Control and Skip Logic circuitry.
DATA MEMORY
Data memory consists of a 128-bit RAM, organized as 4
data registers of 8 4-bit digits. RAM addressing is implemented by a 6-bit B register whose upper 2 bits (Br) select 1
of 4 data registers and lower 3 bits of the 4-bit Bd select 1 of
8 4-bit digits in the selected data register. While the 4-bit
contents of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it
*Can be directly addressed by
LBI instruction (see Table III)
TL/DD/6919 – 6
FIGURE 4. RAM Digit Address to
Physical RAM Digit Mapping
7
Functional Description (Continued)
each low-going pulse (‘‘1’’ to ‘‘0’’) occurring on the SI
input. Each pulse must be at least two instruction cycles
wide. SK outputs the value of SKL. The SO output is
equal to the value of EN3. With EN0 reset, SIO is a serial
shift register shifting left each instruction cycle time. The
data present at SI goes into the least significant bit of
SIO. SO can be enabled to output the most significant bit
of SIO each cycle time. (See 4 below.) The SK output
becomes a logic-controlled clock.
2. EN1 is not used. It has no effect on COP410L/COP411L
operation.
3. With EN2 set, the L drivers are enabled to output the data
in Q to the L I/O ports. Resetting EN2 disables the L
drivers, placing the L I/O ports in a high-impedance input
state.
4. EN3, in conjunction with EN0, affects the SO output. With
EN0 set (binary counter option selected) SO will output
the value loaded into EN3. With EN0 reset (serial shift
register option selected), setting EN3 enables SO as the
output of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with the serial
shift register option selected disables SO as the shift register output; data continues to be shifted through SIO and
can be exchanged with A via an XAS instruction but SO
remains reset to ‘‘0.’’ Table I provides a summary of the
modes associated with EN3 and EN0.
INTERNAL LOGIC
The 4-bit A register (accumulator) is the source and destination register for most I/O, arithmetic, logic and data memory
access operations. It can also be used to load the Bd portion of the B register, to load 4 bits of the 8-bit Q latch data,
to input 4 bits of the 8-bit L I/O port data and to perform
data exchanges with the SIO register.
A 4-bit adder performs the arithmetic and logic functions of
the COP410L/411L, storing its results in A. It also outputs a
carry bit to the 1-bit C register, most often employed to indicate arithmetic overflow. The C register, in conjunction with
the XAS instruction and the EN register, also serves to control the SK output. C can be outputted directly to SK or can
enable SK to be a sync clock each instruction cycle time.
(See XAS instruction and EN register description, below.)
The G register contents are outputs to 4 general-purpose
bidirectional I/O ports.
The Q register is an internal, latched, 8-bit register, used to
hold data loaded from M and A, as well as 8-bit data from
ROM. Its contents are output to the L I/O ports when the L
drivers are enabled under program control. (See LEI instruction.)
The 8 L drivers, when enabled, output the contents of
latched Q data to the L I/O ports. Also, the contents of L
may be read directly into A and M. L I/O ports can be directly connected to the segments of a multiplexed LED display
(using the LED Direct Drive output configuration option) with
Q data being outputted to the Sa–Sg and decimal point
segments of the display.
The SIO register functions as a 4-bit serial-in serial-out shift
register or as a binary counter depending on the contents of
the EN register. (See EN register description, below.) Its
contents can be exchanged with A, allowing it to input or
output a continuous serial data stream. SIO may also be
used to provide additional parallel I/O by connecting SO to
external serial-in/parallel-out shift registers.
The XAS instruction copies C into the SKL Latch. In the
counter mode, SK is the output of SKL in the shift register
mode, SK outputs SKL ANDed with internal instruction cycle
clock.
The EN register is an internal 4-bit register loaded under
program control by the LEI instruction. The state of each bit
of this register selects or deselects the particular feature
associated with each bit of the EN register (EN3 – EN0).
1. The least significant bit of the enable register, EN0, selects the SIO register as either a 4-bit shift register or a
4-bit binary counter. With EN0 set, SIO is an asynchronous binary counter, decrementing its value by one upon
INITIALIZATION
The Reset Logic will initialize (clear) the device upon powerup if the power supply rise time is less than 1 ms and greater than 1 ms. If the power supply rise time is greater than
1 ms, the user must provide an external RC network and
diode to the RESET pin as shown below (Figure 5) . The
RESET pin is configured as a Schmitt trigger input. If not
used it should be connected to VCC. Initialization will occur
whenever a logic ‘‘0’’ is applied to the RESET input, provided it stays low for at least three instruction cycle times.
RC t 5 c Power Supply Rise Time
TL/DD/6919 – 7
FIGURE 5. Power-Up Clear Circuit
TABLE I. Enable Register ModesÐBits EN3 and EN0
EN3
EN0
SIO
0
0
Shift Register
Input to Shift Register
SI
0
1
0
Shift Register
Input to Shift Register
Serial Out
0
1
Binary Counter
Input to Binary Counter
0
1
1
Binary Counter
Input to Binary Counter
1
8
SO
SK
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
If SKL
e
e
e
e
e
e
e
e
1, SK
0, SK
1, SK
0, SK
1, SK
0, SK
1, SK
0, SK
e
e
e
e
e
e
e
e
Clock
0
Clock
0
1
0
1
0
Functional Description (Continued)
Upon initialization, the PC register is cleared to 0 (ROM address 0) and the A, B, C, D, EN, and G registers are cleared.
The SK output is enabled as a SYNC output, providing a
pulse each instruction cycle time. Data Memory (RAM) is
not cleared upon initialization. The first instruction at address 0 must be a CLRA.
CKO PIN OPTIONS
In a resonator controlled oscillator system, CKO is used as
an output to the resonator network. As an option, CKO can
be a RAM power supply pin (VR), allowing its connection to
a standby/backup power supply to maintain the integrity of
RAM data with minimum power drain when the main supply
is inoperative or shut down to conserve power. Using no
connection option is appropriate in applications where the
COP410L system timing configuration does not require use
of the CKO pin.
RAM KEEP-ALIVE OPTION
Selecting CKO as the RAM power supply (VR) allows the
user to shut off the chip power supply (VCC) and maintain
data in the RAM. To insure that RAM data integrity is maintained, the following conditions must be met:
1. RESET must go low before VCC goes below spec during
power-off; VCC must be within spec before RESET goes
high on power-up.
2. During normal operation, VR must be within the operating
range of the chip with (VCC b 1) s VR s VCC.
3. VR must be t 3.3V with VCC off.
I/O OPTIONS
COP410L/411L inputs and outputs have the following optional configurations, illustrated in Figure 7 :
TL/DD/6919 – 8
a. StandardÐan enhancement-mode device to ground in
conjunction with a depletion-mode device to VCC, compatible with LSTTL and CMOS input requirements. Available on SO, SK, and all D and G outputs.
b. Open-DrainÐan enhancement-mode device to ground
only, allowing external pull-up as required by the user’s
application. Available on SO, SK, and all D and G outputs.
c. Push-PullÐan enhancement-mode device to ground in
conjunction with a depletion-mode device paralleled by
an enhancement-mode device to VCC. This configuration
has been provided to allow for fast rise and fall times
when driving capacitive loads. Available on SO and SK
outputs only.
d. Standard LÐsame as a., but may be disabled. Available
on L outputs only.
e. Open Drain LÐsame as b., but may be disabled. Available on L outputs only.
f. LED Direct DriveÐan enhancement mode device to
ground and to VCC, meeting the typical current sourcing
requirements of the segments of an LED display. The
sourcing device is clamped to limit current flow. These
devices may be turned off under program control (see
Functional Description, EN Register), placing the outputs
in a high-impedance state to provide required LED segment blanking for a multiplexed display. Available on L
outputs only.
Ceramic Resonator Oscillator
Resonator
Value
455 kHz
Components Values
R1 (X)
R2 (X)
C1 (pF)
C2 (pF)
4.7k
1M
220
220
RC Controlled Oscillator
R (kX)
C (pF)
Instruction
Cycle Time
in ms
51
82
100
56
19 g 15%
19 g 13%
Note: 200 kX t R t 25 kX. 360 pF t C t 50 pF. Does not include tolerances.
FIGURE 6. COP410L/411L Oscillator
OSCILLATOR
There are three basic clock oscillator configurations available as shown by Figure 6 .
a. Resonator Controlled Oscillator. CKI and CKO are
connected to an external ceramic resonator. The instruction cycle frequency equals the resonator frequency divided by 8. This is not available in the COP411L.
b. External Oscillator. CKI is an external clock input signal.
The external frequency is divided by 4 to give the instruction frequency time. CKO is now available to be used as
the RAM power supply (VR), or no connection.
Note: No CKO on COP411L.
Note: Series current limiting resistors must be used if LEDs are driven directly and higher operating voltage option is selected.
c. RC Controlled Oscillator. CKI is configured as a single
pin RC controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4.
CKO is available as the RAM power supply (VR) or no
connection.
g. TRI-STATE Push-PullÐan enhancement-mode device
to ground and VCC. These outputs are TRI-STATE outputs, allowing for connection of these outputs to a data
bus shared by other bus drivers. Available on L outputs
only.
9
Functional Description (Continued)
h. An on-chip depletion load device to VCC.
i. A Hi-Z input which must be driven to a ‘‘1’’ or ‘‘0’’ by
external components.
The above input and output configurations share common
enhancement-mode and depletion-mode devices. Specifically, all configurations use one or more of six devices
(numbered 1 – 6, respectively). Minimum and maximum current (IOUT and VOUT) curves are given in Figure 8 for each
of these devices to allow the designer to effectively use
these I/O configurations in designing a COP410L/411L system.
The SO, SK outputs can be configured as shown in a., b., or
c. The D and G outputs can be configured as shown in a. or
b. Note that when inputting data to the G ports, the G outputs should be set to ‘‘1’’. The L outputs can be configured
as in d., e., f., or g.
a. Standard Output
An important point to remember if using configuration d. or
f. with the L drivers is that even when the L drivers are
disabled, the depletion load device will source a small
amount of current. (See Figure 8 , device 2.) However, when
the L port is used as input, the disabled depletion device
CANNOT be relied on to source sufficient current to pull an
input to a logic ‘‘1’’.
COP411L
If the COP410L is bonded as a 20-pin device, it becomes
the COP411L, illustrated in Figure 2, COP410L/411L Connection Diagrams. Note that the COP411L does not contain
D2, D3, G3, or CKO. Use of this option of course precludes
use of D2, D3, G3, and CKO options. All other options are
available for the COP411L.
b. Open-Drain Output
c. Push-Pull Output
TL/DD/6919 – 10
TL/DD/6919–9
d. Standard L Output
TL/DD/6919 – 11
e. Open-Drain L Output
f. LED (L Output)
TL/DD/6919 – 13
TL/DD/6919–12
( U is depletion device)
g. TRI-STATE Push-Pull (L Output)
h. Input with Load
TL/DD/6919 – 14
i. Hi-Z Input
TL/DD/6919 – 17
TL/DD/6919 – 16
TL/DD/6919–15
FIGURE 7. Input and Output Configurations
10
L-Bus Considerations
In this program the internal Q register is enabled onto the L
lines and a steady bit pattern of logic highs is output on L0,
L1, L6, L7, and logic lows on L2 –L5 via the two-byte CAMQ
instruction. Timing constraints on the device are such that
the Q register may be temporarily loaded with the second
byte of the CAMQ opcode (XÊ 3C) prior to receiving the valid
data pattern. If this occurs, the opcode will ripple onto the L
lines and cause negative-going glitches on L0, L1, L6, L7,
and positive glitches on L2 –L5. Glitch durations are under
2 ms, although the exact value may vary due to data patterns, processing parameters, and L line loading. These
false states are peculiar only to the CAMQ instruction and
the L lines.
False states may be generated on L0 – L7 during the execution of the CAMQ instruction. The L-ports should not be
used as clocks for edge sensitive devices such as flip-flops,
counters, shift registers, etc. the following short program
that illustrates this situation.
START:
CLRA
;ENABLE THE Q
LEI 4
;REGISTER TO L LINES
LBI TEST
STII 3
AISC 12
LOOP:
LBI TEST ;LOAD Q WITH X’C3
CAMQ
JP
LOOP
Typical Performance Characteristics
Input Current RESET, SI
Input Current for L0 through
L7 when Output Programmed
Off by Software
Source Current for Standard
Output Configuration
Source Current for SO
and SK in Push-Pull
Configuration
Source Current for L0 through
L7 in TRI-STATE Configuration
(High Current Option)
Source Current for L0 through
L7 in TRI-STATE Configuration
(Low Current Option)
TL/DD/6919 – 18
FIGURE 8a. COP410L/COP411L I/O DC Current Characteristics
11
Typical Performance Characteristics
(Continued)
LED Output Source Current
(for High Current LED Option)
LED Output Source Current
(for Low Current LED Option)
LED Output Direct Segment
and Direct Drive High
Current Options on L0 – L7
Very High Current Options
on D0 – D3
LED Output Direct
Segment Drive
Output Sink Current for SO
and SK
Output Sink Current for L0 – L7
and Standard Drive Option for
D0 –D3 and G0 –G3
Output Sink Current for D0 – D3
with Very High Current Option
Output Sink Current for
D0 – D3 (for High Current
Option)
TL/DD/6919 – 19
FIGURE 8a. COP410L/COP411L I/O DC Current Characteristics (Continued)
12
Typical Performance Characteristics
(Continued)
Input Current RESET, SI
Input Current for L0 – L7
when Output Programmed
Off by Software
Source Current for
Standard Output
Configuration
Source Current for SO
and SK in Push-Pull
Configuration
Source Current for L0 – L7
in TRI-STATE Configuration
(High Current Option)
Source Current for L0 – L7
in TRI-STATE Configuration
(Low Current Option)
LED Output Source
Current (for Low Current
LED Option)
LED Output Source
Current (for High Current
LED Option)
Output Sink Current for
SO and SK
Output Sink Current for
L0–L7 and Standard Drive
Option for D0–D3 and G0–G3
Output Sink Current
for D0 – D3 with Very High
Current Option
Output Sink Current
for D0 – D3 (for
High Current Option)
TL/DD/6919 – 20
FIGURE 8b. COP310L/COP311L Input/Output Characteristics
13
COP410L/411L Instruction Set
Table III provides the mnemonic, operand, machine code,
data flow, skip conditions and description associated with
each instruction in the COP410L/411L instruction set.
Table II is a symbol table providing internal architecture, instruction operand and operational symbols used in the instruction set table.
TABLE II. COP410L/411L Instruction Set Table Symbols
Symbol
Definition
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
INSTRUCTION OPERAND SYMBOLS
A
B
Br
Bd
C
D
EN
G
L
M
d
r
PC
Q
SA
SB
SIO
SK
4-bit Accumulator
6-bit RAM Address Register
Upper 2 bits of B (register address)
Lower 4 bits of B (digit address)
1-bit Carry Register
4-bit Data Output Port
4-bit Enable Register
4-bit Register to latch data for G I/O Port
8-bit TRI-STATE I/O Port
4-bit contents of RAM Memory pointed to by B
Register
9-bit ROM Address Register (program counter)
8-bit Register to latch data for L I/O Port
9-bit Subroutine Save Register A
9-bit Subroutine Save Register B
4-bit Shift Register and Counter
Logic-Controlled Clock Output
4-bit Operand Field, 0 – 15 binary (RAM Digit Select)
2-bit Operand Field, 0 – 3 binary (RAM Register
Select)
a
9-bit Operand Field, 0 – 511 binary (ROM Address)
y
4-bit Operand Field, 0 – 15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
a
b
x
Ý
e
A
Z
:
Plus
Minus
Replaces
Is exchanged with
Is equal to
The one’s complement of A
Exclusive-OR
Range of values
TABLE III. COP410L/411L Instruction Set
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
ARITHMETIC INSTRUCTIONS
ASC
30
À 0011 À 0000 À
A a C a RAM(B)
Carry x C
ADD
31
À 0011 À 0001 À
A a RAM(B)
5–
À 0101 À
Aay
CLRA
00
À 0000 À 0000 À
0
COMP
40
À 0100 À 0000 À
A
NOP
44
À 0100 À 0100 À
None
RC
32
À 0011 À 0010 À
‘‘0’’
SC
22
À 0010 À 0010 À
XOR
02
À 0000 À 0010 À
AISC
y
y
À
xA
Carry
Add with Carry, Skip on
Carry
None
Add RAM to A
Carry
Add Immediate, Skip on
Carry (y i 0)
xA
None
Clear A
xA
None
One’s complement of A to A
None
No Operation
xC
None
Reset C
‘‘1’’
xC
None
Set C
A
RAM(B)
None
Exclusive-OR RAM with A
Z
xA
xA
14
xA
Instruction Set (Continued)
TABLE III. COP410L/411L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
TRANSFER OF CONTROL INSTRUCTIONS
JID
FF
À 1111 À 1111 À
ROM (PC8,A,M)
PC7:0
x
None
Jump Indirect (Note 2)
JMP
a
6–
– –
À 0110 À 000 À a8 À
a7:0
À
À
a
x PC
None
Jump
JP
a
– –
a6:0
À1À
À
(pages 2,3 only)
or
a5:0
À 11 À
À
(all other pages)
a
x PC6:0
None
Jump within Page
(Note 3)
a
x PC5:0
x SA x SB
010 x PC8:6
a x PC5:0
PC a 1 x SA x SB
a x PC
SB x SA x PC
SB x SA x PC
None
Jump to Subroutine Page
(Note 4)
None
Jump to Subroutine
None
Return from Subroutine
Always Skip on Return
Return from Subroutine
then Skip
– –
a5:0
JSRP
a
– –
À 10 À
JSR
a
6–
– –
À 0110 À 100 À a8 À
a7:0
À
À
RET
48
À 0100 À 1000 À
RETSK
49
À 0100 À 1001 À
À
PC a 1
MEMORY REFERENCE INSTRUCTIONS
CAMQ
LD
r
LQID
33
3C
À 0011 À 0011 À
À 0011 À 1100 À
A x Q7:4
RAM(B) x Q3:0
None
Copy A, RAM to Q
–5
À 00 À r À 0101 À
RAM(B) x A
Br Z r x Br
None
Load RAM into A,
Exclusive-OR Br with r
BF
À 1011 À 1111 À
ROM(PC8,A,M)
SA x SB
None
Load Q Indirect (Note 2)
0
0
0
0
x RAM(B)0
x RAM(B)1
x RAM(B)2
x RAM(B)3
1 x RAM(B)0
1 x RAM(B)1
1 x RAM(B)2
1 x RAM(B)3
y x RAM(B)
Bd a 1 x Bd
RAM(B) Ý A
Br Z r x Br
RAM(3,15) Ý A
None
Reset RAM Bit
None
Set RAM Bit
None
Store Memory Immediate
and Increment Bd
None
Exchange RAM with A,
Exclusive-OR Br with r
None
Exchange A with RAM
(3,15)
xQ
RMB
0
1
2
3
4C
45
42
43
À 0100 À 1100 À
À 0100 À 0101 À
À 0100 À 0010 À
À 0100 À 0011 À
SMB
0
1
2
3
4D
47
46
4B
À 0100 À 1101 À
À 0100 À 0111 À
À 0100 À 0110 À
À 0100 À 1011 À
STII
y
7–
À 0111 À
X
r
–6
À 00 À r À 0110 À
XAD
3,15
23
BF
À 0010 À 0011 À
À 1011 À 1111 À
XDS
r
–7
À 00 À r À 0111 À
RAM(B) Ý A
Bd – 1 x Bd
Br Z r x Br
Bd decrements past 0
Exchange RAM with A
and Decrement Bd,
Exclusive-OR Br with r
XIS
r
–4
À 00 À r À 0100 À
RAM(B) Ý A
Bd a 1 x Bd
Br Z r x Br
Bd increments past 15
Exchange RAM with A
and Increment Bd
Exclusive-OR Br with r
y
À
15
Instruction Set (Continued)
TABLE III. COP410L/411L Instruction Set (Continued)
Mnemonic
Operand
Hex
Code
Machine
Language Code
(Binary)
Data Flow
Skip Conditions
Description
REGISTER REFERENCE INSTRUCTIONS
x Bd
None
Copy A to Bd
Bd
xA
None
Copy Bd to A
r,d
xB
Skip until not a LBI
Load B Immediate with
r,d (Note 5)
None
Load EN Immediate
(Note 6)
CAB
50
À 0101 À 0000 À
A
CBA
4E
À 0100 À 1110 À
LBI
r,d
– –
À 00 À r À (d b 1) À
(d e 0,9:15)
LEI
y
33
6–
À 0011 À 0011 À
À 0110 À y À
SKC
20
À 0010 À 0000 À
C e ‘‘1’’
Skip if C is True
SKE
21
À 0010 À 0001 À
A e RAM(B)
Skip if A Equals RAM
SKGZ
33
21
À 0011 À 0011 À
À 0010 À 0001 À
G3:0 e 0
Skip if G is Zero
(all 4 bits)
0
1
2
3
33
01
11
03
13
À 0011 À 0011 À
À 0000 À 0001 À
À 0001 À 0001 À
À 0000 À 0011 À
À 0001 À 0011 À
0
1
2
3
01
11
03
13
À 0000 À 0001 À
À 0001 À 0001 À
À 0000 À 0011 À
À 0001 À 0011 À
y
x EN
TEST INSTRUCTIONS
SKGBZ
SKMBZ
1st byte
*
2nd byte
Skip if G Bit is Zero
G0
G1
G2
G3
e
e
e
e
0
0
0
0
RAM(B)0
RAM(B)1
RAM(B)2
RAM(B)3
e
e
e
e
0
0
0
0
Skip if RAM Bit is Zero
INPUT/OUTPUT INSTRUCTIONS
xA
ING
33
2A
À 0011 À 0011 À
À 0010 À 1010 À
G
INL
33
2E
À 0011 À 0011 À
À 0010 À 1110 À
L7:4
L3:0
OBD
33
3E
À 0011 À 0011 À
À 0011 À 1110 À
Bd
OMG
33
3A
À 0011 À 0011 À
À 0011 À 1010 À
RAM(B)
XAS
4F
À 0100 À 1111 À
A
x RAM(B)
xA
xD
xG
Ý SIO, C x SKL
None
Input G Ports to A
None
Input L Ports to RAM, A
None
Output Bd to D Outputs
None
Output RAM to G Ports
None
Exchange A with SIO
(Note 2)
Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., Br and Bd are explicitly defined). Bits are numbered 0 to N where
0 signifies the least significant bit (low-order, right-most bit). For example, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: For additional information on the operation of the XAS, JID, and LQID instructions, see below.
Note 3: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction,
otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page.
Note 4: A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSRP
may not jump to the last word in page 2.
Note 5: The machine code for the lower 4 bits of the LBI instruction equals the binary value of the ‘‘d’’ data minus 1 , e.g., to load the lower four bits of B (Bd) with
the value 9 (10012), the lower 4 bits of the LBI instruction equal 8 (10002). To load 0, the lower 4 bits of the LBI instruction should equal 15 (11112).
Note 6: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds
with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.)
16
Description of Selected Instructions
Option List
The following information is provided to assist the user in
understanding the operation of several unique instructions
and to provide notes useful to programmers in writing
COP410L/411L programs.
The COP410L/411L mask-programmable options are assigned numbers which correspond with the COP410L pins.
The following is a list of COP410L options. The LED Direct
Drive option on the L Lines cannot be used if higher VCC
option is selected. When specifying a COP411L chip, Option
2 must be set to 3, Options 20, 21, and 22 to 0. The options
are programmed at the same time as the ROM pattern to
provide the user with the hardware flexibility to interface to
various I/O components using little or no external circuitry.
Option 1 e 0: Ground Pin Ð no options available
XAS INSTRUCTION
XAS (Exchange A with SIO) exchanges the 4-bit contents of
the accumulator with the 4-bit contents of the SIO register.
The contents of SIO will contain serial-in/serial-out shift register or binary counter data, depending on the value of the
EN register. An XAS instruction will also affect the SK output. (See Functional Description, EN Register, above.) If
SIO is selected as a shift register, an XAS instruction must
be performed once every 4 instruction cycles to effect a
continuous data stream.
Option 2: CKO Output (no option available for COP411L)
e 0: Clock output to ceramic resonator
e 1: Pin is RAM power supply (VR) input
e 3: No connection
Option 3: CKI Input
e 0: Oscillator input divided by 8 (500 kHz max)
e 1: Single-pin RC controlled oscillator divided by 4
e 2: External Schmitt trigger level clock divided by 4
Option 4: RESET Input
e 0: Load device to VCC
e 1: Hi-Z input
Option 5: L7 Driver
e 0: Standard output
e 1: Open-drain output
e 2: High current LED direct segment drive output
e 3: High current TRI-STATE push-pull output
e 4: Low-current LED direct segment drive output
e 5: Low-current TRI-STATE push-pull output
Option 6: L6 Driver
same as Option 5
Option 7: L5 Driver
same as Option 5
Option 8: L4 Driver
same as Option 5
Option 9: Operating voltage
COP41XL
COP31XL
e 0: a 4.5V to a 6.3V
a 4.5V to a 5.5V
Option 10: L3 Driver
same as Option 5
Option 11: L2 Driver
same as Option 5
Option 12: L1 Driver
same as Option 5
Option 13: L0 Driver
same as Option 5
Option 14: SI Input
e 0: load device to VCC
e 1: Hi-Z input
Option 15: SO Driver
e 0: Standard Output
e 1: Open-drain output
e 2: Push-pull output
Option 16: SK Driver
same as Option 15
JID INSTRUCTION
JID (Jump Indirect) is an indirect addressing instruction,
transferring program control to a new ROM location pointed
to indirectly by A and M. It loads the lower 8 bits of the ROM
address register PC with the contents of ROM addressed by
the 9-bit word, PC8, A, M. PC8 is not affected by this instruction.
Note that JID requires 2 instruction cycles to execute.
LQID INSTRUCTION
LQID (Load Q Indirect) loads the 8-bit Q register with the
contents of ROM pointed to by the 9-bit word PC8, A, M.
LQID can be used for table lookup or code conversion such
as BCD to seven-segment. The LQID instruction ‘‘pushes’’
the stack (PC a 1 x SA x SB) and replaces the least
significant 8 bits of PC as follows: A x PC7:4, RAM(B)
x PC3:0, leaving PC8 unchanged. The ROM data pointed
to by the new address is fetched and loaded into the Q
latches. Next, the stack is ‘‘popped’’ (SB x SA x PC),
restoring the saved value of PC to continue sequential program execution. Since LQID pushes SA x SB, the previous contents of SB are lost. Also, when LQID pops the
stack, the previously pushed contents of SA are left in SB.
The net result is that the contents of SA are placed in SB
(SA x SB). Note that LQID takes two instruction cycle
times to execute.
INSTRUCTION SET NOTES
a. The first word of a COP410L/411L program (ROM address 0) must be a CLRA (Clear A) instruction.
b. Although skipped instructions are not executed, one instruction cycle time is devoted to skipping each byte of
the skipped instruction. Thus all program paths except
JID and LQID take the same number of cycle times
whether instructions are skipped or executed. JID and
LQID instructions take 2 cycles if executed and 1 cycle if
skipped.
c. The ROM is organized into 8 pages of 64 words each.
The Program Counter is a 9-bit binary counter, and will
count through page boundaries. If a JP, JSRP, JID or
LQID instruction is located in the last word of a page, the
instruction operates as if it were in the next page. For
example: a JP located in the last word of a page will jump
to a location in the next page. Also, a LQID or JID located
in the last word of page 3 or 7 will access data in the next
group of 4 pages.
17
Option List (Continued)
Option 17: G0 I/O Port
e 0: Standard output
e 1: Open-drain output
Option 18: G1 I/O Port
same as Option 17
Option 19: G2 I/O Port
same as Option 17
Option 20: G3 I/O Port (no option available for COP411L)
same as Option 17
Option 21: D3 Output (no option available for COP411L)
e 0: Very-high sink current standard output
e 1: Very-high sink current open-drain output
e 2: High sink current standard output
e 3: High sink current open-drain output
e 4: Standard LSTTL output (fanout e 1)
e 5: Open-drain LSTTL output (fanout e 1)
Option 22: D2 Output (no option available for COP411L)
same as Option 21
Option 23: D1 Output
same as Option 21
Option 24: D0 Output
same as Option 21
Option 25: L Input Levels
e 0: Standard TTL input levels (‘‘0’’ e 0.8V, ‘‘1’’ e 2.0V)
e 1: Higher voltage input levels (‘‘0’’ e 1.2V, ‘‘1’’ e 3.6V)
Option 26: G Input Levels
same as Option 25
Option 27: SI Input Levels
same as Option 25
Option 28: COP Bonding
e 0: COP410L (24-pin device)
e 1: COP411L (20-pin device)
e 2: Both 24- and 20-pin versions
TEST MODE (NON-STANDARD OPERATION)
The SO output has been configured to provide for standard
test procedures for the custom-programmed COP410L.
With SO forced to logic ‘‘1’’, two test modes are provided,
depending upon the value of SI:
a. RAM and Internal Logic Test Mode (SI e 1)
b. ROM Test Mode (SI e 0)
These special test modes should not be employed by the
user; they are intended for manufacturing test only.
Option Table
The following option information is to be sent to National along with the EPROM.
OPTION 1 VALUE e
Option Data
0
OPTION 2 VALUE e
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
3 VALUE
4 VALUE
5 VALUE
6 VALUE
7 VALUE
8 VALUE
9 VALUE
10 VALUE
11 VALUE
12 VALUE
13 VALUE
14 VALUE
e
e
e
e
e
e
e
e
e
e
e
e
0
Option Data
IS: GROUND PIN
OPTION 15 VALUE e
IS: SO DRIVER
IS: CKO PIN
IS: CKI INPUT
IS: RESET INPUT
IS: L(7) DRIVER
IS: L(6) DRIVER
IS: L(5) DRIVER
IS: L(4) DRIVER
IS: VCC PIN
IS: L(3) DRIVER
IS: L(2) DRIVER
IS: L(1) DRIVER
IS: L(0) DRIVER
IS: SI INPUT
OPTION 16 VALUE e
IS:
IS:
IS:
IS:
IS:
IS:
IS:
IS:
IS:
IS:
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
OPTION
18
17
18
19
20
21
22
23
24
25
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
VALUE
e
e
e
e
e
e
e
e
e
SK DRIVER
G0 I/O PORT
G1 I/O PORT
G2 I/O PORT
G3 I/O PORT
D3 OUTPUT
D2 OUTPUT
D1 OUTPUT
D0 OUTPUT
L INPUT LEVELS
OPTION 26 VALUE e
IS: G INPUT LEVELS
OPTION 27 VALUE e
IS: SI INPUT LEVELS
OPTION 28 VALUE e
IS: COPS BONDING
Physical Dimensions inches (millimeters)
Hermetic Dual-In-Line Package (D)
Order Number COP311L-XXX/D or COP411L-XXX/D
NS Package Number D20A
Hermetic Package (D)
Order Number COP310L-XXX/D or COP410L-XXX/D
NS Package Number D24C
19
COP410L/COP411L/COP310L/COP311L
Single-Chip N-Channel Microcontrollers
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number COP411N or COP311N
NS Package Number N20A
Molded Dual-In-Line Package (N)
Order Number COP410N or COP310N
NS Package Number N24A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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2. A critical component is any component of a life
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be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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