Renesas HM62W8511HCLJP-12 4m high speed sram (512-kword x 8-bit) Datasheet

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HM62W8511HC Series
4M High Speed SRAM (512-kword × 8-bit)
ADE-203-1201C (Z)
Rev. 2.0
Nov. 9, 2001
Description
The HM62W8511HC is a 4-Mbit high speed static RAM organized 512-kword × 8-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. The HM62W8511HC is packaged
in 400-mil 36-pin SOJ for high density surface mounting.
Features
• Single supply : 3.3 V ± 0.3 V
• Access time : 10/12 ns (max)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
 All inputs and outputs
• Operating current : 115/100 mA (max)
• TTL standby current : 40 mA (max)
• CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
• Data retention current : 0.6 mA (max) (L-version)
• Data retention voltage : 2 V (min) (L-version)
• Center VCC and VSS type pin out
HM62W8511HC Series
Ordering Information
Type No.
Access time
Device marking
Package
HM62W8511HCJP-10
HM62W8511HCJP-12
10 ns
12 ns
HM62W8511CJP10
HM62W8511CJP12
400-mil 36-pin plastic SOJ (CP-36D)
HM62W8511HCLJP-10
HM62W8511HCLJP-12
10 ns
12 ns
HM62W8511CLJP10
HM62W8511CLJP12
Rev. 2, Nov. 2001, page 2 of 14
HM62W8511HC Series
Pin Arrangement
36-pin SOJ
A0
1
36
NC
A1
2
35
A18
A2
3
34
A17
A3
4
33
A16
A4
5
32
A15
6
31
I/O1
7
30
I/O8
I/O2
8
29
I/O7
VCC
9
28
VSS
VSS
10
27
VCC
I/O3
11
26
I/O6
I/O4
12
25
I/O5
13
24
A14
A5
14
23
A13
A6
15
22
A12
A7
16
21
A11
A8
17
20
A10
A9
18
19
NC
(Top View)
Pin Description
Pin name
Function
A0 to A18
Address input
I/O1 to I/O8
Data input/output
CS
Chip select
OE
Output enable
WE
Write enable
VCC
Power supply
VSS
Ground
NC
No connection
Rev. 2, Nov. 2001, page 3 of 14
HM62W8511HC Series
Block Diagram
(LSB)
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(MSB)
VCC
Row
decoder
1024-row × 32-column ×
16-block × 8-bit
(4,194,304 bits)
VSS
CS
Column I/O
I/O1
.
.
Input
data
control
Column decoder
.
I/O8
A8 A9 A18 A16 A17 A0 A2 A4 A15
(LSB)
(MSB)
CS
Rev. 2, Nov. 2001, page 4 of 14
CS
HM62W8511HC Series
Operation Table
CS
OE
WE
Mode
VCC current
I/O
Ref. cycle
H
×
×
Standby
ISB, ISB1
High-Z
—
L
H
H
Output disable
ICC
High-Z
—
L
L
H
Read
ICC
Dout
Read cycle (1) to (3)
L
H
L
Write
ICC
Din
Write cycle (1)
L
L
L
Write
ICC
Din
Write cycle (2)
Symbol
Value
Note:
H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Unit
Supply voltage relative to VSS
VCC
–0.5 to +4.6
Voltage on any pin relative to VSS
VT
–0.5* to VCC+0.5*
V
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–10 to +85
°C
V
1
2
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC+2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol
Supply voltage
Input voltage
Min
Typ
Max
Unit
3
3.0
3.3
3.6
V
4
VSS*
0
0
0
VIH
2.0
—
VCC + 0.5*
V
—
0.8
V
VCC*
VIL
Notes: 1.
2.
3.
4.
1
–0.5*
V
2
VIL (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns.
VIH (max) = VCC+2.0 V for pulse width (over shoot) ≤ 6 ns.
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
Rev. 2, Nov. 2001, page 5 of 14
HM62W8511HC Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)
1
Parameter
Symbol Min
Typ* Max
Unit
Test conditions
Input leakage current
IILII
—
—
2
µA
Vin = VSS to VCC
Output leakage current
IILOI
—
—
2
µA
Vin = VSS to VCC
Operation power supply current 10ns cycle ICC
—
—
115
mA
Min cycle
CS = VIL, lout = 0 mA
Other inputs = VIH/VIL
12 ns cycle ICC
—
—
100
mA
ISB
—
—
40
mA
Min cycle
CS = VIH,
Other inputs = VIH/VIL
ISB1
—
2.5
5
mA
f = 0 MHz
VCC ≥ CS ≥ VCC - 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC - 0.2 V
—*
0.5
1.0*
mA
VOL
—
—
0.4
V
IOL = 8 mA
VOH
2.4
—
—
V
IOH = –4 mA
Standby power supply current
2
Output voltage
2
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Input capacitance*
1
1
Input/output capacitance*
Note:
Symbol
Min
Typ
Max
Unit
Test conditions
Cin
—
—
6
pF
Vin = 0 V
CI/O
—
—
8
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
Rev. 2, Nov. 2001, page 6 of 14
HM62W8511HC Series
AC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
1.5 V
3.3 V
RL=50 Ω
Dout Zo=50 Ω
319Ω
Dout
353Ω
30 pF
Output load (A)
5 pF
Output load (B)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW)
Read Cycle
HM62W8511HC
-10
Min
-12
Parameter
Symbol
Max
Read cycle time
tRC
10
—
Address access time
tAA
—
10
Chip select access time
tACS
—
10
Output enable to output valid
tOE
—
Output hold from address change
tOH
Chip select to output in low-Z
Output enable to output in low-Z
Min
Max
Unit
Notes
12
—
ns
—
12
ns
—
12
ns
5
—
6
ns
3
—
3
—
ns
tCLZ
3
—
3
—
ns
1
tOLZ
0
—
0
—
ns
1
Chip deselect to output in high-Z
tCHZ
—
5
—
6
ns
1
Output disable to output in high-Z
tOHZ
—
5
—
6
ns
1
Rev. 2, Nov. 2001, page 7 of 14
HM62W8511HC Series
Write Cycle
HM62W8511HC
-10
Parameter
-12
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
10
—
12
—
ns
Address valid to end of write
tAW
7
—
8
—
ns
Chip select to end of write
tCW
7
—
8
—
ns
9
Write pulse width
tWP
7
—
8
—
ns
8
Address setup time
tAS
0
—
0
—
ns
6
Write recovery time
tWR
0
—
0
—
ns
7
Data to write time overlap
tDW
5
—
6
—
ns
Data hold from write time
tDH
0
—
0
—
ns
Write disable to output in low-Z
tOW
3
—
3
—
ns
1
Output disable to output in high-Z
tOHZ
—
5
—
6
ns
1
Write enable to output in high-Z
tWHZ
—
5
—
6
ns
1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS transition low.
3. WE and/or CS must be high during address transition time.
4. If CS and OE are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS or WE going low.
7. tWR is measured from the earlier of CS or WE going high to the first address transition.
8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low. A write ends at the earliest transition among CS going
high and WE going high. tWP is measured from the beginning of write to the end of write.
9. tCW is measured from the later of CS going low to the end of write.
Rev. 2, Nov. 2001, page 8 of 14
HM62W8511HC Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tOH
tAA
tACS
CS
tOE
tCHZ
tOHZ
OE
tOLZ
tCLZ
Dout
High impedance
Valid data
Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)
tRC
Address
Valid address
tAA
tOH
tOH
Dout
Valid data
Rev. 2, Nov. 2001, page 9 of 14
HM62W8511HC Series
Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)*
2
tRC
CS
tACS
tCHZ
tCLZ
Dout
High
impedance
Valid data
High
impedance
Write Timing Waveform (1) (WE Controlled)
tWC
Valid address
Address
tWR
tAW
tCW
*3
tAS
tWP
*3
tOHZ
High impedance*5
Dout
tDW
Din
Rev. 2, Nov. 2001, page 10 of 14
*4
tDH
Valid data
*4
HM62W8511HC Series
Write Timing Waveform (2) (CS Controlled)
tWC
Valid address
Address
tWR
tCW
*3
tAW
tWP
*3
tAS
tWHZ
tOW
High impedance*5
Dout
tDW
Din
*4
tDH
Valid data
*4
Rev. 2, Nov. 2001, page 11 of 14
HM62W8511HC Series
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*
VCC for data retention
VDR
2.0
Data retention current
ICCDR
Chip deselect to data
retention time
Operation recovery time
Note:
1
Max
Unit
Test conditions
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
—
300
600
µA
VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
tCDR
0
—
—
ns
See retention waveform
tR
5
—
—
ms
1. Typical values are at VCC = 3.0 V, Ta = +25°C, and not guaranteed.
Low VCC Data Retention Timing Waveform
t CDR
Data retention mode
V CC
3.0 V
V DR
2.0 V
0V
Rev. 2, Nov. 2001, page 12 of 14
VCC ≥
≥ VCC – 0.2 V
tR
HM62W8511HC Series
Package Dimensions
HM62W8511HCJP/HCLJP Series (CP-36D)
As of January, 2001
Unit: mm
23.25
23.62 Max
10.16 ± 0.13
*0.43 ± 0.10
0.41 ± 0.08
1.27
0.80 +0.25
–0.17
1.30 Max
2.85 ± 0.12
18
0.74
3.50 ± 0.26
1
11.18 ± 0.13
19
36
9.40 ± 0.25
0.10
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
EIAJ
Mass (reference value)
CP-36D
Conforms
Conforms
1.4 g
Rev. 2, Nov. 2001, page 13 of 14
HM62W8511HC Series
Disclaimer
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions
and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
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5. This product is not designed to be radiation resistant.
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
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Rev. 2, Nov. 2001, page 14 of 14