LTC2159 16-Bit, 20Msps Low Power ADC Features n n n n n n n n n n n n Description 77dB SNR 90dB SFDR Low Power: 43mW Single 1.8V Supply CMOS, DDR CMOS, or DDR LVDS Outputs Selectable Input Ranges: 1VP-P to 2VP-P 550MHz Full Power Bandwidth S/H Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown and Nap Modes Serial SPI Port for Configuration 48-Lead (7mm × 7mm) QFN Package The LTC®2159 is a sampling 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals. It is perfect for demanding communications applications with AC performance that includes 77dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) and no missing codes over temperature. The transition noise is 3.2LSBRMS. The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. Applications n n n n n n Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multichannel Data Acquisition Nondestructive Testing The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application 1.8V VDD Integral Non-Linearity (INL) 1.8V OVDD 4.0 3.0 S/H 2.0 16-BIT ADC CORE OUTPUT DRIVERS 20MHz CMOS DDR CMOS OR DDR LVDS OUTPUTS 1.0 0 –1.0 –2.0 CLOCK CONTROL CLOCK D15 • • • D0 INL ERROR (LSB) ANALOG INPUT –3.0 –4.0 2159 TA01a GND OGND 0 16384 32768 49152 OUTPUT CODE 65536 2159 TA01b 2159f 1 LTC2159 Absolute Maximum Ratings (Notes 1, 2) Supply Voltages (VDD, OVDD)........................ –0.3V to 2V Analog Input Voltage (AIN+, AIN –, PAR/SER, SENSE) (Note 3).................................... –0.3V to (VDD + 0.2V) Digital Input Voltage (ENC+, ENC–, CS, SDI, SCK) (Note 4)................................................. –0.3V to 3.9V SDO (Note 4).............................................. –0.3V to 3.9V Digital Output Voltage.................–0.3V to (OVDD + 0.3V) Operating Temperature Range LTC2159C................................................. 0°C to 70°C LTC2159I..............................................–40°C to 85°C Storage Temperature Range................... –65°C to 150°C Pin Configuration FULL RATE CMOS OUTPUT MODE DOUBLE DATA RATE CMOS OUTPUT MODE TOP VIEW 48 VDD 47 VDD 46 SENSE 45 VREF 44 SDO 43 GND 42 OF 41 DNC 40 D15 39 D14 38 D13 37 D12 48 VDD 47 VDD 46 SENSE 45 VREF 44 SDO 43 GND 42 OF 41 DNC 40 D14_15 39 DNC 38 D12_13 37 DNC TOP VIEW VCM 1 AIN + 2 AIN – 3 GND 4 REFH 5 REFL 6 REFH 7 REFL 8 PAR/SER 9 GND 10 GND 11 VDD 12 49 GND VDD 13 GND 14 ENC + 15 ENC – 16 CS 17 SCK 18 SDI 19 GND 20 DNC 21 D0_1 22 DNC 23 D2_3 24 49 GND 36 D11 35 D10 34 D9 33 D8 32 OVDD 31 OGND 30 CLKOUT + 29 CLKOUT – 28 D7 27 D6 26 D5 25 D4 VDD 13 GND 14 ENC + 15 ENC – 16 CS 17 SCK 18 SDI 19 GND 20 D0 21 D1 22 D2 23 D3 24 VCM 1 AIN + 2 AIN – 3 GND 4 REFH 5 REFL 6 REFH 7 REFL 8 PAR/SER 9 GND 10 GND 11 VDD 12 UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN TJMAX = 150°C, θJA = 29°C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB 36 D10_11 35 DNC 34 D8_9 33 DNC 32 OVDD 31 OGND 30 CLKOUT + 29 CLKOUT – 28 D6_7 27 DNC 26 D4_5 25 DNC TJMAX = 150°C, θJA = 29°C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB 2159f 2 LTC2159 pin configuration DOUBLE DATA RATE LVDS OUTPUT MODE 48 VDD 47 VDD 46 SENSE 45 VREF 44 SDO 43 GND 42 OF + 41 OF – 40 D14_15 + 39 D14_15 – 38 D12_13 + 37 D12_13 – TOP VIEW VCM 1 AIN + 2 AIN – 3 GND 4 REFH 5 REFL 6 REFH 7 REFL 8 PAR/SER 9 GND 10 GND 11 VDD 12 36 D10_11 + 35 D10_11 – 34 D8_9 + 33 D8_9 – 32 OVDD 31 OGND 30 CLKOUT + 29 CLKOUT – 28 D6_7 + 27 D6_7– 26 D4_5 + 25 D4_5– VDD 13 GND 14 ENC + 15 ENC – 16 CS 17 SCK 18 SDI 19 GND 20 D0_1 – 21 D0_1 + 22 D2_3 – 23 D2_3 + 24 49 GND UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN TJMAX = 150°C, θJA = 29°C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2159CUK#PBF LTC2159CUK#TRPBF LTC2159UK 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C LTC2159IUK#PBF LTC2159IUK#TRPBF LTC2159UK 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2159f 3 LTC2159 Converter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PARAMETER CONDITIONS Resolution (No Missing Codes) MIN l TYP MAX UNITS 16 Bits Integral Linearity Error Differential Analog Input (Note 6) l –6 ±2 6 LSB Differential Linearity Error Differential Analog Input l –0.9 ±0.5 0.9 LSB Offset Error (Note 7) l –7 ±1.5 7 mV Gain Error Internal Reference External Reference –1.8 ±1.5 –0.5 0.8 %FS %FS l Offset Drift ±10 µV/°C Full-Scale Drift Internal Reference External Reference ±30 ±10 ppm/°C ppm/°C Transition Noise External Reference 3.2 LSBRMS Analog Input The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (AIN+ – AIN– ) MIN TYP MAX UNITS 1.7V < VDD < 1.9V l VIN(CM) Analog Input Common Mode (AIN+ + AIN– )/2 Differential Analog Input (Note 8) l 0.7 VCM 1.25 V VSENSE External Voltage Reference Applied to SENSE External Reference Mode l 0.625 1.250 1.300 V IINCM Analog Input Common Mode Current Per Pin, 20Msps IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN– < VDD l –1 1 µA IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l –3 3 µA IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l –3 3 µA tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Jitter CMRR Analog Input Common Mode Rejection Ratio BW-3B Full Power Bandwidth 1 to 2 VP-P 32 µA 0 Single-Ended Encode Differential Encode ns 0.07 0.09 Figure 6 Test Circuit psRMS 80 dB 550 MHz Dynamic Accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS SNR Signal-to-Noise Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input SFDR SFDR Spurious Free Dynamic Range 2nd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input Spurious Free Dynamic Range 3rd Harmonic 5MHz Input 30MHz Input 70MHz Input 140MHz Input MIN l 75.5 l 84 l 84 TYP MAX UNITS 77.1 77.0 76.9 76.4 dBFS dBFS dBFS dBFS 90 90 89 84 dBFS dBFS dBFS dBFS 90 90 89 84 dBFS dBFS dBFS dBFS 2159f 4 LTC2159 dynamic accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5) SYMBOL PARAMETER CONDITIONS SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input 70MHz Input 140MHz Input Signal-to-Noise Plus Distortion Ratio 5MHz Input 30MHz Input 70MHz Input 140MHz Input S/(N+D) MIN l 89 l 74.9 TYP MAX UNITS 95 95 95 95 dBFS dBFS dBFS dBFS 76.9 76.8 76.5 76.4 dBFS dBFS dBFS dBFS Internal Reference Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) PARAMETER CONDITIONS VCM Output Voltage IOUT = 0 MIN TYP MAX 0.5•VDD – 25mV 0.5•VDD 0.5•VDD + 25mV VCM Output Temperature Drift ±25 VCM Output Resistance –600µA < IOUT < 1mA VREF Output Voltage IOUT = 0 Ω 1.250 VREF Output Temperature Drift 1.275 ±25 –400µA < IOUT < 1mA VREF Line Regulation 1.7V < VDD < 1.9V V ppm/°C 4 1.225 VREF Output Resistance UNITS V ppm/°C 7 Ω 0.6 mV/V Digital Inputs and Outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC–) DIFFERENTIAL ENCODE MODE (ENC– NOT TIED TO GND) VID Differential Input Voltage (Note 8) l 0.2 VICM Common Mode Input Voltage Internally Set Externally Set (Note 8) l 1.1 l 0.2 V 1.2 1.6 V V 3.6 V VIN Input Voltage Range ENC+, ENC– to GND RIN Input Resistance (See Figure 10) 10 kΩ CIN Input Capacitance (Note 8) 3.5 pF SINGLE-ENDED ENCODE MODE (ENC– TIED TO GND) VIH High Level Input Voltage VDD = 1.8V l 1.2 V VIL Low Level Input Voltage VDD = 1.8V l VIN Input Voltage Range ENC+ to GND l RIN Input Resistance (See Figure 11) 30 kΩ CIN Input Capacitance (Note 8) 3.5 pF 0.6 0 3.6 V V DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode) VIH High Level Input Voltage VDD = 1.8V l VIL Low Level Input Voltage VDD = 1.8V l IIN Input Current VIN = 0V to 3.6V l CIN Input Capacitance (Note 8) 1.3 V –10 3 0.6 V 10 µA pF 2159f 5 LTC2159 digital inputs and outputs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used) ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V IOH Logic High Output Leakage Current SDO = 0V to 3.6V COUT Output Capacitance (Note 8) 200 l –10 Ω 10 µA 3 pF 1.790 V DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) OVDD = 1.8V VOH High Level Output Voltage IO = –500µA l VOL Low Level Output Voltage IO = 500µA l 1.750 0.010 0.050 V OVDD = 1.5V VOH High Level Output Voltage IO = –500µA 1.488 V VOL Low Level Output Voltage IO = 500µA 0.010 V OVDD = 1.2V VOH High Level Output Voltage IO = –500µA 1.185 V VOL Low Level Output Voltage IO = 500µA 0.010 V DIGITAL DATA OUTPUTS (LVDS MODE) VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l 247 350 175 454 VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l 1.125 1.250 1.250 1.375 RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V mV mV V V 100 Ω Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX 1.9 UNITS CMOS Output Modes: Full Data Rate and Double Data Rate VDD Analog Supply Voltage (Note 10) l 1.7 1.8 OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input Sine Wave Input l 24 24.4 28.5 mA mA IOVDD Digital Supply Current Sine Wave Input, OVDD =1.2V PDISS Power Dissipation DC Input Sine Wave Input, OVDD =1.2V l 0.8 V mA 43 45 51.5 mW mW 1.8 1.9 V 1.8 LVDS Output Mode VDD Analog Supply Voltage (Note 10) l 1.7 OVDD Output Supply Voltage (Note 10) l 1.7 IVDD Analog Supply Current Sine Wave Input, 1.75mA Mode Sine Wave Input, 3.5mA Mode IOVDD Digital Supply Current (OVDD = 1.8V) Sine Wave Input, 1.75mA Mode Sine Wave Input, 3.5mA Mode Power Dissipation Sine Wave Input, 1.75mA Mode Sine Wave Input, 3.5mA Mode PDISS 1.9 V l 25.8 26.7 31 mA mA l 21.1 40.9 46 mA mA l 84 122 139 mW mW 2159f 6 LTC2159 power requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS All Output Modes PSLEEP Sleep Mode Power 1 mW PNAP Nap Mode Power 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled (No Increase for Nap or Sleep Modes) 20 mW Timing Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS fS Sampling Frequency (Note 10) l MIN 1 tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 20 2 tH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 20 2 tAP Sample-and-Hold Acquisition Delay Time TYP MAX UNITS 20 MHz 25 25 500 500 ns ns 25 25 500 500 ns ns 0 ns DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 Pipeline Latency Full Data Rate Mode Double Data Rate Mode 6 6.5 ns Cycles Cycles DIGITAL DATA OUTPUTS (LVDS MODE) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.8 3.2 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.5 2.7 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 Pipeline Latency 6.5 ns Cycles SPI PORT TIMING (Note 8) tSCK SCK Period tS Write Mode Readback Mode, CSDO = 20pF, RPULLUP = 2k l l 40 250 ns ns CS to SCK Setup Time l 5 ns tH SCK to CS Setup Time l 5 ns tDS SDI Setup Time l 5 ns tDH SDI Hold Time l 5 ns tDO SCK Falling to SDO Valid Readback Mode, CSDO = 20pF, RPULLUP = 2k l 125 ns 2159f 7 LTC2159 Electrical Characteristics Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: When these pin voltages are taken below GND they will be clamped by internal diodes. When these pin voltages are taken above VDD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup. Note 5: VDD = OVDD = 1.8V, fSAMPLE = 20MHz, LVDS outputs, differential ENC+/ENC– = 2VP-P sine wave, input range = 2VP-P with differential drive, unless otherwise noted. Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band. Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 8: Guaranteed by design, not subject to test. Note 9: VDD = 1.8V, fSAMPLE = 20MHz, CMOS outputs, ENC+ = singleended 1.8V square wave, ENC– = 0V, input range = 2VP-P with differential drive, 5pF load on each digital output unless otherwise noted. Note 10: Recommended operating conditions. Timing Diagrams Full-Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH tL N+1 ENC– ENC+ tD N–6 D0–D15, OF CLKOUT + CLKOUT – N–5 N–4 N–3 N–2 tC 2159 TD01 2159f 8 LTC2159 timing diagrams Double Data Rate CMOS Output Mode Timing All Outputs are Single-Ended and Have CMOS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH tL N+1 ENC– ENC+ tD D0_1 tD D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 •• • D14_15 OFN-6 OF OFN-5 OFN-3 tC tC CLKOUT+ OFN-4 CLKOUT – 2159 TD02 Double Data Rate LVDS Output Mode Timing All Outputs are Differential and Have LVDS Levels tAP ANALOG INPUT N+4 N+2 N N+3 tH tL N+1 ENC– ENC+ D0_1+ D0_1– tD tD D0N-6 D1N-6 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D14N-6 D15N-6 D14N-5 D15N-5 D14N-4 D15N-4 D14N-3 D15N-3 •• • D14_15+ D14_15– OF+ OF– CLKOUT+ CLKOUT – OFN-6 tC OFN-5 OFN-4 OFN-3 tC 2159 TD03 2159f 9 LTC2159 timing diagrams SPI Port Timing (Readback Mode) tDS tS tDH tSCK tH CS SCK tDO SDI A6 R/W SDO A5 A4 A3 A2 A1 A0 XX D7 HIGH IMPEDANCE XX XX D6 D5 XX XX D4 D3 XX D2 XX XX D1 D0 SPI Port Timing (Write Mode) CS SCK SDI A6 R/W SDO A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 2159 TD04 HIGH IMPEDANCE Typical Performance Characteristics Integral Non-Linearity (INL) DNL ERROR (LSB) 2.0 1.0 0 –1.0 –2.0 1.0 10000 0.8 9000 0.6 8000 0.4 7000 0.2 6000 COUNT 3.0 INL ERROR (LSB) Shorted Input Histogram Differential Non-Linearity (DNL) 4.0 0 5000 –0.2 4000 –0.4 3000 –0.6 2000 –3.0 –0.8 1000 –4.0 –1.0 0 16384 32768 49152 OUTPUT CODE 65536 2159 G01 0 16384 32768 49152 OUTPUT CODE 65536 2159 G02 0 32836 32842 32848 32854 OUTPUT CODE 32860 2159 G03 2159f 10 LTC2159 Typical Performance Characteristics 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 20Msps, 2V Range SNR vs Input Frequency, –1dBFS, 20Msps, 2V Range 77 DIFFERENTIAL ENCODE 73 72 71 100 150 200 250 INPUT FREQUENCY (MHz) 95 90 80 2ND 75 70 65 300 3RD 85 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 2159 G04 130 300 3RD 90 85 2ND 80 75 70 65 0 50 100 150 200 250 INPUT FREQUENCY (MHz) 2159 G05 300 2159 G06 IVDD vs Sample Rate, 5MHz, –1dBFS Wine Wave Input SFDR vs Input Level, fIN = 70MHz, 20Msps, 2V Range 29 120 110 dBFS 100 3.5mA LVDS OUTPUTS 25 90 80 IVDD (mA) 50 95 dBc 70 60 CMOS OUTPUTS 21 50 40 30 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 17 0 0 4 8 12 16 SAMPLE RATE (Msps) IOVDD vs Sample Rate, 5MHz, –1dBFS Sine Wave Input 50 78 SNR vs SENSE, fIN = 5MHz, –1dBFS 77 3.5mA LVDS 40 76 30 1.75mA LVDS 20 75 74 73 72 10 1.2V CMOS 0 20 2159 G08 2159 G07 SNR (dBFS) 0 SFDR (dBc AND dBFS) 70 IOVDD (mA) SNR (dBFS) 75 74 100 2ND AND 3RD HARMONIC (dBFS) SINGLE-ENDED ENCODE 76 100 2ND AND 3RD HARMONIC (dBFS) 78 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 20Msps, 1V Range 0 4 71 1.8V CMOS 8 12 16 SAMPLE RATE (Msps) 20 2159 G09 70 0.6 0.7 0.8 0.9 1 1.1 SENSE PIN (V) 1.2 1.3 2159 G10 2159f 11 LTC2159 Pin Functions (Pins that are the Same for All Digital Output Modes) VCM (Pin 1): Common Mode Bias Output. Nominally equal to VDD /2. VCM should be used to bias the common mode of the analog inputs. Bypass to ground with a 0.1µF ceramic capacitor. AIN+ (Pin 2): Positive Differential Analog Input. AIN– (Pin 3): Negative Differential Analog Input. GND (Pins 4, 10, 11, 14, 20, 43, Exposed Pad Pin 49): ADC Power Ground. The exposed pad must be soldered to the PCB ground. REFH (Pins 5, 7): ADC High Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. REFL (Pins 6, 8): ADC Low Reference. See the Applications Information section for recommended bypassing circuits for REFH and REFL. PAR/SER (Pin 9): Programming Mode Selection Pin. Connect to ground to enable the serial programming mode. CS, SCK, SDI, SDO become a serial interface that control the A/D operating modes. Connect to VDD to enable the parallel programming mode where CS, SCK, SDI, SDO become parallel logic inputs that control a reduced set of the A/D operating modes. PAR/SER should be connected directly to ground or VDD and not be driven by a logic signal. VDD (Pins 12, 13, 47, 48): Analog Power Supply, 1.7V to 1.9V. Bypass to ground with 0.1µF ceramic capacitors. Adjacent pins can share a bypass capacitor. ENC+ (Pin 15): Encode Input. Conversion starts on the rising edge. ENC– (Pin 16): Encode Complement Input. Conversion starts on the falling edge. Tie to GND for single-ended encode mode. CS (Pin 17): Serial Interface Chip Select Input. In serial programming mode (PAR/SER = 0V), CS is the serial interface chip select input. When CS is low, SCK is enabled for shifting data on SDI into the mode control registers. In the parallel programming mode (PAR/SER = VDD), CS controls the clock duty cycle stabilizer (see Table 2). CS can be driven with 1.8V to 3.3V logic. SCK (Pin 18): Serial Interface Clock Input. In serial programming mode, (PAR/SER = 0V), SCK is the serial interface clock input. In the parallel programming mode (PAR/SER = VDD), SCK controls the digital output mode (see Table 2). SCK can be driven with 1.8V to 3.3V logic. SDI (Pin 19): Serial Interface Data Input. In serial programming mode, (PAR/SER = 0V), SDI is the serial interface data input. Data on SDI is clocked into the mode control registers on the rising edge of SCK. In the parallel programming mode (PAR/SER = VDD), SDI can be used together with SDO to power down the part (Table 2). SDI can be driven with 1.8V to 3.3V logic. OGND (Pin 31): Output Driver Ground. Must be shorted to the ground plane by a very low inductance path. Use multiple vias close to the pin. OVDD (Pin 32): Output Driver Supply. Bypass to ground with a 0.1µF ceramic capacitor. SDO (Pin 44): Serial Interface Data Output. In serial programming mode, (PAR/SER = 0V), SDO is the optional serial interface data output. Data on SDO is read back from the mode control registers and can be latched on the falling edge of SCK. SDO is an open-drain NMOS output that requires an external 2k pull-up resistor to 1.8V – 3.3V. If read back from the mode control registers is not needed, the pull-up resistor is not necessary and SDO can be left unconnected. In the parallel programming mode (PAR/SER = VDD), SDO can be used together with SDI to power down the part (Table 2). When used as an input, SDO can be driven with 1.8V to 3.3V logic through a 1k series resistor. VREF (Pin 45): Reference Voltage Output. Bypass to ground with a 2.2µF ceramic capacitor. The output voltage is nominally 1.25V. SENSE (Pin 46): Reference Programming Pin. Connecting SENSE to VDD selects the internal reference and a ±1V input range. Connecting SENSE to ground selects the internal reference and a ±0.5V input range. An external reference between 0.625V and 1.3V applied to SENSE selects an input range of ±0.8 • VSENSE. 2159f 12 LTC2159 pin functions FULL RATE CMOS OUTPUT MODE DOUBLE DATA RATE LVDS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) All Pins Below Have LVDS Output Levels. The Output Current Level is Programmable. There is an Optional Internal 100Ω Termination Resistor Between the Pins of Each LVDS Output Pair. D0 to D15 (Pins 21-28, 33-40): Digital Outputs. D15 is the MSB. CLKOUT– (Pin 29): Inverted version of CLKOUT+. CLKOUT+ (Pin 30): Data Output Clock. The digital outputs normally transition at the same time as the falling edge of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. DNC (Pin 41): Do not connect this pin. OF (Pin 42): Overflow/Underflow Digital Output. OF is high when an overflow or underflow has occurred. DOUBLE DATA RATE CMOS OUTPUT MODE All Pins Below Have CMOS Output Levels (OGND to OVDD) D0_1–/D0_1+ to D14_15–/D14_15+ (Pins 21/22, 23/24, 25/26, 27/28, 33/34, 35/36, 37/38, 39/40): Double Data Rate Digital Outputs. Two data bits are multiplexed onto each differential output pair. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. CLKOUT–/CLKOUT+ (Pins 39/40): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. OF–/OF+ (Pins 41/42): Overflow/Underflow Digital Output. OF+ is high when an overflow or underflow has occurred. D0_1 to D14_15 (Pins 22, 24, 26, 28, 34, 36, 38, 40): Double Data Rate Digital Outputs. Two data bits are multiplexed onto each output pin. The even data bits (D0, D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT+ is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15) appear when CLKOUT+ is high. DNC (Pins 21, 23, 25, 27, 33, 35, 37, 39, 41): Do not connect these pins. CLKOUT– (Pin 29): Inverted version of CLKOUT+. CLKOUT+ (Pin 30): Data Output Clock. The digital outputs normally transition at the same time as the falling and rising edges of CLKOUT+. The phase of CLKOUT+ can also be delayed relative to the digital outputs by programming the mode control registers. OF (Pin 42): Overflow/Underflow Digital Output. OF is high when an overflow or underflow has occurred. 2159f 13 LTC2159 Functional Block Diagram VDD OVDD ANALOG INPUT 16-BIT ADC CORE S/H OF CORRECTION LOGIC • • • OUTPUT DRIVERS VREF 2.2µF 1.25V REFERENCE D15 D0 CLKOUT + CLKOUT – RANGE SELECT SENSE VCM REFH REF BUF REFL DIFF REF AMP VDD/2 OGND INTERNAL CLOCK SIGNALS CLOCK/DUTY CYCLE CONTROL MODE CONTROL REGISTERS 0.1µF REFH GND 0.1µF 2.2µF 2159 BD REFL + ENC ENC– PAR/SER CS SCK SDI SDO 0.1µF Figure 1. Functional Block Diagram Applications Information CONVERTER OPERATION ANALOG INPUT The LTC2159 is a low power, 16-bit, 20Msps A/D converter that is powered by a single 1.8V supply. The analog inputs should be driven differentially. The encode input can be driven differentially or single-ended for lower power consumption. The digital outputs can be CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system). Many additional features can be chosen by programming the mode control registers through a serial SPI port. The analog inputs are differential CMOS sample-and-hold circuits (Figure 2). The inputs should be driven differentially around a common mode voltage set by the VCM output pin, which is nominally VDD/2. For the 2V input range, the inputs should swing from VCM – 0.5V to VCM + 0.5V. There should be 180° phase difference between the inputs. 2159f 14 LTC2159 Applications Information Transformer Coupled Circuits LTC2159 VDD AIN+ RON 15Ω 10Ω CPARASITIC 1.8pF VDD AIN– CSAMPLE 5pF RON 15Ω 10Ω CSAMPLE 5pF CPARASITIC 1.8pF Figure 3 shows the analog input being driven by an RF transformer with a center-tapped secondary. The center tap is biased with VCM, setting the A/D input at its optimal DC level. At higher input frequencies a transmission line balun transformer (Figures 4 through 6) has better balance, resulting in lower A/D distortion. Amplifier Circuits VDD Figure 7 shows the analog input being driven by a high speed differential amplifier. The output of the amplifier is AC coupled to the A/D so the amplifier’s output common mode voltage can be optimally set to minimize distortion. 1.2V 10k ENC+ ENC– 10k 1.2V 2159 F02 At very high frequencies an RF gain block will often have lower distortion than a differential amplifier. If the gain block is single-ended, then a transformer circuit (Figures 4 through 6) should convert the signal to differential before driving the A/D. Figure 2. Equivalent Input Circuit 50Ω 0.1µF Single-Ended Input For applications less sensitive to harmonic distortion, the AIN+ input can be driven single-ended with a 1VP-P signal centered around VCM. The AIN– input should be connected to VCM and the VCM bypass capacitor should be increased to 2.2µF. With a single-ended input the harmonic distortion and INL will degrade, but the noise and DNL will remain unchanged. INPUT DRIVE CIRCUITS VCM 0.1µF ANALOG INPUT T1 1:1 AIN+ 25Ω 25Ω LTC2159 0.1µF 12pF 25Ω 25Ω T1: MA/COM MABAES0060 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 2159 F03 Figure 3. Analog Input Circuit Using a Transformer. Recommended for Input Frequencies from 5MHz to 70MHz Input filtering If possible, there should be an RC lowpass filter right at the analog inputs. This lowpass filter isolates the drive circuitry from the A/D sample-and-hold switching, and also limits wideband noise from the drive circuitry. Figure 3 shows an example of an input RC filter. The RC component values should be chosen based on the application’s input frequency. 2159f 15 LTC2159 applications information 50Ω VCM 0.1µF 0.1µF ANALOG INPUT T1 AIN+ 12Ω T2 25Ω LTC2159 0.1µF 8.2pF 0.1µF 25Ω AIN– 12Ω 2159 F04 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 4. Recommended Front End Circuit for Input Frequencies from 5MHz to 150MHz 50Ω VCM 0.1µF 0.1µF ANALOG INPUT AIN+ T2 T1 25Ω LTC2159 0.1µF 1.8pF 0.1µF 25Ω AIN– 2159 F05 T1: MA/COM MABA-007159-000000 T2: COILCRAFT WBC1-1TL RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE Figure 5. Recommended Front End Circuit for Input Frequencies from 150MHz to 250MHz 50Ω VCM VCM HIGH SPEED DIFFERENTIAL 0.1µF AMPLIFIER 0.1µF 0.1µF ANALOG INPUT 4.7nH T1 0.1µF LTC2159 0.1µF 25Ω 25Ω AIN+ 4.7nH Figure 6. Recommended Front End Circuit for Input Frequencies Above 250MHz 2159 F06 200Ω 25Ω + – AIN– T1: MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE ANALOG INPUT 200Ω 0.1µF AIN+ 12pF 0.1µF 25Ω LTC2159 AIN– 12pF 2159 F07 Figure 7. Front End Circuit Using a High Speed Differential Amplifier 2159f 16 LTC2159 Applications Information Reference The LTC2159 has an internal 1.25V voltage reference. For a 2V input range using the internal reference, connect SENSE to VDD. For a 1V input range using the internal reference, connect SENSE to ground. For a 2V input range with an external reference, apply a 1.25V reference voltage to SENSE (Figure 9). The input range can be adjusted by applying a voltage to SENSE that is between 0.625V and 1.30V. The input range will then be 1.6 • VSENSE. The VREF, REFH and REFL pins should be bypassed as shown in Figure 8a. A low inductance 2.2µF interdigitated capacitor is recommended for the bypass between REFH and REFL. This type of capacitor is available at a low cost from multiple suppliers. Alternatively, C1 can be replaced by a standard 2.2µF capacitor between REFH and REFL. The capacitor should be as close to the pins as possible (not on the back side of the circuit board). REFH C3 0.1µF LTC2159 REFL C1 2.2µF REFH C2 0.1µF REFL 2159 F08b CAPACITORS ARE 0402 PACKAGE SIZE Figure 8b. Alternative REFH/REFL Bypass Circuit Figures 8c and 8d show the recommended circuit board layout for the REFH/REFL bypass capacitors. Note that in Figure 8c, every pin of the interdigitated capacitor (C1) is connected since the pins are not internally connected in some vendors’ capacitors. In Figure 8d, the REFH and REFL pins are connected by short jumpers in an internal layer. To minimize the inductance of these jumpers they can be placed in a small hole in the GND plane on the second board layer. LTC2159 VREF 1.25V 5Ω 2.2µF 1.25V BANDGAP REFERENCE 0.625V TIE TO VDD FOR 2V RANGE; TIE TO GND FOR 1V RANGE; RANGE = 1.6 • VSENSE FOR 0.625V < VSENSE < 1.300V Figure 8c. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8a RANGE DETECT AND CONTROL SENSE BUFFER INTERNAL ADC HIGH REFERENCE C2 0.1µF – + REFH + – REFL – + REFH + – REFL C1 C3 0.1µF Figure 8d. Recommended Layout for the REFH/REFL Bypass Circuit in Figure 8b 0.8x DIFF AMP VREF INTERNAL ADC LOW REFERENCE C1: 2.2µF LOW INDUCTANCE INTERDIGITATED CAPACITOR TDK CLLE1AX7S0G225M MURATA LLA219C70G225M AVX W2L14Z225M OR EQUIVALENT Figure 8a. Reference Circuit 2.2µF 2159 F08 1.25V EXTERNAL REFERENCE LTC2159 SENSE 1µF 2159 F09 Figure 9. Using an External 1.25V Reference 2159f 17 LTC2159 applications information Encode Input The signal quality of the encode inputs strongly affects the A/D noise performance. The encode inputs should be treated as analog signals—do not route them next to digital traces on the circuit board. There are two modes of operation for the encode inputs: the differential encode mode (Figure 10), and the single-ended encode mode (Figure 11). LTC2159 ENC+ T1 50Ω LTC2159 100Ω 50Ω 0.1µF 0.1µF ENC– 2159 F12 T1 = MA/COM ETC1-1-13 RESISTORS AND CAPACITORS ARE 0402 PACKAGE SIZE VDD DIFFERENTIAL COMPARATOR VDD 0.1µF Figure 12. Sinusoidal Encode Drive 0.1µF ENC+ 15k ENC+ PECL OR LVDS CLOCK ENC– LTC2159 0.1µF 30k ENC– 2159 F13 2159 F10 Figure 10. Equivalent Encode Input Circuit for Differential Encode Mode LTC2159 1.8V TO 3.3V 0V ENC+ ENC– 30k CMOS LOGIC BUFFER 2159 F11 Figure 11. Equivalent Encode Input Circuit for Single-Ended Encode Mode. The differential encode mode is recommended for sinusoidal, PECL, or LVDS encode inputs (Figures 12, 13). The encode inputs are internally biased to 1.2V through 10kΩ equivalent resistance. The encode inputs can be taken above VDD (up to 3.6V), and the common mode range is from 1.1V to 1.6V. In the differential encode mode, ENC– should stay at least 200mV above ground to avoid falsely triggering the single-ended encode mode. For good jitter performance ENC+ and ENC– should have fast rise and fall times. The single ended encode mode should be used with CMOS encode inputs. To select this mode, ENC– is connected to ground and ENC+ is driven with a square wave Figure 13. PECL or LVDS Encode Drive encode input. ENC+ can be taken above VDD (up to 3.6V) enabling 1.8V to 3.3V CMOS logic levels to be used. The ENC+ threshold is 0.9V. For good jitter performance ENC+ should have fast rise and fall times. If the encode signal is turned off or drops below approximately 500kHz, the A/D enters nap mode. Clock Duty Cycle Stabilizer For good performance the encode signal should have a 50% (±10%) duty cycle. If the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 10% to 90% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the encode signal changes frequency, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. The duty cycle stabilizer is enabled by mode control register A2 (serial programming mode), or by CS (parallel programming mode). For applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. If the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (±10%) duty cycle. The duty cycle stabilizer should not be used below 5Msps. 2159f 18 LTC2159 Applications Information DIGITAL OUTPUTS Double Data Rate LVDS Mode Digital Output Modes In double data rate LVDS mode, two data bits are multiplexed and output on each differential output pair. There are eight LVDS output pairs (D0_1+/D0_1– through D14_15+/ D14_15–) for the digital output data. Overflow (OF+/OF–) and the data output clock (CLKOUT+/CLKOUT–) each have an LVDS output pair. The LTC2159 can operate in three digital output modes: full rate CMOS, double data rate CMOS (to halve the number of output lines), or double data rate LVDS (to reduce digital noise in the system.) The output mode is set by mode control register A3 (serial programming mode), or by SCK (parallel programming mode). Note that double data rate CMOS cannot be selected in the parallel programming mode. Full Rate CMOS Mode In full rate CMOS mode the data outputs (D0 to D15), overflow (OF), and the data output clocks (CLKOUT+, CLKOUT–) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. For good performance, the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF, a digital buffer should be used. Double Data Rate CMOS Mode In double data rate CMOS mode, two data bits are multiplexed and output on each data pin. This reduces the number of digital lines by eight, simplifying board routing and reducing the number of input pins needed to receive the data. The data outputs (D0_1, D2_3, D4_5, D6_7, D8_9, D10_11, D12_13, D14_15), overflow (OF), and the data output clocks (CLKOUT+, CLKOUT–) have CMOS output levels. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. OVDD can range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. For good performance, the digital outputs should drive minimal capacitive loads. If the load capacitance is larger than 10pF, a digital buffer should be used. By default the outputs are standard LVDS levels: 3.5mA output current and a 1.25V output common mode voltage. An external 100Ω differential termination resistor is required for each LVDS output pair. The termination resistors should be located as close as possible to the LVDS receiver. The outputs are powered by OVDD and OGND which are isolated from the A/D core power and ground. In LVDS mode, OVDD must be 1.8V. Programmable LVDS Output Current In LVDS mode, the default output driver current is 3.5mA. This current can be adjusted by serially programming mode control register A3. Available current levels are 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. Optional LVDS Driver Internal Termination In most cases using just an external 100Ω termination resistor will give excellent LVDS signal integrity. In addition, an optional internal 100Ω termination resistor can be enabled by serially programming mode control register A3. The internal termination helps absorb any reflections caused by imperfect termination at the receiver. When the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. Overflow Bit The overflow output bit outputs a logic high when the analog input is either overranged or underranged. The overflow bit has the same pipeline latency as the data bits. 2159f 19 LTC2159 applications information Phase-Shifting the Output Clock In full rate CMOS mode the data output bits normally change at the same time as the falling edge of CLKOUT +, so the rising edge of CLKOUT+ can be used to latch the output data. In double data rate CMOS and LVDS modes the data output bits normally change at the same time as the falling and rising edges of CLKOUT+. To allow adequate setup and hold time when latching the data, the CLKOUT+ signal may need to be phase-shifted relative to the data output bits. Most FPGAs have this feature; this is generally the best place to adjust the timing. The LTC2159 can also phase-shift the CLKOUT+/CLKOUT– signals by serially programming mode control register A2. The output clock can be shifted by 0°, 45°, 90°, or 135°. To use the phase-shifting feature the clock duty cycle stabilizer must be turned on. Another control register bit can invert the polarity of CLKOUT+ and CLKOUT–, independently of the phase-shift. The combination of these two features enables phase-shifts of 45° up to 315° (Figure 14). ENC+ D0-D15, OF MODE CONTROL BITS PHASE SHIFT CLKINV CLKPHASE1 CLKPHASE0 0° 0 0 0 45° 0 0 1 90° 0 1 0 135° 0 1 1 180° 1 0 0 225° 1 0 1 270° 1 1 0 315° 1 1 1 CLKOUT+ 2159 F14 Figure 14. Phase-Shifting CLKOUT Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V RANGE) OF D15 – D0 (OFFSET BINARY) D15 – D0 (2’S COMPLEMENT) >1.000000V +0.999970V +0.999939V 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 1111 0111 1111 1111 1111 0111 1111 1111 1110 +0.000030V +0.000000V –0.000030V –0.000061V 0 0 0 0 1000 1000 0111 0111 0000 0000 1111 1111 –0.999939V –1.000000V < –1.000000V 0 0 1 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 0000 0000 1111 1111 0001 0000 1111 1110 0000 0000 1111 1111 0000 0000 1111 1111 0001 0000 1111 1110 1000 0000 0000 0001 1000 0000 0000 0000 1000 0000 0000 0000 2159f 20 LTC2159 Applications Information DATA FORMAT PC BOARD Table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. By default the output data format is offset binary. The 2’s complement format can be selected by serially programming mode control register A4. Digital Output Randomizer OF D15/D0 D15 D14/D0 Interference from the A/D digital outputs is sometimes unavoidable. Digital interference may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can cause unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. The digital output is randomized by applying an exclusiveOR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied —an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT outputs are not affected. The output randomizer is enabled by serially programming mode control register A4. CLKOUT CLKOUT OF OF D15 D15/D0 D14 D2 CLKOUT FPGA D14/D0 • • • D2/D0 RANDOMIZER ON D1 D1/D0 D0 D0 2159 F15 Figure 15. Functional Equivalent of Digital Output Randomizer LTC2159 D2/D0 • • • D14 D2 D1/D0 D1 D0 D0 2159 F16 Figure 16. Unrandomizing a Randomized Digital Output Signal Alternate Bit Polarity Another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. When this mode is enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, D13, D15) are inverted before the output buffers. The even bits (D0, D2, D4, D6, D8, D10, D12, D14), OF and CLKOUT are not affected. This can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. When there is a very small signal at the input of the A/D that is centered around mid-scale, the digital outputs toggle between mostly 1’s and mostly 0’s. This simultaneous switching of most of the bits will cause large currents in the ground plane. By inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. This cancels current flow in the ground plane, reducing the digital noise. The digital output is decoded at the receiver by inverting the odd bits (D1, D3, D5, D7, D9, D11, D13, D15.) The alternate bit polarity mode is independent of the digital output randomizer—either, both or neither function can be on at the same time. The alternate bit polarity mode is enabled by serially programming mode control register A4. 2159f 21 LTC2159 applications information Digital Output Test Patterns To allow in-circuit testing of the digital interface to the A/D, there are several test modes that force the A/D data outputs (OF, D15 to D0) to known values: All 1s: all outputs are 1 All 0s: all outputs are 0 Alternating: outputs change from all 1s to all 0s on alternating samples. Checkerboard: outputs change from 10101010101010101 to 01010101010101010 on alternating samples. The digital output test patterns are enabled by serially programming mode control register A4. When enabled, the test patterns override all other formatting modes: 2’s complement, randomizer, alternate bit polarity. Output Disable The digital outputs may be disabled by serially programming mode control register A3. All digital outputs including OF and CLKOUT are disabled. The high-impedance disabled state is intended for in-circuit testing or long periods of inactivity—it is too slow to multiplex a data bus between multiple converters at full speed. When the outputs are disabled the ADC should be put into either sleep or nap mode. Sleep and Nap Modes The A/D may be placed in sleep or nap modes to conserve power. In sleep mode the entire device is powered down, resulting in 1mW power consumption. The amount of time required to recover from sleep mode depends on the size of the bypass capacitors on VREF, REFH, and REFL. For the suggested values in Figure 8, the A/D will stabilize after 2ms. In nap mode the A/D core is powered down while the internal reference circuits stay active, allowing faster wake-up than from sleep mode. Recovering from nap mode requires at least 100 clock cycles. If the application demands very accurate DC settling then an additional 50µs should be allowed so the on-chip references can settle from the slight temperature shift caused by the change in supply current as the A/D leaves nap mode. Sleep mode and nap mode are enabled by mode control register A1 (serial programming mode), or by SDI and SDO (parallel programming mode). DEVICE PROGRAMMING MODES The operating modes of the LTC2159 can be programmed by either a parallel interface or a simple serial interface. The serial interface has more flexibility and can program all available modes. The parallel interface is more limited and can only program some of the more commonly used modes. Parallel Programming Mode To use the parallel programming mode, PAR/SER should be tied to VDD. The CS, SCK, SDI and SDO pins are binary logic inputs that set certain operating modes. These pins can be tied to VDD or ground, or driven by 1.8V, 2.5V, or 3.3V CMOS logic. When used as an input, SDO should be driven through a 1kΩ series resistor. Table 2 shows the modes set by CS, SCK, SDI and SDO. Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD) PIN DESCRIPTION CS Clock Duty Cycle Stabilizer Control Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On SCK Digital Output Mode Control Bit 0 = Full Rate CMOS Output Mode 1 = Double Data Rate LVDS Output Mode (3.5mA LVDS Current, Internal Termination Off) SDI/SDO Power-Down Control Bits 00 = Normal Operation 01 = Not Used 10 = Nap Mode 11 = Sleep Mode (Entire Device Powered Down) 2159f 22 LTC2159 Applications Information Serial Programming Mode To use the serial programming mode, PAR/SER should be tied to ground. The CS, SCK, SDI and SDO pins become a serial interface that program the A/D mode control registers. Data is written to a register with a 16-bit serial word. Data can also be read back from a register to verify its contents. Serial data transfer starts when CS is taken low. The data on the SDI pin is latched at the first 16 rising edges of SCK. Any SCK rising edges after the first 16 are ignored. The data transfer ends when CS is taken high again. The first bit of the 16-bit input word is the R/W bit. The next seven bits are the address of the register (A6:A0). The final eight bits are the register data (D7:D0). If the R/W bit is low, the serial data (D7:D0) will be written to the register set by the address bits (A6:A0). If the R/W bit is high, data in the register set by the address bits (A6:A0) will be read back on the SDO pin (see the Timing Diagrams). During a read back command the register is not updated and data on SDI is ignored. The SDO pin is an open drain output that pulls to ground with a 200Ω impedance. If register data is read back through SDO, an external 2k pull-up resistor is required. If serial data is only written and read back is not needed, then SDO can be left floating and no pull-up resistor is needed. Table 3 shows a map of the mode control registers. Software Reset If serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. The first serial command must be a software reset which will reset all register data bits to logic 0. To perform a software reset, bit D7 in the reset register is written with a logic 1. After the reset SPI write command is complete, bit D7 is automatically set back to zero. Table 3. Serial Programming Mode Register Map (PAR/SER = GND) REGISTER A0: RESET REGISTER (ADDRESS 00h) D7 D6 D5 D4 D3 D2 D1 D0 RESET X X X X X X X RESET Bits 7 Software Reset Bit 0 = Not Used 1 = Software Reset. All Mode Control Registers are reset to 00h. The ADC is momentarily placed in sleep mode. This bit is automatically set back to zero at the end of the SPI write command. The Reset register is write-only. Data read back from the reset register will be random. Bits 6-0 Unused, Don’t Care Bits REGISTER A1: POWER DOWN REGISTER (ADDRESS 01h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X PWROFF1 PWROFF0 Bits 7-2 Unused, Don’t Care Bits Bits 1-0 PWROFF1: PWROFF0 Power Down Control Bits 00 = Normal Operation 01 = Not Used 10 = Nap Mode 11 = Sleep Mode 2159f 23 LTC2159 applications information REGISTER A2: TIMING REGISTER (ADDRESS 02h) D7 D6 D5 D4 D3 D2 D1 D0 X X X X CLKINV CLKPHASE1 CLKPHASE0 DCS Bits 7-4 Unused, Don’t Care Bits Bit 3 CLKINV Output Clock Invert Bit 0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams) 1 = Inverted CLKOUT Polarity CLKPHASE1: CLKPHASE0 Bits 2-1 Output Clock Phase Delay Bits 00 = No CLKOUT Delay (as shown in the Timing Diagrams) 01 = CLKOUT+/CLKOUT– Delayed by 45° (Clock Period × 1/8) 10 = CLKOUT+/CLKOUT– Delayed by 90° (Clock Period × 1/4) 11 = CLKOUT+/CLKOUT– Delayed by 135° (Clock Period × 3/8) Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on. DCS Bit 0 Clock Duty Cycle Stabilizer Bit 0 = Clock Duty Cycle Stabilizer Off 1 = Clock Duty Cycle Stabilizer On REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h) D7 D6 D5 D4 D3 D2 D1 D0 X ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0 Bit 7 Unused, Don’t Care Bit Bits 6-4 ILVDS2: ILVDS0 LVDS Output Current Bits 000 = 3.5mA LVDS Output Driver Current 001 = 4.0mA LVDS Output Driver Current 010 = 4.5mA LVDS Output Driver Current 011 = Not Used 100 = 3.0mA LVDS Output Driver Current 101 = 2.5mA LVDS Output Driver Current 110 = 2.1mA LVDS Output Driver Current 111 = 1.75mA LVDS Output Driver Current Bit 3 TERMON LVDS Internal Termination Bit 0 = Internal Termination Off 1 = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS0. 2159f 24 LTC2159 Applications Information OUTOFF Bit 2 Output Disable Bit 0 = Digital outputs are enabled. 1 = Digital outputs are disabled and have high output impedance. Note: If the digital outputs are disabled the part should also be put in sleep mode or nap mode. OUTMODE1: OUTMODE0 Bits 1-0 Digital Output Mode Control Bits 00 = Full Rate CMOS Output Mode 01 = Double Data Rate LVDS Output Mode 10 = Double Data Rate CMOS Output Mode 11 = Not Used REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h) D7 D6 D5 D4 D3 D2 D1 D0 X X OUTTEST2 OUTTEST1 OUTTEST0 ABP RAND TWOSCOMP Bits 7-6 Unused, Don’t Care Bits Bits 5-3 OUTTEST2: OUTTEST0 Digital Output Test Pattern Bits 000 = Digital Output Test Patterns Off 001 = All Digital Outputs = 0 011 = All Digital Outputs = 1 101 = Checkerboard Output Pattern. OF, D15-D0 alternate between 1 0101 0101 0101 0101 and 0 1010 1010 1010 1010. 111 = Alternating Output Pattern. OF, D15-D0 alternate between 0 0000 0000 0000 0000 and 1 1111 1111 1111 1111. Note: Other bit combinations are not used. Bit 2 ABP Alternate Bit Polarity Mode Control Bit 0 = Alternate Bit Polarity Mode Off 1 = Alternate Bit Polarity Mode On. Forces the output format to be Offset Binary. Bit 1 RAND Data Output Randomizer Mode Control Bit 0 = Data Output Randomizer Mode Off 1 = Data Output Randomizer Mode On Bits 0 TWOSCOMP Two’s Complement Mode Control Bit 0 = Offset Binary Data Format 1 = Two’s Complement Data Format 2159f 25 LTC2159 applications information GROUNDING AND BYPASSING The LTC2159 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the ADC. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass capacitors must be located as close to the pins as possible. Size 0402 ceramic capacitors are recommended. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. Of particular importance is the capacitor between REFH and REFL. This capacitor should be on the same side of the circuit board as the A/D, and as close to the device as possible. The analog inputs, encode signals, and digital outputs should not be routed next to each other. Ground fill and grounded vias should be used as barriers to isolate these signals from each other. HEAT TRANSFER Most of the heat generated by the LTC2159 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. This pad should be connected to the internal ground planes by an array of vias. 2159f 26 LTC2159 Typical Applications Silkscreen Top Top Side 2159f 27 LTC2159 Typical applications Inner Layer 2 Inner Layer 3 2159f 28 LTC2159 Typical applications Inner Layer 4 Inner Layer 5 Bottom Side 2159f 29 LTC2159 Typical applications C23 2.2µF SDO SENSE VDD C19 0.1µF 48 C51 0.1µF AIN+ AIN– C15 0.1µF C21 0.1µF – + – + CN1 + – + – PAR/SER VDD C18 0.1µF 47 46 45 44 43 42 VDD VDD SENSE VREF SDO GND OF 1 VCM 2 AIN+ 3 AIN– 4 GND 5 REFH 6 REFL LTC2159 7 REFH 8 REFL 9 PAR/SER 10 GND 11 GND 12 VDD VDD GND ENC+ ENC– CS 13 14 15 16 17 41 40 39 SCK SDI GND D0 18 19 38 37 DNC D15 D14 D13 D12 36 D11 35 D10 34 D9 33 D8 32 OVDD 31 OGND 30 CLKOUT+ 29 CLKOUT– 28 D7 27 D6 26 D5 25 D4 20 21 D1 22 D2 23 0VDD C37 0.1µF DIGITAL OUTPUTS D3 24 2159 TA02 C28 0.1µF C32 0.1µF R51 100Ω SPI PORT ENCODE CLOCK 2159f 30 LTC2159 Package Description UK Package 48-Lead Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704 Rev C) 0.70 0.05 5.15 0.05 5.50 REF (4 SIDES) 6.10 0.05 7.50 0.05 5.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 0.10 (4 SIDES) 0.75 0.05 R = 0.10 TYP R = 0.115 TYP 47 48 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 CHAMFER C = 0.35 5.50 REF (4-SIDES) 5.15 0.10 5.15 0.10 (UK48) QFN 0406 REV C 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 2159f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31 LTC2159 Typical Application Integral Non-Linearity (INL) 1.8V 1.8V OVDD VDD 4.0 3.0 2.0 16-BIT ADC CORE S/H OUTPUT DRIVERS 20MHz D15 • • • D0 1.0 0 –1.0 –2.0 CLOCK CONTROL CLOCK CMOS, DDR CMOS OR DDR LVDS OUTPUTS INL ERROR (LSB) ANALOG INPUT –3.0 –4.0 GND 2159 TA03a OGND 0 16384 32768 49152 OUTPUT CODE 65536 2159 TA03b Related Parts PART NUMBER ADCs LTC2259-14/LTC2260-14/ LTC2261-14 LTC2262-14 DESCRIPTION COMMENTS 14-Bit, 80Msps/105Msps/125Msps 1.8V ADCs, Ultralow Power 14-Bit, 150Msps 1.8V ADC, Ultralow Power LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps LTC2268-14 1.8V Dual ADCs, Ultralow Power LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps LTC2268-12 1.8V Dual ADCs, Ultralow Power LTC2208 16-Bit, 130Msps 3.3V ADC LTC2207/LTC2206 16-Bit, 105Msps/80Msps 3.3V ADCs LTC2217/LTC2216 16-Bit, 105Msps/80Msps 3.3V ADCs RF Mixers/Demodulators LTC5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator LTC5527 400MHz to 3.7GHz High Linearity Downconverting Mixer LTC5557 400MHz to 3.8GHz High Linearity Downconverting Mixer LTC5575 800MHz to 2.7GHz Direct Conversion Quadrature Demodulator Amplifiers/Filters LTC6412 800MHz, 31dB Range, Analog-Controlled Variable Gain Amplifier LTC6420-20 1.8GHz Dual Low Noise, Low Distortion Differential ADC Drivers for 300MHz IF LTC6421-20 1.3GHz Dual Low Noise, Low Distortion Differential ADC Drivers LTC6605-7/LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz LTC6605-14 Filters with ADC Drivers Signal Chain Receivers 14-Bit Dual Channel IF/Baseband LTM®9002 Receiver Subsystem 89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-40 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs, 6mm × 6mm QFN-40 216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-40 216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs, 6mm × 6mm QFN-40 1250mW, 77.7dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 900mW/725mW, 77.9dB SNR, 100dB SFDR, CMOS Outputs, 7mm × 7mm QFN-48 1190mW/970mW, 81.2dB SNR, 100dB SFDR, CMOS/LVDS Outputs, 9mm × 9mm QFN-64 High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports 23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply Operation, Integrated Transformer High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF and LO Transformer Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure, 4mm × 4mm QFN-24 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier, 3mm × 4mm QFN-20 Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier, 3mm × 4mm QFN-20 Dual Matched 2nd Order Lowpass Filters with Differential Drivers, Pin-Programmable Gain, 6mm × 3mm DFN-22 Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers 2159f 32 Linear Technology Corporation LT 0312 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012