AD AD5429 Dual 8-,10-,12-bit high bandwidth multiplying dacs with serial interface Datasheet

Dual 8-,10-,12-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5429/AD5439/AD5449
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5429/AD5439/AD5449
RFB
R
VDD
RFBA
SYNC
SCLK
SHIFT
REGISTER
INPUT
REGISTER
DAC
REGISTER
IOUT1A
8-/10-/12-BIT
R-2R DAC A
IOUT2A
SDIN
SDO
LDAC
CLR
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
IOUT1B
8-/10-/12-BIT
R-2R DAC B
IOUT2B
RFB
R
LDAC
RFBB
VREFB
04464-0-001
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
±10 V reference input
Pin compatible 8-, 10-, and 12-bit DACs
Extended temperature range: −40°C to +125°C
16-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 µA typical current consumption
Figure 1.
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5429/AD5439/AD54491 are CMOS 8-, 10-, and 12-bit
dual-channel current output digital-to-analog converters,
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier.
These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros and the DAC outputs
are at zero scale.
As a result of manufacture on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication characteristics, with large signal multiplying bandwidths of 10 MHz.
The AD5429/AD5439/AD5449 DAC are available in 16-lead
TSSOP packages.
1
US Patent Number 5,689,257.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD5429/AD5439/AD5449
TABLE OF CONTENTS
Specifications..................................................................................... 3
Adding Gain................................................................................ 18
Timing Characteristics..................................................................... 5
Divider or Programmable Gain Element ................................ 18
Absolute Maximum Ratings............................................................ 7
Reference Selection .................................................................... 19
ESD Caution.................................................................................. 7
Amplifier Selection .................................................................... 19
Pin Configuration and Function Descriptions............................. 8
Serial Interface ................................................................................ 20
Terminology ...................................................................................... 9
Microprocessor Interfacing....................................................... 22
Typical Performance Characteristics ........................................... 10
PCB Layout and Power Supply Decoupling................................ 24
General Description ....................................................................... 15
Power Supplies for the Evaluation Board................................ 24
Unipolar Mode............................................................................ 15
Evaluation Board for the DACs................................................ 24
Bipolar Operation....................................................................... 16
Overview of AD54xx Devices....................................................... 28
Stability ........................................................................................ 16
Outline Dimensions ....................................................................... 29
Single-Supply Applications........................................................ 17
Ordering Guide .......................................................................... 29
Positive Output Voltage ............................................................. 17
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD5429/AD5439/AD5449
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2A, IOUT2B = 0 V. All specifications TMIN to TMAX, unless otherwise noted. DC performance measured
with OP1177, ac performance with AD9631, unless otherwise noted. Temperature range for Y version is −40°C to +125°C.
Table 1.
Parameter
STATIC PERFORMANCE
AD5429
Resolution
Relative Accuracy
Differential Nonlinearity
AD5439
Resolution
Relative Accuracy
Differential Nonlinearity
AD5449
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temp Coefficient1
Output Leakage Current
REFERENCE INPUT1
Reference Input Range
VREFA,VREFB Input Resistance
VREFA/B Input Resistance Mismatch
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIL
Input Capacitance
VDD = 4.5 V to 5.5 V
Output Low Voltage, VOL
Output High Voltage, VOH
VDD = 2.5 V to 3.6 V
Output Low Voltage, VOL
Output High Voltage, VOH
DYNAMIC PERFORMANCE1
Reference Multiplying BW
Output Voltage Settling Time
AD5429
AD5439
AD5449
Digital Delay
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Min
Typ
Max
Unit
Conditions
8
±0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
10
±0.5
±1
Bits
LSB
LSB
Guaranteed monotonic
12
±1
−1/+2
±10
±5
±10
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
±10
10
1.6
12
2.5
V
kΩ
%
0.8
0.7
1
10
V
V
V
µA
pF
VDD = 2.5 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
0.4
V
V
ISINK = 200 µA
ISOURCE = 200 µA
10
MHz
50
55
100
110
ns
ns
90
20
3
160
40
ns
ns
nV-s
±5
8
1.7
VDD − 1
VDD − 0.5
−75
dB
Rev. 0 | Page 3 of 32
Guaranteed monotonic
Data = 0000H, TA = 25°C, IOUT1
Data = 0000H, IOUT1
Typical resistor TC = −50 ppm/°C
DAC input resistance
Typ = 25°C, max = 125°C
VREF = 5 V p-p, DAC loaded all 1s
Measured to ±4 mV of FS, RLOAD = 100 Ω,
CLOAD = 0s
DAC latch alternately loaded with 0s
and 1s
RLOAD = 100 Ω, CLOAD = 15 pF
1 LSB change around major carry,
VREF = 0 V
DAC latch loaded with all 0s,
reference = 10 kHz
AD5429/AD5439/AD5449
Parameter
Output Capacitance
Digital Feedthrough
5
Unit
pF
pF
nV-s
Total Harmonic Distortion
−75
−75
dB
dB
25
nV/√Hz
55
63
65
dB
dB
dB
50
60
62
dB
dB
dB
Output Noise Spectral Density
SFDR PERFORMANCE (Wideband)
Clock = 10 MHz
500 kHz fout
100 kHz fout
50 kHz fout
Clock = 25 MHz
500 kHz fout
100 kHz fout
50 kHz fout
SFDR PERFORMANCE (Narrow Band)
Clock = 10 MHz
500 kHz fout
100 kHz fout
50 kHz fout
Clock = 25 MHz
500 kHz fout
100 kHz fout
50 kHz fout
INTERMODULATION DISTORTION
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz
f1 = 40 kHz, f2 = 50 kHz
POWER REQUIREMENTS
Power Supply Range
IDD
Power Supply Sensitivity1
1
Min
Typ
Max
2
4
Conditions
DAC latches loaded with all 0s
DAC latches loaded with all 1s
Feedthrough to DAC output with CS high
and alternate loading of all 0s and all 1s
VREF = 5 V p-p, all 1s loaded, f = 1 kHz
VREF = 5 V, sine wave generated from
digital code
@ 1 kHz
AD5449, 65 k codes, VREF = 3.5 V
AD5449, 65 k codes, VREF = 3.5 V
73
80
87
dB
dB
dB
70
75
80
dB
dB
dB
AD5449, 65 k codes, VREF = 3.5 V
65
72
dB
dB
51
65
dB
dB
2.5
5.5
10
0.001
V
µA
%/%
Guaranteed by design and characterization, not subject to production test.
Rev. 0 | Page 4 of 32
Logic inputs = 0 V or VDD
∆VDD = ±5%
AD5429/AD5439/AD5449
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
See Figure 2 and Figure 3. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to
production test. All input signals are specified with tr = tf = ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Table 2.
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t122
1
2
Limit at TMIN, TMAX
50
20
8
8
13
5
4
5
30
0
12
10
25
60
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conditions/Comments1
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK falling edge
Minimum SYNC high time
SCLK falling edge to LDAC falling edge
LDAC pulse width
SCLK falling edge to LDAC rising edge
SCLK active edge to SDO valid, strong SDO driver
SCLK active edge to SDO valid, weak SDO driver
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.
Rev. 0 | Page 5 of 32
AD5429/AD5439/AD5449
t1
SCLK
t2
t4
t8
t3
t7
SYNC
t6
t5
DB0
DB15
DIN
t9
t10
LDAC1
t11
LDAC2
04464-0-002
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE
2SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
t1
SCLK
t2
t4
t3
t7
SYNC
t6
t8
t5
SDIN
DB0
(N)
DB15
(N)
DB15
(N+1)
DB0
(N+1)
DB15
(N)
DB0
(N)
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200µA
VOH (MIN) + VOL (MAX)
2
CL
50pF
200µA
IOH
Figure 4. Load Circuit for SDO Timing Specifications
Rev. 0 | Page 6 of 32
04464-0-004
TO OUTPUT
PIN
IOL
04464-0-003
t12
AD5429/AD5439/AD5449
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDD to GND
VREF, RFB to GND
IOUT1, IOUT2 to GND
Input Current to Any Pin except Supplies
Logic Inputs and Output1
Operating Temperature Range
Extended (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP θJA Thermal Impedance
Lead Temperature, Soldering (10 s)
IR Reflow, Peak Temperature (< 20 s)
1
Rating
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
±10 mA
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
150°C/W
300°C
235°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C unless otherwise noted.
Overvoltages at SCLK, SYNC, and DIN are clamped by internal diodes.
Current should be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 32
AD5429/AD5439/AD5449
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOUT1A 1
16
IOUT2A
2
15
IOUT2B
RFBA
3
14
RFBB
VREFA
4
GND
5
LDAC
6
SCLK
7
10
SDIN
8
9
TOP VIEW
(Not to Scale)
13
VREFB
12
VDD
11
CLR
SYNC
SDO
NC = NO CONNECT
04464-0-005
AD5429/
AD5439/
AD5449
IOUT1B
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
Mnemonic
IOUT1A
IOUT2A
3
4
5
6
RFBA
VREFA
GND
LDAC
7
SCLK
8
SDIN
9
SDO
10
SYNC
11
CLR
12
13
14
15
VDD
VREFB
RFBB
IOUT2B
16
IOUT1B
Function
DAC A Current Output.
DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
DAC A Reference Voltage Input Pin.
Ground Pin.
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous
update mode is selected whereby the DAC is updated on the 16th clock falling edge when the device is in
standalone mode, or on the rising edge of SYNC when in daisy-chain mode.
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to rising edge.
Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges
to the active clock edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on
the active edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched
to the shift register on the16th active clock edge.
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware CLR pin as a clear to zero scale or midscale as required.
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC B Reference Voltage Input Pin.
DAC B Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
DAC B Current Output.
Rev. 0 | Page 8 of 32
AD5429/AD5439/AD5449
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is typically expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF − 1 LSB. Gain error of the
DACs is adjustable to zero with external resistance.
Output Leakage Current
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the IOUT1 terminal, it can
be measured by loading all 0s to the DAC and measuring the
IOUT1 current. Minimum current flows in the IOUT2 line when
the DAC is loaded with all 1s.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Digital Crosstalk
The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s and vice
versa) in the input register of the other DAC. It is expressed in
nV-s.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa), while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
Channel-to-Channel Isolation
The proportion of input signal from the reference input of one
DAC that appears at the output of the other DAC. It is expressed
in dB.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth.
THD = 20 log
Output Current Settling Time
The amount of time needed for the output to settle to a
specified level for a full-scale input change. For these devices,
it is specified with a 100 Ω resistor to ground.
Digital-to-Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s,
depending upon whether the glitch is measured as a current
or voltage signal.
V1
Intermodulation Distortion
The DAC is driven by two combined sine wave references of
frequencies fa and fb. Distortion products are produced at
sum and difference frequencies of mfa ± nfb, where m,
n = 0, 1, 2, 3… Intermodulation terms are those for which m or
n is not equal to zero. The second-order terms include (fa + fb)
and (fa − fb) and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb) and (fa − 2fb). IMD is defined as
IMD = 20 log
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the IOUT pins and subsequently
into the following circuitry. This noise is digital feedthrough.
(V22 +V32 + V42 + V52 )
(rms sum of the sum and diff distortion products )
rms amplitude of the fundamental
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal, when all 0s are
loaded to the DAC.
Rev. 0 | Page 9 of 32
AD5429/AD5439/AD5449
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.20
0.10
0.05
0.05
DNL (LSB)
0.10
0
0
–0.05
–0.05
–0.10
–0.10
–0.15
–0.15
–0.20
0
50
TA = 25°C
VREF = 10V
VDD = 5V
0.15
100
150
200
250
CODE
–0.20
04462-0-007
0
50
200
250
Figure 9. DNL vs. Code (8-Bit DAC)
0.5
TA = 25°C
VREF = 10V
VDD = 5V
0.4
0.3
0.3
0.2
0.1
0.1
DNL (LSB)
0.2
0
–0.1
0
–0.1
–0.2
–0.2
–0.3
–0.3
–0.4
–0.4
200
400
600
800
1000
CODE
–0.5
04462-0-008
–0.5
0
TA = 25°C
VREF = 10V
VDD = 5V
0.4
0
200
400
600
800
1000
CODE
Figure 7. INL vs. Code (10-Bit DAC)
04462-0-011
0.5
INL (LSB)
150
CODE
Figure 6. INL vs. Code (8-Bit DAC)
Figure 10. DNL vs. Code (10-Bit DAC)
1.0
1.0
TA = 25°C
VREF = 10V
VDD = 5V
0.8
0.6
0.6
0.4
0.2
0.2
DNL (LSB)
0.4
0
–0.2
0
–0.2
–0.4
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
0
500
1000
TA = 25°C
VREF = 10V
VDD = 5V
0.8
1500
2000
2500
3000
CODE
3500
4000
04462-0-009
INL (LSB)
100
Figure 8. INL vs. Code (12-Bit DAC)
–1.0
0
500
1000
1500
2000
2500
3000
CODE
Figure 11. DNL vs. Code (12-Bit DAC)
Rev. 0 | Page 10 of 32
3500
4000
04462-0-012
INL (LSB)
0.15
04462-0-010
TA = 25°C
VREF = 10V
VDD = 5V
AD5429/AD5439/AD5449
0.6
8
0.5
7
TA = 25°C
0.4
6
MAX INL
CURRENT (mA)
INL (LSB)
0.3
0.2
TA = 25°C
VREF = 10V
VDD = 5V
0.1
5
VDD = 5V
4
3
0
MIN INL
2
–0.1
–0.2
1
–0.3
0
VDD = 3V
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE
0
Figure 12. INL vs. Reference Voltage
0.5
1.5
1.0
2.0
2.5
3.0
3.5
INPUT VOLTAGE (V)
4.0
4.5
5.0
04462-0-022
2
04462-0-013
VDD = 2.5V
Figure 15. Supply Current vs. Logic Input Voltage
–0.40
1.6
TA = 25°C
VREF = 10V
VDD = 5V
–0.45
1.4
1.2
IOUT1 VDD 5V
IOUT LEAKAGE (nA)
DNL (LSB)
–0.50
–0.55
–0.60
MIN DNL
1.0
0.8
IOUT1 VDD 3V
0.6
0.4
–0.65
3
4
5
6
7
8
9
10
REFERENCE VOLTAGE
0
–40
0
20
60
80
100
120
Figure 16. IOUT1 Leakage Current vs. Temperature
5
0.50
4
0.45
TA = 25°C
VDD = 5V
3
40
TEMPERATURE (°C)
Figure 13. DNL vs. Reference Voltage
VDD = 5V
0.40
2
CURRENT (µA)
0.35
1
0
VDD = 2.5V
–1
ALL 0s
0.30
0.15
0.10
VREF = 10V
–5
–60
–40
–20
VDD = 2.5V
0.20
–3
–4
ALL 1s
0.25
–2
ALL 1s
ALL 0s
0.05
0
20
40
60
80
100
TEMPERATURE (°C)
120
140
04462-0-015
ERROR (mV)
–20
Figure 14. Gain Error vs. Temperature
0
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. Supply Current vs. Temperature
Rev. 0 | Page 11 of 32
120
140
04462-0-024
2
04462-0-014
–0.70
04462-0-023
0.2
AD5429/AD5439/AD5449
14
3
VDD = 5V
0
GAIN (dB)
8
6
VDD = 3V
–3
4
VREF = ±2V, AD8038 CC 1.47pF
VREF = ±2V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1pF
VREF = ±0.15V, AD8038 CC 1.47pF
VREF = ±3.51V, AD8038 CC 1.8pF
–6
VDD = 2.5V
2
1
10
100
1k
10k
100k
1M
10M
–9
10k
04462-0-025
0
100M
FREQUENCY (Hz)
0.045
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
10
100
1M
10M
100M
OUTPUT VOLTAGE (V)
TA = 25°C
VDD = 5V
VREF = ±3.5V
INPUT
CCOMP = 1.8pF
AD8038 AMPLIFIER
1k
10k
100k
FREQUENCY (Hz)
10M
100M
TA = 25°C
VREF = 0V
AD8038 AMPLIFIER
CCOMP = 1.8pF
VDD = 5V
0.035
ALL OFF
1
7FF TO 800H
0.040
0.030
0.025
VDD = 3V
0.020
0.015
800 TO 7FFH
0.010
VDD = 3V
0.005
0
–0.005
04462-0-026
VDD = 5V
–0.010
0
20
40
60
80
100
120
140
160
180
200
TIME (ns)
Figure 19. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 22. Midscale Transition, VREF = 0 V
0.2
–1.68
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
CCOMP = 1.8pF
7FF TO 800H
–1.69
VDD = 5V
OUTPUT VOLTAGE (V)
–1.70
–0.2
–0.4
TA = 25°C
VDD = 5V
VREF = ±3.5V
CCOMP = 1.8pF
AD8038 AMPLIFIER
–0.6
10
100
–1.72
VDD = 3V
–1.73
VDD = 5V
–1.74
VDD = 3V
–1.76
800 TO 7FFH
–0.8
1
–1.71
–1.75
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
04462-0-027
GAIN (dB)
0
–1.77
0
20
40
60
80
100
120
140
160
TIME (ns)
Figure 23. Midscale Transition, VREF = 3.5 V
Figure 20. Reference Multiplying Bandwidth–All 1s Loaded
Rev. 0 | Page 12 of 32
180
200
04462-0-042
GAIN (dB)
TA = 25°C
LOADING
ZS TO FS
1M
FREQUENCY (Hz)
Figure 21. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
Figure 18. Supply Current vs. Update Rate
6
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
100k
04462-0-028
10
04462-0-041
12
IDD (mA)
TA = 25°C
VDD = 5V
TA = 25°C
LOADING ZS TO FS
AD5429/AD5439/AD5449
20
90
TA = 25°C
VDD = 3V
AMP = AD8038
0
80
MCLK = 5MHz
70
MCLK = 10MHz
–20
SFDR (dB)
PSRR (dB)
60
–40
FULL SCALE
–60
ZERO SCALE
50
MCLK = 25MHz
40
30
–80
20
–100
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
1
100
10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
0
100
200
300
400
500
600
700
900
1000
fOUT (kHz)
Figure 24. Power Supply Rejection vs. Frequency
Figure 27. Wideband SFDR vs. fOUT Frequency
–60
0
TA = 25°C
VDD = 3V
VREF = 3.5V p-p
–65
800
04462-0-046
–120
04462-0-043
10
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–30
SFDR (dB)
THD + N (dB)
–70
–75
–40
–50
–60
–80
–70
–85
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
–90
04462-0-044
–90
0
2
4
6
8
FREQUENCY (MHz)
10
12
04462-0-047
–80
Figure 28. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 25. THD + Noise vs. Frequency
100
0
MCLK = 1MHz
TA= 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
80
–20
SFDR (dB)
MCLK = 200kHz
60
MCLK = 0.5MHz
40
–40
–50
–60
–70
–80
20
TA = 25°C
VREF = 3.5V
AD8038 AMPLIFIER
0
20
40
60
80
100
120
140
160
180
fOUT (kHz)
200
–90
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
Figure 29. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Figure 26. Wideband SFDR vs. fOUT Frequency
Rev. 0 | Page 13 of 32
044620-048
0
04462-0-045
SFDR (dB)
–30
AD5429/AD5439/AD5449
0
0
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–20
–30
–40
–40
(dB)
–50
–50
–60
–60
–70
–70
–80
–80
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FREQUENCY (MHz)
4.0
4.5
5.0
Figure 30. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
0
–100
70
–20
85
95
90
100 105
FREQUENCY (MHz)
0
110
115
120
TA= 25°C
VDD = 5V
AMP = AD8038
65k CODES
–10
–20
–30
–40
–40
(dB)
–30
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
300
350
400
450 500 550 600
FREQUENCY (MHz)
650
700
750
04462-0-050
–100
250
80
Figure 33. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
75
04462-0-052
0
04462-0-049
–90
–90
–100
0
Figure 31. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
20
100
150
200
250
FREQUENCY (kHz)
300
350
400
Figure 34. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
300
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
0
50
04462-0-053
SFDR (dB)
–30
SFDR (dB)
TA= 25°C
VDD = 3V
AMP = AD8038
65k CODES
–10
TA = 25°C
AMP = AD8038
ZERO SCALE LOADED TO DAC
250
MIDSCALE LOADED TO DAC
OUTPUT NOISE (nV/ Hz)
FULL SCALE LOADED TO DAC
–40
–60
–80
150
100
50
60
70
80
90
100 110 120
FREQUENCY (MHz)
130
140
150
04462-0-051
–100
–120
50
200
0
100
1k
10k
FREQUENCY (Hz)
Figure 32. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Figure 35. Output Noise Spectral Density
Rev. 0 | Page 14 of 32
100k
04462-0-054
SFDR (dB)
–20
AD5429/AD5439/AD5449
GENERAL DESCRIPTION
The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit dualchannel current output DACs consisting of a standard inverting
R−2R ladder configuration. A simplified diagram of one DAC
channel for the AD5449 is shown in Figure 36. The feedback
resistor RFB has a value of R. The value of R is typically 10 kΩ
(minimum 8 kΩ and maximum 12 kΩ). If IOUT1 and IOUT2 are
kept at the same potential, a constant current flows in each
ladder leg, regardless of digital input code. Therefore, the input
resistance presented at VREF is always constant.
R
R
When an output amplifier is connected in unipolar mode, the
output voltage is given by
VOUT = − VREF × D / 2n
where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.
D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
R
VREFA
2R
2R
2R
2R
S1
S2
S3
S12
With a fixed 10 V reference, the circuit shown in Figure 37 gives
a unipolar 0 V to −10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
2R
2R
RFBA
IOUT1A
IOUT2A
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation for the AD5429.
04464-0-006
DAC DATA LATCHES
AND DRIVERS
Figure 36. Simplified Ladder
Table 5. Unipolar Code Table
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DACs, making the devices extremely versatile and allowing
them to be configured in several operating modes, such as
unipolar mode, bipolar output mode, or single-supply mode.
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
UNIPOLAR MODE
Analog Output (V)
−VREF (4095/4096)
−VREF (2048/4096) = −VREF/2
−VREF (1/4096)
−VREF (0/4096) = 0
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 37.
VDD
R2
VDD
VREF
VREF
R1
AD5429/
AD5439/
AD5449
SYNC SCLK SDIN
C1
RFBA
IOUT1A
A1
IOUT2A
GND
VOUT = 0V TO –VREF
µCONTROLLER
Figure 37. Unipolar Operation
Rev. 0 | Page 15 of 32
04464-0-007
AGND
NOTES:
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
3. DAC B OMITTED FOR CLARITY.
AD5429/AD5439/AD5449
BIPOLAR OPERATION
STABILITY
In some applications, it might be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and three external resistors, as shown in Figure 38.
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as closely as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking can occur, if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response, which can cause ringing or instability in the closedloop applications circuit.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. When connected in bipolar mode, the output
voltage is
(
)
VOUT = VREF × D / 2n −1 − VREF
As shown in Figure 37 and Figure 38, an optional compensation
capacitor, C1, can be added in parallel with RFB for stability. Too
small a value of C1 can produce ringing at the output, while too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.
D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation with the AD5429.
Table 6. Bipolar Code Table
Analog Output (V)
+VREF (2047/2048)
0
−VREF (2047/2048)
−VREF (2048/2048)
R3
20kΩ
VDD
VDD
R1
VREF ±10V
VREF
AD5429/
AD5439/
AD5449
SYNC SCLK SDIN
µCONTROLLER
R2
RFBA
IOUT1A
R5
20kΩ
C1
A1
R4
10kΩ
A2
IOUT2A
VOUT = –VREF TO +VREF
GND
AGND
NOTES:
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
4. DAC B AND ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. Bipolar Operation
Rev. 0 | Page 16 of 32
04464-0-008
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
AD5429/AD5439/AD5449
SINGLE-SUPPLY APPLICATIONS
POSITIVE OUTPUT VOLTAGE
Voltage-Switching Mode
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and −2.5 V, respectively, as shown in Figure 40.
Figure 39 shows the DACs operating in voltage-switching mode.
The reference voltage, VIN, is applied to the IOUT1 pin, IOUT2 is
connected to AGND, and the output voltage is available at the
VREF terminal. In this configuration, a positive reference voltage
results in a positive output voltage, making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance). Therefore, an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
Note that VIN is limited to low voltages, because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and this degrades
the integral linearity of the DAC. Also, VIN must not go negative
by more than 0.3 V or an internal diode turns on, exceeding the
maximum ratings of the device. In this type of application, the
DAC’s full range of multiplying capability is lost.
VDD
R1
RFB
IOUT1
VIN
R2
VDD
VOUT
VREF
IOUT2
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
04464-0-009
GND
Figure 39. Single-Supply Voltage-Switching Mode
VDD = +5V
ADR03
VOUT
VIN
GND
+5V
–2.5V
1/2 AD8552
VREF 8-/10-/12-BIT
DAC
RFB
C1
IOUT1
IOUT2
GND
–5V
VOUT = 0V TO +2.5V
1/2 AD8552
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 40. Positive Voltage Output with Minimum Components
Rev. 0 | Page 17 of 32
04464-0-010
VDD
AD5429/AD5439/AD5449
ADDING GAIN
In applications in which the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. Be sure to take
into consideration the effect of temperature coefficients of the
thin film resistors of the DAC. Simply placing a resistor in series
with the RFB resistor causes mismatches in the temperature
coefficients, resulting in larger gain temperature coefficient
errors. Instead, the circuit of Figure 41 is a recommended
method of increasing the gain of the circuit. R1, R2, and R3
should all have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits in which gains of > 1
are required.
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0 × 10 (00010000)—that is, 16 decimal—in the circuit of
Figure 42 should cause the output voltage to be 16 × VIN.
However, if the DAC has a linearity specification of ±0.5 LSB,
then D can, in fact, have a weight in the range 15.5/256 to
16.5/256, so that the possible output voltage is in the range
15.5 VIN to 16.5 VIN with an error of +3%, even though the DAC
itself has a maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction D of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage has to change
as follows:
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp, and RFB is used as the input
resistor, as shown in Figure 42, then the output voltage is
inversely proportional to the digital input fraction D. For
D = 1 − 2n the output voltage is
where R is the DAC resistance at the VREF terminal. For a DAC
leakage current of 10 nA, R = 10 kΩ and a gain (that is, 1/D) of
16, the error voltage is 1.6 mV.
)
VDD
VIN
R2
VREF
C1
RFB
8-/10-/12-BIT
DAC
IOUT1
VOUT
IOUT2
R3
GND
GAIN =
R2
R2 + R3
R2
R2R3
R1 =
R2 + R3
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Increasing Gain of Current Output DAC
VDD
VIN
RFB
VDD
IOUT1
VREF
IOUT2
GND
VOUT
NOTE:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 42. Current-Steering DAC Used as a Divider
or Programmable Gain Element
Rev. 0 | Page 18 of 32
04464-0-011
VDD
04464-0-012
VOUT = − VIN / D = − VIN / (1 − 2
−n
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
AD5429/AD5439/AD5449
REFERENCE SELECTION
When selecting a reference for use with the AD5429/AD5439/
AD5449 family of current output DACs, pay attention to the
reference’s output voltage temperature coefficient specification.
This parameter affects not only the full-scale error, but also
the linearity (INL and DNL) performance. The reference
temperature coefficient should be consistent with the system
accuracy specifications. For example, an 8-bit system required
to hold its overall specification to within 1 LSB over the
temperature range 0°C to 50°C dictates that the maximum
system drift with temperature should be less than 78 ppm/°C.
A 12-bit system with the same temperature range to overall
specification within 2 LSBs requires a maximum drift of
10 ppm/°C. By choosing a precision reference with low output
temperature coefficient, this error source can be minimized.
Table 7 lists some of the references available from Analog
Devices that are suitable for use with this range of current
output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. The input bias current of an op amp also
generates an offset at the voltage output as a result of the bias
current flowing in the feedback resistor RFB. Most op amps have
input bias currents low enough to prevent any significant errors
in 12-bit applications.
Common-mode rejection of the op amp is important in
voltage-switching circuits, because it produces a codedependent error at the voltage output of the circuit. Most
op amps have adequate common-mode rejection for use at
8-, 10-, and 12-bit resolution.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output
op amp. To obtain minimum settling time in this configuration,
it is important to minimize capacitance at the VREF node
(voltage output node in this application) of the DAC. This is
done by using low input capacitance buffer amplifiers and
careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. Analog Devices supplies a large range
of single-supply amplifiers.
Table 7. Suitable ADI Precision References Recommended for Use with AD5429/AD5439/AD5449 DACs
Reference
ADR01
ADR02
ADR03
ADR425
Output Voltage
10 V
5V
2.5 V
5V
Initial Tolerance
0.1%
0.1%
0.2%
0.04%
Temperature Drift
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
0.1 Hz to 10 Hz Noise
20 µV p-p
10 µV p-p
10 µV p-p
3.4 µV p-p
Package
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
Table 8. Precision ADI Op Amps Suitable for Use with AD5429/AD5439/AD5449 DACs
Part No.
OP97
OP1177
AD8551
Max Supply Voltage (V)
±20
±18
±6
VOS (max) µV
25
60
5
IB (max) nA
0.1
2
0.05
GBP MHz
0.9
1.3
1.5
Slew Rate V/µs
0.2
0.7
0.4
VOS (max) µV
1500
1000
3000
IB max (nA)
0.01
1000
0.75
Table 9. High Speed ADI Op Amps Suitable for Use with AD5429/AD5439/AD5449 DACs
Part No.
AD8065
AD8021
AD8038
Max Supply Voltage (V)
±12
±12
±5
BW @ ACL (MHz)
145
200
350
Slew Rate (V/µs)
180
100
425
Rev. 0 | Page 19 of 32
AD5429/AD5439/AD5449
SERIAL INTERFACE
SDO Control (SDO1 and SDO2)
The AD5429/AD5439/AD5449 have an easy to use, 3-wire
interface that is compatible with SPI, QSPI, MICROWIRE, and
DSP interface standards. Data is written to the device in 16-bit
words. This 16-bit word consists of 4 control bits and either
8, 10, or 12 data bits, as shown in Figure 43, Figure 44, and
Figure 45.
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an opendrain driver. The strength of the SDO driver affects the timing
of t12, and, when stronger, allows a faster clock cycle.
Table 10. SDO Control Bits
Low Power Serial Interface
SDO2
0
0
1
1
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.
SDO1
0
1
0
1
Function Implemented
Full SDO driver
SDO configured as open-drain
Weak SDO driver
Disable SDO output
DAC Control Bits C3–C0
Control bits C3 to C0 allow control of various functions of
the DAC, as shown in Table 11. Default setting of the DAC at
power-on are as follows.
Daisy-Chain Control (DSY)
DSY allows the enabling or disabling of daisy-chain mode.
A 1 enables daisy-chain mode, and 0 disables daisy-chain mode.
When disabled, a readback request is accepted, SDO is automatically enabled, the DAC register contents of the relevant
DAC are clocked out on SDO, and, when complete, SDO is
disabled again.
Data is clocked into the shift register on falling clock edges;
daisy-chain mode is enabled. The device powers on with zeroscale load to the DAC register and IOUT lines. The DAC control
bits allow the user to adjust certain features at power-on; for
example, daisy-chaining can be disabled if not in use, active
clock edge can be changed to rising edge, and DAC output can
be cleared to either zero scale or midscale. The user can also
initiate a readback of the DAC register contents for verification.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR bit is to clear the
registers and DAC output to zero code. A 1 in the HCLR bit
allows the CLR pin to clear the DAC outputs to midscale and
a 0 clears to zero scale.
Control Register (Control Bits = 1101)
While maintaining software compatibility with the singlechannel current output DACs (AD5426/AD5432/AD5443),
these DACs also feature some additional interface functionality.
Set the control bits to 1101 to enter control register mode.
Figure 46 shows the contents of the control register. The
following sections describe the functions of the control register.
Active Clock Edge (SCLK)
The default active clock edge is falling edge. Write a 1 to this bit
to clock data in on the rising edge, or a 0 for falling edge.
C3
C2
DB0 (LSB)
C1
C0
DB7
DB6
DB5
DB4
DB3
CONTROL BITS
DB2
DB1
DB0
0
0
0
0
DATA BITS
04464-0-013
DB15 (MSB)
Figure 43. AD5429 8-Bit Input Shift Register Contents
C3
C2
DB0 (LSB)
C1
C0
DB9
DB8
DB7
DB6
DB5
CONTROL BITS
DB4
DB3
DB2
DB1
DB0
0
0
DATA BITS
04464-0-014
DB15 (MSB)
Figure 44. AD5439 10-Bit Input Shift Register Contents
C3
C2
DB0 (LSB)
C1
CONTROL BITS
C0
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DATA BITS
Figure 45. AD5449 12-Bit Input Shift Register Contents
Rev. 0 | Page 20 of 32
DB3
DB2
DB1
DB0
04464-0-015
DB15 (MSB)
AD5429/AD5439/AD5449
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling to SCLK falling edge setup time, t4.
Daisy-Chain Mode
Daisy-chain mode is the default power-on mode. To disable the
daisy-chain function, write 1001 to the control word. In daisychain mode, the internal gating on SCLK is disabled. The SCLK
is continuously applied to the input shift register when SYNC is
low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default, use
the control word to change the active edge) and is valid for the
next device on the falling edge (default). By connecting this line
to the SDIN input on the next device in the chain, a multidevice
interface is constructed. For each device in the system, 16 clock
pulses are required. Therefore, the total number of clock cycles
must equal 16, where N is the total number of devices in the
chain. See Figure 3.
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
number of clock cycles can be used and SYNC taken high some
time later. After the rising edge of SYNC, data is automatically
transferred from each device’s input shift register to the
addressed DAC. When control bits = 0000, the device is in no
operation mode. This might be useful in daisy-chain applications, in which the user does not wish to change the settings of a
particular DAC in the chain. Write 0000 to the control bits for
that DAC, and the following data bits are ignored.
Standalone Mode
After power-on, write 1001 to the control word to disable daisychain mode. The first falling edge of SYNC resets a counter that
counts the number of serial clocks to ensure that the correct
number of bits are shifted in and out of the serial shift registers.
A SYNC edge during the 16-bit write cycle causes the device to
abort the current write cycle.
After the falling edge of the 16th SCLK pulse, data is automatically transferred from the input shift register to the DAC. In
order for another serial transfer to take place, the counter must
be reset by the falling edge of SYNC.
LDAC Function
The LDAC function allows asynchronous or synchronous
updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is
held permanently low, an automatic or synchronous update
mode is selected, whereby the DAC is updated on the 16th clock
falling edge when the device is in standalone mode, or on the
rising edge of SYNC when in daisy-chain mode.
Table 11. DAC Control Bits
C2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC
A and B
A
A
A
B
B
B
A and B
A and B
-
Function Implemented
No operation (power-on default)
Load and update
Initiate readback
Load input register
Load and update
Initiate readback
Load input register
Update DAC outputs
Load input registers
Daisy chain disable
Clock data to shift register on rising edge
Clear DAC output to zero scale
Clear DAC output to midscale
Control word
Reserved
No operation
DB15 (MSB)
1
1
DB0 (LSB)
0
1
SDO2 SDO1
DSY HCLR SCLK
X
X
CONTROL BITS
Figure 46. Control Register Loading Sequence
Rev. 0 | Page 21 of 32
X
X
X
X
X
04464-0-016
C3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AD5429/AD5439/AD5449
Software LDAC Function
Load and update mode can also function as a software update
function, irrespective of the voltage level on the LDAC pin.
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface
expects a t4 SYNC falling edge to SCLK falling edge setup time)
of 13 ns minimum. See the ADSP-21xx User Manual for details
on clock and frame sync frequencies for the SPORT register.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to this family of DACs is via a serial
bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is
a 3-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5429/AD5439/AD5449
require a 16-bit word with the default being data valid on the
falling edge of SCLK, but this is changeable via the control bits
in the data-word.
Table 12 shows how the SPORT control register must be set up.
Table 12.
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
ADSP-21xx to AD5429/AD5439/AD5449 Interface
The ADSP-21xx family of DSPs is easily interfaced to this
family of DACs without the need for extra glue logic. Figure 47
is an example of an SPI interface between the DAC and the
ADSP-2191M. SCK of the DSP drives the serial data line, DIN.
SYNC is driven from one of the port lines, in this case SPIxSEL.
AD5429/AD5439/
AD5449*
SPIxSEL
80C51/80L51 to AD5429/AD5439/AD5449 Interface
SYNC
SDIN
SCK
SCLK
04464-0-027
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. ADSP-2191 SPI to AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 48. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP’s serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
AD5429/AD5439/
AD5449*
TFS
SYNC
DT
SDIN
SCLK
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 49. TxD of the 80C51/80L51drives SCLK of the
DAC serial interface, while RxD drives the serial data line, DIN.
P1.1 is a bit-programmable pin on the serial port and is used to
drive SYNC. When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RXD is clocked out of
the microcontroller on the rising edge of TXD and is valid on
the falling edge. As a result, no glue logic is required between
the DAC and microcontroller interface. P1.1 is taken high
following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
into account.
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to
AD5429/AD5439/AD5449 Interface
AD5429/AD5439/
AD5449*
80C51*
04464-0-028
ADSP-2101/
ADSP-2103/
ADSP-2191*
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
TxD
SCLK
RxD
SDIN
P1.1
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 49. 80C51/80L51 to AD5429/AD5439/AD5449 Interface
Rev. 0 | Page 22 of 32
04464-0-029
ADSP-2191*
Setting
1
1
00
1
1
1
1111
AD5429/AD5439/AD5449
MC68HC11 to AD5429/AD5439/AD5449 Interface
MICROWIRE to AD5429/AD5439/AD5449 Interface
Figure 50 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the
clock phase bit (CPHA) = 1. The SPI is configured by writing
to the SPI control register (SPCR)—see the 68HC11 User
Manual. The SCK of the 68HC11 drives the SCLK of the DAC
interface; the MOSI output drives the serial data line (DIN) of
the AD5429/AD5439/AD5449.
Figure 51 shows an interface between the DAC and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the
DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
MICROWIRE*
PIC16C6x/7x to AD5429/AD5439/AD5449
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual.
In this example, the I/O port RA1 is used to provide a SYNC
signal and enable the serial port of the DAC. This microcontroller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 52 shows the connection diagram.
SYNC
SCLK
MOSI
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
PIC16C6x/7x*
Figure 50. MCH68HC11/68L11 to AD5429/AD5439/AD5449 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11, and, with SYNC low, the shift register clocks
data out on the rising edges of SCLK.
SYNC
Figure 51. MICROWIRE to AD5429/AD5439/AD5449 Interface
04464-0-030
PC7
SDIN
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5429/AD5439/
AD5449*
SCK
SCLK
AD5429/AD5439/
AD5449*
SCK/RC3
SCLK
SDI/RC4
SDIN
RA1
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 52. PIC16C6x/7x to AD5429/AD5439/AD5449 Interface
Rev. 0 | Page 23 of 32
04464-0-032
MC68HC11*
SK
SO
04464-0-031
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5429/AD5439/AD5449, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only 8 falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.
AD5429/AD5439/
AD5449*
AD5429/AD5439/AD5449
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the DAC is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the DAC is in a system in which
multiple devices require an AGND to DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
It is good practice to employ compact, minimum lead-length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
These DACs should have ample supply bypassing of 10 µF
in parallel with 0.1 µF on the supply located as close to the
package as possible, ideally right up against the device. The
0.1 µF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
The board requires ±12 V and +5 V supplies. The 12 V VDD
and VSS are used to power the output amplifier, while the 5 V
is used to power the DAC (VDD1) and transceivers (VCC).
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane, while signal traces
are placed on the soldered side.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
POWER SUPPLIES FOR THE EVALUATION BOARD
Both supplies are decoupled to their respective ground plane
with 10 µF tantalum and 0.1 µF ceramic capacitors.
EVALUATION BOARD FOR THE DACS
The evaluation board includes a DAC from the AD5429/
AD5439/AD5449 family and a current-to-voltage amplifier,
AD8065. On the evaluation board is a 10 V reference, ADR01.
An external reference can also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software allows the user to
write a code to the device.
Rev. 0 | Page 24 of 32
Figure 53. Schematic of the Evaluation Board
Rev. 0 | Page 25 of 32
04464-0-023
P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
P1–6
P1–13
P1–5
P1–4
P1–2
P1–3
P2–4
P2–1
P2–2
P2–3
LDAC
SDIN
SCLK
C15
0.1µF
C13
0.1µF
C11
0.1µF
+
+
+
A
B
C16
10µF
C14
10µF
C12
10µF
LK2
R1
10kΩ
VDD
R2
10kΩ
VDD
R3
10kΩ
VDD
SDO
VSS
VDD1
AGND
VDD
J6
J5
J4
J3
CLR
C3
10µF
J7
LDAC
SYNC
SDIN
SCLK
CLR
SDO
+
VDD
C4
0.1µF
RFBB
VREFA
IOUT2A
IOUT1A
RFBB
IOUT2B
IOUT1B
5 TRIM
3 +V
IN
4
GND
U2
J8
1
LK1 B
C5
0.1µF
VREFB
J9
VREFA
VOUT 4
VREFB
VREFA
5
13
4
2
1
3
15
16
14
C1
0.1µF
+
C2
10µF
VREFB
GND
LDAC
SYNC
SDIN
SCLK
12
VDD
AD5429/AD5439/
AD5449
11
9
6
10
8
7
U1
VDD1
A
C6
1.8pF
C17
1.8pF
3
VDD
7
V–
V+
U3
4
7
V–
V+
4
2
VSS
VDD
U4
3
2
VSS
C10
0.1µF
+
C9
10µF
AD8065AR
6
C8
0.1µF
+
C7
10µF
C21
0.1µF
+
C20
10µF
AD8065AR
6
C19
0.1µF
+
C18
10µF
TP1
TP2
J1
J2
VOUT A
VOUT B
AD5429/AD5439/AD5449
04464-0-024
AD5429/AD5439/AD5449
04464-0-025
Figure 54. Component-Side Artwork
Figure 55. Silkscreen—Component-Side View (Top)
Rev. 0 | Page 26 of 32
04464-0-026
AD5429/AD5439/AD5449
Figure 56. Solder-Side Artwork
Rev. 0 | Page 27 of 32
AD5429/AD5439/AD5449
OVERVIEW OF AD54xx DEVICES
Table 13.
Part No.
AD5424
AD5426
AD5428
AD5429
AD5450
AD5432
AD5433
AD5439
AD5440
AD5451
AD5443
AD5444
AD5415
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution
8
8
8
8
8
10
10
10
10
10
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
No. DACs
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
INL (LSB)
±0.25
±0.25
±0.25
±0.25
±0.25
±0.5
±0.5
±0.5
±0.5
±0.25
±1
±0.5
±1
±1
±1
±1
±0.5
±1
±2
±1
±1
±1
±1
±2
±2
±2
±2
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package
RU-16, CP-20
RM-10
RU-20
RU-10
RJ-8
RM-10
RU-20, CP-20
RU-16
RU-24
RJ-8
RM-10
RM-8
RU-24
RU-20, CP-20
RU-24
RU-16
RJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
RM-8
RU-38
RM-8
RU-28
RU-16
RU-38
Rev. 0 | Page 28 of 32
Features
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 58 MHz Serial
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 17 ns CS Pulse Width
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
10 MHz BW, 50 MHz Serial
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
4 MHz BW, 50 MHz Serial Clock
4 MHz BW, 20 ns WR Pulse Width
AD5429/AD5439/AD5449
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5429YRU
AD5429YRU-REEL
AD5429YRU-REEL7
AD5439YRU
AD5439YRU-REEL
AD5439YRU-REEL7
AD5449YRU
AD5449YRU-REEL
AD5449YRU-REEL7
EVAL-AD5429EB
EVAL-AD5439EB
EVAL-AD5449EB
Resolution
8
8
8
10
10
10
12
12
12
INL (LSBs)
±0.5
±0.5
±0.5
±0.5
±0.5
±0.5
±1
±1
±1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Rev. 0 | Page 29 of 32
Package Description
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
Evaluation Board
Evaluation Board
Evaluation Board
Package Option
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
RU-16
AD5429/AD5439/AD5449
NOTES
Rev. 0 | Page 30 of 32
AD5429/AD5439/AD5449
NOTES
Rev. 0 | Page 31 of 32
AD5429/AD5439/AD5449
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04464–0–7/04(0)
Rev. 0 | Page 32 of 32