Actel A54SX72A-PQ208A Sx-a automotive family fpgas Datasheet

v2.2
™
SX-A Automotive Family FPGAs
Specifications
•
12,000 to 108,000 Available System Gates
•
Up to 360 User-Programmable I/O Pins
•
Up to 2,012 Dedicated Flip-Flops
•
0.22µ CMOS Process Technology
Features
u e
•
Nonvolatile
•
Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
2.5V LVCMOS2
•
Configurable Weak-Resistor Pull-up or Pull-down for
Outputs at Power-up
•
Individual Output Slew Rate Control
•
Up to 100% Resource Utilization and 100% Pin
Locking
•
Deterministic, User-Controllable Timing
•
Unique In-System Diagnostic
Capability with Silicon Explorer II
•
250 MHz Internal Performance
•
Hot-Swap Compliant I/Os
•
Power-up/down Friendly (No Sequencing Required
for Supply Voltages)
•
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
•
66 MHz PCI Compliant
•
•
Single-Chip Solution
Actel’s Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and Design
Theft
and
Verification
SX-A Automotive-Grade Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Maximum User I/Os
Global Clocks
Quadrant Clocks
Boundary Scan Testing
3.3V PCI
Speed Grades
Temperature Grades*
Package (by pin count)
PQFP
TQFP
FBGA
A54SX08A
A54SX16A
A54SX32A
A54SX72A
8,000
12,000
768
512
16,000
24,000
1,452
924
32,000
48,000
2,880
1,800
72,000
108,000
6,036
4,024
256
512
130
3
0
Yes
Yes
Std
A
528
990
180
3
0
Yes
Yes
Std
A
1,080
1,980
249
3
0
Yes
Yes
Std
A
2,012
4,024
360
3
4
Yes
Yes
Std
A
208
100, 144
144
208
100, 144
144, 256
208
100, 144
144, 256
208
–
256, 484
Note: *The SX-A family is also offered in commercial, industrial and military temperature grades with -F, -1, -2 and -3 speed grades, in
addition to the Std speed grade. Refer to the SX-A Family FPGAs datasheet and HiRel SX-A Family FPGAs datasheet for more
details.
June 2006
© 2006 Actel Corporation
i
SX-A Automotive Family FPGAs
Ordering Information
A54SX16A
PQ
208
G
A
Application (Temperature Range)
A= Automotive (-40˚C to 125˚C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
FG = Fine Pitch Ball Grid Array (1.0mm pitch)
PQ = Plastic Quad Flat Pack
TQ = Thin Quad Flat Pack (1.4mm pitch)
Part Number
A54SX08A = 12,000 System Gates
A54SX16A = 24,000 System Gates
A54SX32A = 48,000 System Gates
A54SX72A = 108,000 System Gates
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded
based on characterization across the recommended operating conditions. A-grade parts are not tested at extended
temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel
Sales office to discuss testing options available.
Plastic Device Resources
User I/Os (including clock buffers)
PQFP 208-Pin
TQFP 100-Pin
TQFP 144-Pin
FBGA 144-Pin
FBGA 256-Pin
FBGA 484-Pin
A54SX08A
130
81
113
111
–
–
A54SX16A
175
81
113
111
180
–
A54SX32A
174
81
113
111
203
–
A54SX72A
171
–
–
–
203
360
Device
Note: Contact your Actel sales representative for product availability.
Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, FBGA = 1.0mm Fine Pitch Ball Grid Array
ii
v2.2
Table of Contents
General Description
SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Clock Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
PCI Compliance for the Automotive-Grade SX-A Family . . . . . . . . . . . . . . . . . 1-14
SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
Package Pin Assignments
208-Pin PQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
144-Pin TQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
144-Pin FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
256-Pin FBGA (Top View)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
484-Pin FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v2.2
iii
General Description
SX-A Family Architecture
Actel's SX-A family of FPGAs features a sea-of-modules
architecture. SX-A devices simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time-to-market for
performance-intensive
applications.
With
the
automotive temperature grade support (-40°C to 125°C),
the SX-A devices can address many in-cabin telematics
and automobile interconnect applications.
Programmable Interconnect Element
The SX-A family provides efficient use of silicon by
locating the routing interconnect resources between the
top two metal layers (Figure 1-1). This completely
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on
SRAM FPGAs and previous generations of antifuse
FPGAs), and enables the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
Actel’s SX-A architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient
mapping of synthesized logic functions. The routing and
interconnect resources are in the metal layers above the
logic modules, providing optimal use of silicon. This
enables the entire floor of the device to be spanned with
an uninterrupted grid of fine-grained, synthesis-friendly
logic modules (or “sea-of-modules”), which reduces the
distance signals have to travel between logic modules. To
minimize signal propagation delay, SX-A devices employ
both local and general routing resources. The high-speed
local routing resources (DirectConnect and FastConnect)
enable very fast local signal propagation that is optimal
for fast counters, state machines, and datapath logic.
The general system of segmented routing tracks allows
any logic module in the array to be connected to any
other logic or I/O module. Within this system,
propagation delay is minimized by limiting the number
of antifuse interconnect elements to five (90 percent of
connections typically use only three or fewer antifuses).
The unique local and general routing structure featured
in SX-A devices gives fast and predictable performance,
allows 100% pin-locking with full logic utilization,
enables concurrent PCB development, reduces design
time, and allows designers to achieve performance goals
with minimum effort.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are
normally open circuit and, when programmed, form a
permanent low-impedance connection.
The extremely small size of these interconnect elements
gives the automotive-grade SX-A devices abundant
routing resources and provides excellent protection
against design pirating. Reverse engineering is virtually
impossible because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses,
and since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and
metal tracks) have lower capacitance and lower
resistance than any other device of similar capacity,
leading to the fastest signal propagation in the industry.
Logic Module Design
The SX-A family architecture is described as a “sea-ofmodules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX-A family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
Further complementing SX-A’s flexible routing structure
is a hardwired, constantly loaded clock network that has
been tuned to provide fast clock propagation with
minimal clock skew. Additionally, the high performance
of the internal logic has eliminated the need to embed
latches or flip-flops in the I/O cells to achieve fast clockto-out or fast input set-up times. SX-A devices have easyto-use I/O cells that do not require HDL instantiation,
facilitating design re-use and reducing design and
verification time.
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure 1-2 on page 1-3).
The R-cell registers feature programmable clock polarity
selectable on a register-by-register basis. This provides
additional flexibility while allowing mapping of
synthesized functions into the SX-A FPGA. The clock
source for the R-cell can be chosen from either the
hardwired clock, the routed clocks, or internal logic.
v2.2
1-1
Routing Tracks
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Metal 4
Metal 3
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug Contact
Silicon Substrate
Note: A54SX72A has four layers of metal with the antifuse between Metal 3 and Metal 4. A54SX08A, A54SX16A, and A54SX32A have
three layers of metal with antifuse between Metal 2 and Metal 3.
Figure 1-1 • SX-A Family Interconnect Elements
The C-cell implements a range of combinatorial functions
of up to five inputs (Figure 1-3 on page 1-3). Inclusion of
the DB input and its associated inverter function allows
more than 4,000 combinatorial functions to be
implemented in a single module in the SX-A architecture.
The inverter function improves flexibility in the
architecture; for instance a 3-input exclusive-OR function
can be integrated into a single C-cell. At the same time,
the C-cell structure is extremely synthesis friendly,
simplifying the overall design and reducing synthesis
time.
Two C cells can be combined together to create a flipflop to imitate an R-cell via the user of the CC macro. This
is particularly useful when implementing paths which are
not timing-critical or if the designer needs more R-cells.
More information about CC macro can be found in
Actel's Maximizing Logic Utilization in eX, SX and SX-A
FPGA Devices Using CC Macros Application Note.
1 -2
v2.2
Chip Architecture
The SX-A family’s chip architecture provides a unique
approach to module organization and chip routing that
delivers the best register/logic mix for a wide variety of
new and emerging applications.
Module Organization
The C-cell and R-cell logic modules are arranged into
horizontal groups called Clusters. There are two types of
Clusters: Type 1 contains two C-cells and one R-cell, while
Type 2 contains one C-cell and two R-cells.
Clusters are further organized into SuperClusters for
even better design efficiency and device performance
(Figure 1-4 on page 1-4). SuperCluster 1 is a two-wide
grouping of Type 1 Clusters. SuperCluster 2 is a two-wide
group containing one Type 1 Cluster and one Type 2
Cluster. SX-A devices feature more SuperCluster 1
modules than SuperCluster 2 modules because designers
typically require significantly more combinatorial logic
than flip-flops.
S0
Routed
Data Input S1
PRE
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
Internal Logic
CLR
CKS
CKP
Figure 1-2 • R-Cell
D0
D1
Y
D2
D3
Sa
Sb
DB
A0
B0
A1
B1
Figure 1-3 • C-Cell
Routing Resources
DirectConnect is a horizontal routing resource that
provides connections from a C-cell to its neighboring Rcell in a given SuperCluster. DirectConnect uses a
hardwired signal path requiring no programmable
interconnection to achieve its fast signal propagation
time of less than 0.1 ns.
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 1-5 on page 1-4 and
Figure 1-6 on page 1-5). This routing architecture also
dramatically reduces the number of antifuses required to
complete a circuit, ensuring the highest possible
performance.
FastConnect enables horizontal routing between any
two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately
below it. Only one programmable connection is used in a
FastConnect path, delivering a maximum pin-to-pin
propagation time of 0.5 ns.
v2.2
1-3
R-Cell
Routed
S0 Data Input
C-Cell
D0
D1
S1
PRE
Y
D2
DirectConnect
Input
D
Q
D3
Y
Sb
Sa
HCLK
CLKA,
CLKB,
Internal Logic
CLR
DB
CKS
CKP
Cluster 1
A0
Cluster 1
Cluster 2
Type 1 SuperCluster
B0
A1
B1
Cluster 1
Type 2 SuperCluster
Figure 1-4 • Cluster Organization
DirectConnect
• No antifuses
• 0.1 ns maximum routing delay
FastConnect
• One antifuse
• 0.3 ns maximum routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 1 SuperClusters
Figure 1-5 • DirectConnect and FastConnect for Type 1 SuperClusters
1 -4
v2.2
DirectConnect
• No antifuses
• 0.1 ns maximum routing delay
FastConnect
• One antifuse
• 0.3 ns maximum routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Type 2 SuperClusters
Figure 1-6 • DirectConnect and FastConnect for Type 2 SuperClusters
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing
between SuperClusters. The exact combination of track
lengths and antifuses within each path is chosen by the
fully automatic place-and-route software to minimize
signal propagation delays.
Two additional clocks (CLKA, CLKB) are global clocks that
can be sourced from external pins or from internal logic
signals within the automotive-grade SX-A device. CLKA
and CLKB may be connected to sequential cells or to
combinational logic. If CLKA or CLKB pins are not used or
sourced from signals, then these pins must be set as LOW
or HIGH on the board. They must not be left floating
(except in the A54SX72A where these clocks can be
configured as regular I/Os and can float). Figure 1-8 on
page 1-6 describes the CLKA and CLKB circuit used in SXA devices with the exception of A54SX72A.
Clock Resources
In addition to CLKA and CLKB, the A54SX72A device
provides four quadrant clocks (QCLKA, QCLKB, QCLKC,
QCLKD – corresponding to bottom-left, bottom-right,
top-left, and top-right locations on the die, respectively),
which can be sourced from external pins or from internal
logic signals within the device. Each of these clocks can
individually drive up to a quarter of the chip, or they can
be grouped together to drive multiple quadrants. If
QCLKs are not used as quadrant clocks, they will behave
as regular I/Os. Bidirectional clock buffers are also
available on the A54SX72A. The CLKA, CLKB, and QCLK
circuits for A54SX72A are shown in Figure 1-9 on page 16. Note that bidirectional clock buffers are only available
in A54SX72A. For more information, refer to the “Pin
Description” on page 1-38.
Actel’s high-drive routing structure provides three clock
networks (Table 1-1). The first clock, called HCLK, is
hardwired from the HCLK buffer to the clock select MUX
in each R-cell. HCLK cannot be connected to
combinatorial logic. This provides a fast propagation
path for the clock signal, enabling the 5.6 ns clock-to-out
(pad-to-pad) performance of the auotmotive-grade SX-A
devices. The hardwired clock is tuned to provide clock
skew less than 0.3 ns worst case. If not used, this pin must
be set as LOW or HIGH on the board. It must not be left
floating. Figure 1-7 on page 1-6 describes the clock
circuit used for the constant load HCLK. When the device
is powered up and TRST is not grounded, HCLK does not
function until the fourth clock cycle. This prevents
possible false outputs due to a slow power-on-reset
signal and fast start-up clock circuit. To activate HCLK
from the first cycle, TRST pin must be reserved in the
Designer software and the pin must be tied to GND on
the board.
For more information on how to use quadrant clocks in
the A54SX72A device, refer to the Global Clock Networks
in Actel’s Antifuse Devices and Using A54SX72A and
RT54SX72S Quadrant Clocks application notes.
v2.2
1-5
Table 1-1 • SX-A Clock Resources
A54SX08A
A54SX16A
A54SX32A
A54SX72A
Routed Clocks (CLKA, CLKB)
2
2
2
2
Hardwired Clocks (HCLK)
1
1
1
1
Quadrant Clocks (QCLKA, QCLKB, QCLKC, QCLKD)
0
0
0
4
Constant Load
Clock Network
HCLKBUF
Figure 1-7 • SX-A HCLK Clock Pad
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
Figure 1-8 • SX-A Routed Clock Structure Except for A54SX72A
OE
From Internal Logic
To Internal Logic
Clock Network
From Internal Logic
CLKBUF
CLKBUFI
CLKINT
CLKINTI
CLKBIBUF
CLKBIBUFI
QCLKBUF
QCLKBUFI
QCLKINT
QCLKINTI
QCLKBIBUF
QCLKBIBUFI
Figure 1-9 • A54SX72A Routed Clock and QClock Structure
1 -6
v2.2
Other Architectural Features
I/O Modules
Each user I/O on an automotive-grade SX-A device can be
configured as an input, an output, a tristate output, or a
bidirectional pin. I/O pins can be set for 2.5 V or 3.3 V
operation through VCCI. SX-A I/Os, combined with array
registers, can achieve clock-to-output-pad timing of
5.6 ns even without the dedicated I/O registers. In most
FPGAs, I/O cells that have embedded latches and flipflops require instantiation in HDL code; this is a design
complication not encountered in SX-A FPGAs. Fast pinto-pin timing ensures that the device is able to interface
with any other device in the system, which in turn
enables parallel design of system components and
reduces overall design time. All unused I/Os are
configured as tristate outputs by Actel’s Designer
software, for maximum flexibility when designing new
boards or migrating existing designs.
Technology
The automotive-grade SX-A devices are implemented on
a high-voltage, twin-well CMOS process using 0.22 µ
design rules. The metal-to-metal antifuse is comprised of
a combination of amorphous silicon and dielectric
material with barrier metals and has a programmed
(“on” state) resistance of 25 Ω with capacitance of 1.0 fF
for low signal impedance.
Performance
The combination of architectural features described
above enables automotive-grade SX-A devices to
operate with internal clock frequencies of 250 MHz,
enabling fast execution of even complex logic functions
at extended tempetature ranges. Thus, the automotivegrade SX-A devices are an optimal platform upon which
to integrate the functionality previously contained in
multiple CPLDs. In addition, designs that previously
would have required a gate array to meet performance
goals can be integrated into an SX-A device with
dramatic improvements in cost and time-to-market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
SX-A inputs should be driven by high-speed push-pull
devices with a low-resistance pull-up device. If the input
voltage is greater than VCCI and a fast push-pull device is
NOT used, the high-resistance pull-up of the driver and
the internal circuitry of the SX-A I/O may create a voltage
divider. This voltage divider could pull the input voltage
below specification for some devices connected to the
driver. A logic '1' may not be correctly presented in this
case. For example, if an open drain driver is used with a
pull-up resistor to 3.3V to provide the logic '1' input, and
VCCI is set to 2.5 V on the SX-A device, the input signal
may be pulled down by the SX-A input.
User Security
Each I/O module has an available power-up resistor of
approximately 50 kΩ that can configure the I/O in a
known state during power-up. Just slightly before VCCA
reaches 2.5 V, the resistors are disabled, so the I/Os will
be controlled by user logic. See Table 1-2 on page 1-8
and Table 1-3 on page 1-8 for more information
concerning available I/O features.
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, special security fuses that
prevent internal probing and overwriting are hidden
throughout the fabric of the device. They are located
such that they cannot be accessed or bypassed without
destroying the rest of the device, making both invasive
and more-subtle noninvasive attacks ineffective against
Actel antifuse FPGAs.
Hot Swapping
During power-up/down (or partial up/down), all I/Os are
tristated. VCCA and VCCI do not have to be stable during
power-up/down. After the SX-A device is plugged into an
electrically active system, the device will not degrade the
reliability of or cause damage to the host system. The
device’s output pins are driven to a high impedance state
until normal chip operating conditions are reached.
Table 1-4 on page 1-8 summarizes the VCCA voltage at
which the I/Os behave according to the user’s design for
an SX-A device at room temperature for various ramp-up
rates. The data reported assumes a linear ramp-up
profile to 2.5V. For more information on power-up and
hot-swapping, refer to the application note, Actel SX-A
and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications.
Look for this symbol to ensure your valuable IP is secure.
™
u e
For more information, refer to Actel’s Implementation of
Security in Actel Antifuse FPGAs application note.
v2.2
1-7
Table 1-2 • I/O Features
Function
Description
Input Buffer Threshold Selections
•
3.3V PCI, LVTTL
•
2.5V LVCMOS2
•
3.3V PCI, LVTTL
•
2.5V LVCMOS2
Flexible Output Driver
Output Buffer
"Hot-Swap" Capability (except 3.3V PCI)
•
I/O on an unpowered device does not sink current
•
Can be used for “cold-sparing”
Selectable on an individual I/O basis
Individually selectable slew rate, high slew or low slew (The default is high slew rate).
The slew is only affected on the falling edge of an output. Rising edges of outputs are
not affected.
Power-Up
Individually selectable pull-ups and pull-downs during power-up (default is to power-up
in tristate)
Enables deterministic power-up of device
VCCA and VCCI can be powered in any order
Table 1-3 • I/O Characteristics for All I/O Configurations
Hot Swappable
Slew Rate Control
Power-Up Resistor
LVTTL, LVCMOS2
Yes
Yes. Only affects falling edges of outputs
Pull-up or pull-down
3.3V PCI
No
No. High slew rate only
Pull-up or pull-down
Table 1-4 • Power-up Time at which I/Os Become Active
Supply Ramp Rate
0.25V/µs
0.025V/µs
5V/ms
2.5V/ms
0.5V/ms
0.25V/ms
0.1V/ms
0.025V/ms
Units
µs
µs
ms
ms
ms
ms
ms
ms
A54SX08A
10
96
0.34
0.65
2.7
5.4
12.9
50.8
A54SX16A
10
100
0.36
0.62
2.5
4.7
11.0
41.6
A54SX32A
10
100
0.46
0.74
2.8
5.2
12.1
47.2
A54SX72A
10
100
0.41
0.67
2.6
5.0
12.1
47.2
Boundary-Scan Testing (BST)
Automotive-grade SX-A devices are IEEE 1149.1
compliant and offer superior diagnostic and testing
capabilities by providing Boundary Scan Testing (BST)
and probing capabilities. The BST function is controlled
through the special JTAG pins (TMS, TDI, TCK, TDO, and
TRST). The functionality of the JTAG pins is defined by
two available modes: Dedicated and Flexible. TMS
cannot be employed as user I/O in either mode.
Dedicated Mode
In Dedicated mode, all JTAG pins are reserved for BST;
designers cannot use them as regular I/Os. An internal
pull-up resistor is automatically enabled on both TMS
and TDI pins, and the TMS pin will function as defined in
the IEEE 1149.1 (JTAG) specification.
1 -8
v2.2
To select Dedicated mode, users need to reserve the JTAG
pins in Actel’s Designer software. To reserve the JTAG
pins, users can check the "Reserve JTAG" box in "Device
Selection Wizard" (Figure 1-10 on page 1-9).
To select Dedicated mode, users need to reserve the JTAG
pins in Actel's Designer software by checking the
"Reserve JTAG" box in "Device Selection Wizard"
(Figure 1-10 on page 1-9). JTAG pins comply with LVTTL/
TTL I/O specification regardless of whether they are used
as a user I/O or a JTAG I/O. Refer to the “3.3V LVTTL
Electrical Specifications” on page 1-13 and “2.5V
LVCMOS2 Electrical Specifications” on page 1-14 for
detailed specifications.
Upon power-up, the TAP controller enters the Test-LogicReset state. In this state, TDI, TCK and TDO function as
user I/Os. The TDI, TCK, and TDO are transformed from
user I/Os into BST pins when a rising edge on TCK is
detected while TMS is at logic low. To return to TestLogic Reset state, TMS must be high for at least five TCK
cycles. An external 10KΩ pull-up resistor to VCCI should
be placed on the TMS pin to pull it HIGH by default.
Table 1-5
describes
the
different
configuration
requirements of BST pins and their functionality in
different modes.
TRST Pin
Figure 1-10 • Device Selection Wizard
The TRST pin functions as a dedicated Boundary-Scan
Reset pin when the "Reserve JTAG Test Reset" option is
selected as shown in Figure 1-10 on page 1-9. An internal
pull-up resistor is permanently enabled on the TRST pin
in this mode. Actel recommends connecting this pin to
ground in normal operation to keep the JTAG state
controller in the Test-Logic-Reset state. When JTAG is
being used, it can be left floating or be driven high.
Flexible Mode
In Flexible mode, TDI, TCK, and TDO may be employed as
either user I/Os or as JTAG input pins. The internal
resistors on the TMS and TDI pins are not present in
flexible JTAG mode.
To select the Flexible mode, users need to uncheck the
"Reserve JTAG" box in "Device Selection Wizard" in
Actel’s Designer software. In Flexible mode, TDI, TCK and
TDO pins may function as user I/Os or BST pins. The
functionality is controlled by the BST TAP controller. The
TAP controller receives two control inputs, TMS and TCK.
When the "Reserve JTAG Test Reset" option is not
selected, this pin will function as a regular I/O. If unused
as an I/O in the design, it will be configured as a tristated
output.
Table 1-5 • Boundary-Scan Pin Configurations and Functions
Mode
Designer "Reserve JTAG" Selection
TAP Controller State
Dedicated (JTAG)
Checked
Any
Flexible (User I/O)
Unchecked
Test-Logic-Reset
Flexible (JTAG)
Unchecked
Any EXCEPT Test-Logic-Reset
Probing Capabilities
Automotive-grade SX-A devices also provide an internal
probing capability that is accessed with the JTAG pins.
The Silicon Explorer II Diagnostic Hardware is used to
control the TDI, TCK, TMS and TDO pins to select the
desired nets for debugging. The user assigns the selected
internal nets in Actel's Silicon Explorer II software to the
PRA/PRB output pins for observation. Silicon Explorer II
automatically places the device into JTAG mode.
However, probing functionality is only activated when
the TRST pin is driven high or left floating, allowing the
internal pull-up resistor to pull TRST to HIGH. If the TRST
pin is held LOW, the TAP controller remains in the TestLogic-Reset state so no probing can be performed.
However, the user must drive the TRST pin HIGH or allow
the internal pull-up resistor to pull TRST HIGH.
When selecting the "Reserve Probe Pin" box as shown in
Figure 1-10 on page 1-9, direct the layout tool to reserve
the PRA and PRB pins as dedicated outputs for probing.
This "reserve" option is merely a guideline. If the
designer assigns user I/Os to the PRA and PRB pins and
selects the "Reserve Probe Pin" option, Designer Layout
will override the "Reserve Probe Pin" option and place
the user I/Os on those pins.
To allow probing capabilities, the security fuse must not
be programmed. Programming the security fuse disables
the probe circuitry. Table 1-6 on page 1-10 summarizes
the possible device configurations for probing once the
device leaves the "Test-Logic-Reset" JTAG state.
v2.2
1-9
Table 1-6 • Device Configuration Options for Probe Capability (TRST pin reserved)
JTAG Mode
Dedicated
TRST1
Security Fuse
Programmed
PRA, PRB2
TDI, TCK, TDO2
LOW
No
User I/O3
Probing Unavailable
I/O3
LOW
No
Dedicated
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
Flexible
HIGH
No
Probe Circuit Outputs
Probe Circuit Inputs
–
Yes
Probe Circuit Secured
Probe Circuit Secured
–
User
User I/O3
Flexible
Note:
1. If the TRST pin is not reserved, the device behaves according to TRST=HIGH as described in the table.
2. Avoid using the TDI, TCK, TDO, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
3. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. Unused pins are automatically tristated by
the Designer software.
SX-A Probe Circuit Control Pins
Automotive-grade SX-A devices contain internal probing
circuitry that provides built-in access to every node in a
design, enabling 100% real-time observation and analysis
of a device's internal logic nodes without design iteration.
The probe circuitry is accessed by Silicon Explorer II, an
easy-to-use integrated verification and logic analysis tool
that can sample data at 100 MHz (asynchronous) or 66
MHz (synchronous). Silicon Explorer II attaches to a PC's
standard COM port, turning the PC into a fully functional
18 channel logic analyzer. Silicon Explorer II allows
designers to complete the design verification process at
their desks and reduces verification time from several
hours per cycle to a few seconds.
The Silicon Explorer II tool uses the boundary-scan ports
(TDI, TCK, TMS, and TDO) to select the desired nets for
verification. The selected internal nets are assigned to
the PRA/PRB pins for observation. Figure 1-11 illustrates
the interconnection between Silicon Explorer II and the
FPGA to perform in-circuit verification
16 Pin
Connection
SX-A FPGAs
TDI
TCK
Serial
Connection
Silicon Explorer II
TMS
TDO
PRA
PRB
22 Pin
Connection
Additional 16 Channels
(Logic Analyzer)
Figure 1-11 • Probe Setup
1 -1 0
v2.2
Design Considerations
Programming
Avoid using the TDI, TCK, TDO, PRA, and PRB pins as
input or bidirectional ports. Since these pins are active
during probing, critical input signals through these pins
are not available. In addition, do not program the
Security Fuse. Programming the Security Fuse disables
the Probe Circuit. Actel recommends that you use a 70Ω
series termination resistor on every probe connector
(TDI, TCK, TMS, TDO, PRA, PRB). The 70Ω series
termination, effective for traces of fewer than 8 inches, is
used to prevent data transmission corruption during
probing and reading back the checksum.
Device programming is supported through Silicon
Sculptor series of programmers. In particular, Silicon
Sculptor is compact, robust, single-site and multi-site
device programmer for the PC.
Development Tool Support
The procedure for programming an SX-A Automotive
device using Silicon Sculptor is as follows:
With standalone software, Silicon Sculptor
allows
concurrent programming of multiple units from the
same PC, ensuring the fastest programming times
possible. Each fuse is subsequently verified by Silicon
Sculptor II to insure correct programming. In addition,
integrity tests ensure that no extra fuses are
programmed. Silicon Sculptor also provides extensive
hardware self-testing capability.
The SX-A Automotive family of FPGAs is fully supported
by both Actel's Libero® Integrated Design Environment
and Designer FPGA Development software. Actel Libero
IDE is a design management environment that
streamlines the design flow. Libero IDE provides an
integrated design manager that seamlessly integrates
design tools while guiding the user through the design
flow, managing all design and log files, and passing
necessary design data among tools. Additionally, Libero
IDE allows users to integrate both schematic and HDL
synthesis into a single flow and verify the entire design
in a single environment. Libero IDE includes Synplify®
for Actel from Synplicity®, ViewDraw® for Actel from
Mentor Graphics®, ModelSim™ HDL Simulator from
Mentor
Graphics,
WaveFormer
Lite™
from
SynaptiCAD™, and Designer software from Actel. Refer
to the Libero IDE flow (located on Actel’s website)
diagram for more information.
1. Load the .AFM file
2. Select the device to be programmed
3. Begin programming
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via in-house
programming from the factory.
For detailed information on programming, read the
following documents Programming Antifuse Devices and
Silicon Sculptor User’s Guide.
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven place-and-route, and a world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can lock his/her
design pins before layout while minimally impacting the
results of place-and-route. Additionally, the backannotation flow is compatible with all the major
simulators and the simulation results can be cross-probed
with Silicon Explorer II, Actel’s integrated verification
and logic analysis tool. Another tool included in the
Designer software is the SmartGen core generator, which
easily creates popular and commonly used logic
functions for implementation into your schematic or HDL
design. Actel's Designer software is compatible with the
most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synplicity,
Synopsys, and Cadence Design Systems. The Designer
software is available for both the Windows and UNIX
operating systems.
v2.2
1-11
Related Documents
Application Notes
Global Clock Networks in Actel’s Antifuse Devices
http://www.actel.com/documents/GlobalClk_AN.pdf
Using A54SX72A and RT54SX72S Quadrant Clocks
http://www.actel.com/documents/QCLK_AN.pdf
Implementation of Security in Actel Antifuse FPGAs
http://www.actel.com/documents/
Antifuse_Security_AN.pdf
Actel eX, SX-A, and RTSX-S I/Os
http://www.actel.com/documents/AntifuseIO_AN.pdf
Actel SX-A and RT54SX-S Devices in Hot-Swap and ColdSparing Applications
http://www.actel.com/documents/
HotSwapColdSparing_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/
AntifuseProgram_AN.pdf
Datasheets
SX-A Family FPGAs
http://www.actel.com/documents/SXA_DS.pdf
HiRel SX-A Family FPGAs
http://www.actel.com/documents/HRSXA_DS.pdf
User’s Guides
Silicon Sculptor User’s Guide
http://www.actel.com/documents/SiliSculptII_WIN_ug.pdf
1 -1 2
v2.2
Operating Conditions
Table 1-7 • Absolute Maximum Ratings1
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.3 to +4.0
V
VCCA
DC Supply Voltage for Array
–0.3 to +3.0
V
VI
Input Voltage
–0.5 to VCCI +0.5
V
VO
Output Voltage
–0.5 to +VCCI
V
TSTG
Storage Temperature
–65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
2. SX-A Automotive devices are not 5 V tolerant.
Table 1-8 • Recommended Operating Conditions
Automotive1
Units
–40 to +125
°C
2.5V Power Supply Range
2.375 to 2.625
V
3.3V Power Supply Range
3.135 to 3.465
V
Parameter
Temperature
Range2
Notes:
1. Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based on
characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If testing to
ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to discuss testing
options available.
2. Ambient temperature (TA).
3.3V LVTTL Electrical Specifications
Automotive
Symbol
Parameter
Min
Units
Max
VOH
VCCI = MIN,
VI = VIH or VIL
IOH = –2mA
2.4
V
VOL
VCCI = MIN,
VI = VIH or VIL
IOL = 2mA
VIL
Input Low Voltage
VIH
Input High Voltage
2.1
IIL / IIH
Input Leakage Current, VIN = VCCI or GND
–20
20
µA
–20
0.4
V
0.7
V
V
IOZ
3-State Output Leakage Current
20
µA
tR, tF1,2
Input Transition Time tR, tF
10
ns
CIO
I/O Capacitance
10
pF
ICC3
Standby Current
45
mA
IV Curve
Can be derived from the IBIS model at http://www.actel.com/techdocs/models/ibis.html.
Note:
1.
2.
3.
tR is the transition time from 0.7V to 2.1V.
tF is he transition time from 2.1V to 0.7V.
ICC = ICCI + ICCA
v2.2
1-13
2.5V LVCMOS2 Electrical Specifications
Automotive
Symbol
Parameter
Min.
Max.
VOH
VCCI = MIN,
VI = VIH or VIL
IOH = -1mA
VOL
VCCI = MIN,
VI = VIH or VIL
IOL = 1mA
VIL
Input Low Voltage, VOUT =< VVOL (max)
VIH
Input High Voltage, VOUT >= VVOH (min)
1.7
IIL / IIH
Input Leakage Current, VIN = VCCI or GND
–20
20
µA
IOZ
3-State Output Leakage Current
–20
20
µA
Input Transition Time tR, tF
10
ns
CIO
I/O Capacitance
10
pF
ICC3
Standby Current
35
mA
IV Curve
Can be derived from the IBIS model at http://www.actel.com/techdocs/models/ibis.html.
tR, tF
1,2
1.8
Units
V
0.5
V
0.6
V
V
Note:
1.
2.
3.
tR is the transition time from 0.6V to 1.7V.
tF is he transition time from 1.7V to 0.6V.
ICC = ICCI + ICCA
PCI Compliance for the Automotive-Grade SX-A Family
The automotive-grade SX-A devices support 3.3V PCI and are compliant with the PCI Local Bus Specification Rev. 2.1.
Table 1-9 • DC Specifications (3.3V PCI Operation)
Symbol
Parameter
VCCA
Condition
Min.
Max.
Units
Supply Voltage for Array
2.375
2.625
V
VCCI
Supply Voltage for I/Os
3.135
3.465
V
VIH
Input High Voltage
0.5VCCI
VCCI + 0.5
V
VIL
Input Low Voltage
–0.5
0.3VCCI
V
IIPU
Input Pull-up Voltage1
0.7VCCI
2
IIL
Input Leakage Current
0 < VIN < VCCI
–20
VOH
Output High Voltage
IOUT = –500 µA
0.9VCCI
VOL
Output Low Voltage
IOUT = 1500 µA
CIN
Input Pin Capacitance3
CCLK
CLK Pin Capacitance
5
V
+20
µA
V
0.1VCCI
V
10
pF
12
pF
Note:
1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a
floated network. Designers should ensure that the input buffer is conducting minimum current at this input voltage in applications
sensitive to static power utilization.
2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs.
3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK).
1 -1 4
v2.2
Table 1-10 • AC Specifications (3.3V PCI Operation)
Symbol
IOH(AC)
Parameter
Condition
Min.
Switching Current High
0 < VOUT ≤ 0.3VCCI
1
0.3VCCI ≤ VOUT < 0.9VCCI 1
0.7VCCI < VOUT < VCCI
IOL(AC)
(Test Point)
VOUT = 0.7VCC 2
Switching Current Low
VCCI > VOUT ≥ 0.6VCCI
Max.
–12VCCI
mA
(–17.1(VCCI – VOUT))
mA
1, 2
EQ 1-1 on
page 1-17
–32VCCI
1
0.6VCCI > VOUT > 0.1VCCI
1
VOUT = 0.18VCC 2
ICL
Low Clamp Current
–3 < VIN ≤ –1
ICH
High Clamp Current
VCCI + 4 > VIN ≥ VCCI + 1
mA
16VCCI
mA
(26.7VOUT)
mA
0.18VCCI > VOUT > 0 1, 2
(Test Point)
Units
EQ 1-2 on
page 1-17
38VCCI
mA
–25 + (VIN + 1)/0.015
mA
25 + (VIN – VCCI – 1)/0.015
mA
3
1
4
V/ns
1
4
V/ns
slewR
Output Rise Slew Rate
0.2VCCI - 0.6VCCI load
slewF
Output Fall Slew Rate
0.6VCCI - 0.2VCCI load 3
Note:
1. Refer to the V/I curves in Figure 1-12 on page 1-16. Switching current characteristics for REQ# and GNT# are permitted to be one
half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and
RST#, which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and
INTD#, which are open drain outputs.
2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C
and D) are provided with the respective diagrams in Figure 1-12 on page 1-16. The equation defined maximum should be met by
design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any
point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter
with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and
minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain
outputs.
pin
1/2 in. max.
output
buffer
10 pF
1k/25Ω
pin
output
buffer
1k/25Ω
10 pF
v2.2
1-15
Figure 1-12 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the automotivegrade SX-A devices.
150.0
IOL MAX Spec
IOL
Current (mA)
100.0
50.0
IOL MIN Spec
0.0
0
–50.0
0.5
1
1.5
2
3
IOH MIN Spec
–100.0
IOH MAX Spec
IOH
–150.0
Voltage Out (V)
Figure 1-12 • 3.3V PCI V/I Curve for Automotive-Grade SX-A Devices
Equation C
IOH = (98.0/VCCI ) ∗ (VOUT – VCCI ) ∗ (VOUT + 0.4VCCI )
for 0.7 VCCI < VOUT < VCCI
Equation D
IOL = (256/VCCI ) ∗ VOUT ∗ (VCCI – VOUT )
for 0V < VOUT < 0.18 VCCI
1 -1 6
2.5
v2.2
3.5
4
Junction Temperature (TJ)
Where:
Ta = Ambient Temperature
The temperature variable in the Designer Series software
refers to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature.
Equation 1, shown below, can be used to calculate
junction temperature.
∆T = Temperature gradient between junction (silicon)
and ambient
∆T = θja * P
EQ 1-2
P = Power
θja = Junction to ambient of package. θja numbers are
Junction Temperature = ∆T + Ta +
located in the Package Thermal Characteristics table
below.
EQ 1-1
Package Thermal Characteristics
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates.
The maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 144-pin package at
automotive temperature and still air is as follows:
Max. junction temp. (°C) – Max. ambient temp. (°C)
150°C – 125°C
Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------------- = 0.78W
θ ja (°C/W)
32°C/W
Table 1-11 • Package Thermal Characteristics
Pin Count
θjc
θja
Still Air
θja
300 ft/min
Units
100
12
37.5
30
°C/W
144
11
32
24
°C/W
208
8
30
23
°C/W
Plastic Quad Flat Pack (PQFP) with Heat Spreader
208
3.8
20
17
°C/W
Fine Pitch Ball Grid Array (FBGA)
144
3.8
38.8
26.7
°C/W
Fine Pitch Ball Grid Array (FBGA)
256
3.3
30
25
°C/W
Fine Pitch Ball Grid Array (FBGA)
484
3
20
15
°C/W
Package Type
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
1
Plastic Quad Flat Pack (PQFP)
2
Note:
1. The A54SX08A PQ208 has no heat spreader.
2. The SX-A PQ208 package has a heat spreader for A54SX16A, A54SX32A, and A54SX72A.
For Power Estimator information, please go to http://www.actel.com/products/tools/index.html.
v2.2
1-17
SX-A Timing Model*
Input Delays
I/O Module
tINYH = 1.0 ns
Internal Delays
tIRD1 = 0.5 ns
tIRD2 = 0.7 ns
Combinatorial
Cell
tPD = 1.5 ns
Predicted
Routing
Delays
I/O Module
tRD1 = 0.6 ns
tRD4 = 1.1 ns
tRD8 = 2.0 ns
Routed
Clock
tRCKH = 2.2 ns
Q
tRD1 = 0.6 ns
tENZL = 2.8 ns
tRCO = 1.0 ns
(100% Load)
I/O Module
tDHL = 3.8 ns
Register
Cell
I/O Module
tINYH = 1.0 ns
tSUD = 1.2 ns
tHD = 0.0 ns
Hard-Wired
Clock
D
tHCKH = 1.8 ns
tDHL = 3.8 ns
I/O Module
tDHL = 3.8 ns
Register
Cell
tSUD = 1.2 ns
tHD = 0.0 ns
Output Delays
D
Q
tRD1 = 0.6 ns
tENZL = 2.8 ns
tRCO = 1.0 ns
Note: *Values shown for A54SX08A, worst-case automotive conditions at 3.3V PCI with standard place-and-route.
Figure 1-13 • Timing Model
Sample Path Calculations
Hardwired Clock
External Setup =(tINYH + tIRD2 + tSUD) – tHCKH
=1.0+0.7+1.2-1.8=1.1ns
Clock-to-Out (Pad-to-Pad)
=tHCKH + tRCO + tRD1 + tDHL
=1.8+1.0+0.6+3.8=7.2ns
1 -1 8
Routed Clock
External Setup = (tINYH + tIRD2 + tSUD) – tRCKH
= 1.0+0.7+1.2-1.8=1.1ns
Clock-to-Out (Pad-to-Pad)
= tRCKH + tRCO + tRD1 + tDHL
= 1.8+1.0+0.6+3.8=7.2ns
v2.2
Output Buffer Delays
E
D
VCC
In
To AC test loads (shown below)
VCC
GND
50% 50%
VOH
Out
VOL
PAD
TRIBUFF
En
1.5V
1.5V
Out
VCC
GND
50% 50%
VCC
1.5V
E
Out
GND
10%
VOL
tDLH
tDHL
t ENZL
GND
50% 50%
VOH
tENZH
tENLZ
90%
1.5V
tENHZ
Figure 1-14 • Output Buffer Delay
Load 2
(Used to measure enable delays)
Load 1
(Used to measure
propagation delay)
VCC
To the output
under test
35 pF
To the output
under test
Load 3
(Used to measure disable delays)
VCC
GND
R to VCC for t PZL
R to GND for t PZH
R = 1 kΩ
GND
R to VCC for t PLZ
R to GND for t PHZ
R = 1 kΩ
To the output
under test
35 pF
5 pF
Figure 1-15 • AC Test Loads
PAD
INBUF
S
A
B
Y
Y
VCC
S, A or B
In
Out
GND
3V
1.5V 1.5V
VCC
50%
Out
GND
0V
50%
Out
50%
50%
tPD
50%
t PD
Figure 1-16 • Input Buffer Delays
GND
50% 50%
VCC
t PD
GND
tPD
VCC
50%
Figure 1-17 • C-Cell Delays
v2.2
1-19
Cell Timing Characteristics
D
CLK
PRESET
Q
CLR
(Positive Edge-Triggered)
t HD
D
t SUD
CLK
tHP
t HPWH
t RPWH
t RCO
t
t HPWL
RPWL
Q
t CLR
t PRESET
CLR
t WASYN
PRESET
Figure 1-18 • Cell Timing Characteristics
Timing Characteristics
Long Tracks
Timing characteristics for SX-A devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all SX-A family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined
until after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer utility or performing simulation with postlayout delays.
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three to five
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6 percent of
nets in a fully utilized device require long tracks. Long
tracks contribute approximately 4 ns to 8.4 ns delay. This
additional delay is represented statistically in higher
fanout routing delays.
Critical Nets and Typical Nets
Timing Derating
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net
property assignment prior to placement and routing. Up
to 6 percent of the nets in a design may be designated as
critical, while 90 percent of the nets in a design are
typical.
SX-A devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature, and worst-case processing.
1 -2 0
v2.2
Table 1-12 • Temperature and Voltage Derating Factors
(Normalized to TJ = 125°C, VCCA = 2.3 V)
Junction Temperature (TJ)
VCCA
–55° C
–40° C
0° C
25° C
70° C
85° C
125° C
2.3 V
0.7
0.70
0.77
0.78
0.88
0.91
1.00
2.5 V
0.65
0.66
0.72
0.73
0.83
0.85
0.93
2.7 V
0.66
0.62
0.67
0.69
0.78
0.80
0.88
Table 1-13 • A54SX08A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
1.5
ns
0.1
ns
1
C-Cell Propagation Delays
tPD
Internal Array Module
Predicted Routing Delays
2
tDC
FO=1 Routing Delay, Direct Connect
tFC
FO=1 Routing Delay, Fast Connect
0.5
ns
tRD1
FO=1 Routing Delay
0.6
ns
tRD2
FO=2 Routing Delay
0.7
ns
tRD3
FO=3 Routing Delay
0.9
ns
tRD4
FO=4 Routing Delay
1.1
ns
tRD8
FO=8 Routing Delay
2.0
ns
tRD12
FO=12 Routing Delay
2.9
ns
R-Cell Timing
tRCO
Sequential Clock-to-Q
1.0
ns
tCLR
Asynchronous Clear-to-Q
1.2
ns
tPRESET
Asynchronous Preset-to-Q
1.2
ns
tSUD
Flip-Flop Data Input Set-Up
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
2.3
ns
tRECASYN
Asynchronous Recovery Time
0.6
ns
tHASYN
Asynchronous Hold Time
0.5
ns
1.2
ns
Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
1.0
ns
tINYL
Input Data Pad-to-Y LOW
1.6
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-21
Table 1-13 • A54SX08A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
Input Module Predicted Routing Delays
Min.
Max.
Units
2
tIRD1
FO=1 Routing Delay
0.5
ns
tIRD2
FO=2 Routing Delay
0.7
ns
tIRD3
FO=3 Routing Delay
0.9
ns
tIRD4
FO=4 Routing Delay
1.1
ns
tIRD8
FO=8 Routing Delay
2.0
ns
tIRD12
FO=12 Routing Delay
2.9
ns
Dedicated (Hardwired) Array Clock Networks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
2.1
Input HIGH to LOW
(Pad to R-Cell Input)
1.8
ns
ns
tHPWH
Minimum Pulse Width HIGH
2.4
ns
tHPWL
Minimum Pulse Width LOW
2.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.3
4.8
ns
ns
208
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
1.8
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
2.2
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
2.2
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
2.5
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
2.3
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
2.6
ns
ns
ns
ns
ns
ns
tRPWH
Min. Pulse Width HIGH
2.4
ns
tRPWL
Min. Pulse Width LOW
2.4
ns
tRCKSW
Maximum Skew (Light Load)
0.3
ns
tRCKSW
Maximum Skew (50% Load)
0.5
ns
tRCKSW
Maximum Skew (100% Load)
0.5
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -2 2
v2.2
Table 1-13 • A54SX08A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
1.8
ns
1.7
ns
tHPWH
Minimum Pulse Width HIGH
2.4
tHPWL
Minimum Pulse Width LOW
2.4
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
ns
ns
0.3
4.8
ns
ns
208
MHz
Routed Array Clock Networks
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
1.8
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
2.3
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
2.1
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
2.5
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
2.2
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
2.6
tRPWH
Min. Pulse Width HIGH
2.4
ns
tRPWL
Min. Pulse Width LOW
2.4
ns
tRCKSW
Maximum Skew (Light Load)
0.5
ns
tRCKSW
Maximum Skew (50% Load)
0.5
ns
tRCKSW
Maximum Skew (100% Load)
0.5
ns
ns
tRCKH
2.5 V LVTTL Output Module Timing
ns
ns
ns
ns
ns
ns
3
tDLH
Data-to-Pad LOW to HIGH
5.0
tDHL
Data-to-Pad HIGH to LOW
21.8
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
4.6
ns
tENZL
Enable-to-Pad, Z to L
22.8
ns
tENZLS
Data-to-Pad, Z to L—low slew
6.7
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-23
Table 1-13 • A54SX08A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
tENZH
Min.
Max.
Units
Enable-to-Pad, Z to H
4.1
ns
tENLZ
Enable-to-Pad, L to Z
6.7
ns
tENHZ
Enable-to-Pad, H to Z
0.064
ns
dTLH
Delta LOW to HIGH
0.029
ns/pF
dTHL
Delta HIGH to LOW
0.108
ns/pF
dTHLS
Delta HIGH to LOW—low slew
5.0
ns/pF
4
3.3 V PCI Output Module Timing
tDLH
Data-to-Pad LOW to HIGH
3.8
ns
tDHL
Data-to-Pad HIGH to LOW
3.8
ns
tENZL
Enable-to-Pad, Z to L
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.8
ns
tENLZ
Enable-to-Pad, L to Z
4.8
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
3.3 V LVTTL Output Module Timing3
tDLH
Data-to-Pad LOW to HIGH
5.3
ns
tDHL
Data-to-Pad HIGH to LOW
4.8
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
17.3
ns
tENZL
Enable-to-Pad, Z to L
4.3
ns
tENZLS
Enable-to-Pad, Z to L—low slew
31.9
ns
tENZH
Enable-to-Pad, Z to H
5.5
ns
tENLZ
Enable-to-Pad, L to Z
5.5
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
dTHLS
Delta HIGH to LOW—low slew
0.092
ns/pF
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -2 4
v2.2
Table 1-14 • A54SX16A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C)
‘Std’ Speed
Parameter
Description
C-Cell Propagation
tPD
Predicted Routing
Min
Max.
Units
Delays1
Internal Array Module
1.5
ns
Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
0.5
ns
tRD1
FO=1 Routing Delay
0.6
ns
tRD2
FO=2 Routing Delay
0.7
ns
tRD3
FO=3 Routing Delay
0.9
ns
tRD4
FO=4 Routing Delay
1.1
ns
tRD8
FO=8 Routing Delay
2.0
ns
tRD12
FO=12 Routing Delay
2.9
ns
tRCO
Sequential Clock-to-Q
1.0
ns
tCLR
Asynchronous Clear-to-Q
1.2
ns
tPRESET
Asynchronous Preset-to-Q
1.2
ns
tSUD
Flip-Flop Data Input Set-Up
1.2
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
2.3
ns
tRECASYN
Asynchronous Recovery Time
0.6
ns
tHASYN
Asynchronous Removal Time
0.5
ns
R-Cell Timing
Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
1.0
ns
tINYL
Input Data Pad-to-Y LOW
1.6
ns
Input Module Predicted Routing
Delays2
tIRD1
FO=1 Routing Delay
0.5
ns
tIRD2
FO=2 Routing Delay
0.7
ns
tIRD3
FO=3 Routing Delay
0.9
ns
tIRD4
FO=4 Routing Delay
1.1
ns
tIRD8
FO=8 Routing Delay
0.9
ns
tIRD12
FO=12 Routing Delay
2.9
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-25
Table 1-14 • A54SX16A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
Min
Max.
Units
Dedicated (Hardwired) Array Clock Networks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
2.2
Input HIGH to LOW
(Pad to R-Cell Input)
2.1
ns
ns
tHPWH
Minimum Pulse Width HIGH
2.4
ns
tHPWL
Minimum Pulse Width LOW
2.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.1
4.8
ns
ns
208
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
2.1
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
2.2
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
2.6
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
2.4
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
2.6
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
3.1
ns
ns
ns
ns
ns
ns
tRPWH
Min. Pulse Width HIGH
2.4
ns
tRPWL
Min. Pulse Width LOW
2.4
ns
tRCKSW
Maximum Skew (Light Load)
0.5
ns
tRCKSW
Maximum Skew (50% Load)
0.9
ns
tRCKSW
Maximum Skew (100% Load)
0.9
ns
Dedicated (Hardwired) Array Clock Networks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
2.2
Input HIGH to LOW
(Pad to R-Cell Input)
2.1
ns
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -2 6
v2.2
Table 1-14 • A54SX16A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
Min
Max.
tHPWH
Minimum Pulse Width HIGH
2.4
ns
tHPWL
Minimum Pulse Width LOW
2.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.1
4.8
Units
ns
ns
208
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
2.1
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
2.3
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
2.6
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
2.7
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
3.0
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
3.1
ns
ns
ns
ns
ns
ns
tRPWH
Min. Pulse Width HIGH
2.4
ns
tRPWL
Min. Pulse Width LOW
2.4
ns
tRCKSW
Maximum Skew (Light Load)
0.5
ns
tRCKSW
Maximum Skew (50% Load)
0.9
ns
tRCKSW
Maximum Skew (100% Load)
0.9
ns
2.5 V LVTTL Output Module
Timing3
tDLH
Data-to-Pad LOW to HIGH
6.3
ns
tDHL
Data-to-Pad HIGH to LOW
5.0
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
21.8
ns
tENZL
Enable-to-Pad, Z to L
4.6
ns
tENZLS
Data-to-Pad, Z to L—low slew
22.8
ns
tENZH
Enable-to-Pad, Z to H
6.7
ns
tENLZ
Enable-to-Pad, L to Z
4.1
ns
tENHZ
Enable-to-Pad, H to Z
6.7
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-27
Table 1-14 • A54SX16A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V , TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
dTLH
Min
Max.
Units
Delta LOW to HIGH
0.064
ns/pF
dTHL
Delta HIGH to LOW
0.029
ns/pF
dTHLS
Delta HIGH to LOW—low slew
0.108
ns/pF
4
3.3 V PCI Output Module Timing
tDLH
Data-to-Pad LOW to HIGH
3.8
ns
tDHL
Data-to-Pad HIGH to LOW
3.8
ns
tENZL
Enable-to-Pad, Z to L
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.8
ns
tENLZ
Enable-to-Pad, L to Z
4.8
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
3.3 V LVTTL Output Module Timing
3
tDLH
Data-to-Pad LOW to HIGH
5.3
ns
tDHL
Data-to-Pad HIGH to LOW
4.8
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
17.3
ns
tENZL
Enable-to-Pad, Z to L
4.3
ns
tENZLS
Enable-to-Pad, Z to L—low slew
31.9
ns
tENZH
Enable-to-Pad, Z to H
5.5
ns
tENLZ
Enable-to-Pad, L to Z
5.5
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
dTHLS
Delta HIGH to LOW—low slew
0.092
ns/pF
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -2 8
v2.2
Table 1-15 • A54SX32A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C
‘Std’ Speed
Parameter
Description
C-Cell Propagation
tPD
Predicted Routing
Min.
Max.
Units
1.5
ns
Delays1
Internal Array Module
Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
0.5
ns
tRD1
FO=1 Routing Delay
0.6
ns
tRD2
FO=2 Routing Delay
0.7
ns
tRD3
FO=3 Routing Delay
0.9
ns
tRD4
FO=4 Routing Delay
1.1
ns
tRD8
FO=8 Routing Delay
2.0
ns
tRD12
FO=12 Routing Delay
2.9
ns
tRCO
Sequential Clock-to-Q
1.0
ns
tCLR
Asynchronous Clear-to-Q
1.2
ns
tPRESET
Asynchronous Preset-to-Q
1.2
ns
tSUD
Flip-Flop Data Input Set-Up
1.2
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
2.3
ns
tRECASYN
Asynchronous Recovery Time
0.6
ns
tHASYN
Asynchronous Removal Time
0.5
ns
R-Cell Timing
Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
1.0
ns
tINYL
Input Data Pad-to-Y LOW
1.6
ns
Input Module Predicted Routing
Delays2
tIRD1
FO=1 Routing Delay
0.5
ns
tIRD2
FO=2 Routing Delay
0.7
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-29
Table 1-15 • A54SX32A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
tIRD3
Min.
Max.
Units
FO=3 Routing Delay
0.9
ns
tIRD4
FO=4 Routing Delay
1.1
ns
tIRD8
FO=8 Routing Delay
2.0
ns
tIRD12
FO=12 Routing Delay
2.9
ns
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
Minimum Pulse Width HIGH
2.5
ns
tHPWL
Minimum Pulse Width LOW
2.5
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
2.6
0.6
5.0
ns
ns
ns
199
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
3.0
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
3.7
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
3.7
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
3.9
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
4.3
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
4.3
ns
tRPWH
Min. Pulse Width HIGH
2.5
ns
tRPWL
Min. Pulse Width LOW
2.5
ns
tRCKSW
Maximum Skew (Light Load)
1.5
ns
tRCKSW
Maximum Skew (50% Load)
2.2
ns
tRCKSW
Maximum Skew (100% Load)
2.3
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -3 0
v2.2
Table 1-15 • A54SX32A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
tHPWH
Minimum Pulse Width HIGH
2.5
ns
tHPWL
Minimum Pulse Width LOW
2.5
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
2.6
0.6
5.0
ns
ns
ns
199
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
3.0
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
3.7
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
3.7
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
3.9
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
4.3
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
4.3
ns
tRPWH
Min. Pulse Width HIGH
2.5
ns
tRPWL
Min. Pulse Width LOW
2.5
ns
tRCKSW
Maximum Skew (Light Load)
1.5
ns
tRCKSW
Maximum Skew (50% Load)
2.2
ns
tRCKSW
Maximum Skew (100% Load)
2.3
ns
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
3.1
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
2.6
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-31
Table 1-15 • A54SX32A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
tHPWH
Minimum Pulse Width HIGH
2.5
0.0
ns
tHPWL
Minimum Pulse Width LOW
2.5
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
ns
0.6
5.0
ns
ns
199
MHz
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
3.0
ns
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
3.8
ns
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
3.7
ns
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
3.9
ns
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
4.3
ns
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
4.3
ns
tRPWH
Min. Pulse Width HIGH
2.5
ns
tRPWL
Min. Pulse Width LOW
2.5
ns
tRCKSW
Maximum Skew (Light Load)
1.5
ns
tRCKSW
Maximum Skew (50% Load)
2.2
ns
tRCKSW
Maximum Skew (100% Load)
2.3
ns
2.5 V LVTTL Output Module
Timing3
tDLH
Data-to-Pad LOW to HIGH
6.3
ns
tDHL
Data-to-Pad HIGH to LOW
5.0
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
21.8
ns
tENZL
Enable-to-Pad, Z to L
4.6
ns
tENZLS
Data-to-Pad, Z to L—low slew
22.8
ns
tENZH
Enable-to-Pad, Z to H
6.7
ns
tENLZ
Enable-to-Pad, L to Z
4.1
ns
tENHZ
Enable-to-Pad, H to Z
6.7
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -3 2
v2.2
Table 1-15 • A54SX32A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C (Continued)
‘Std’ Speed
Parameter
Description
dTLH
Min.
Max.
Units
Delta LOW to HIGH
0.064
ns/pF
dTHL
Delta HIGH to LOW
0.029
ns/pF
dTHLS
Delta HIGH to LOW—low slew
0.108
ns/pF
4
3.3 V PCI Output Module Timing
tDLH
Data-to-Pad LOW to HIGH
3.8
ns
tDHL
Data-to-Pad HIGH to LOW
3.8
ns
tENZL
Enable-to-Pad, Z to L
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.8
ns
tENLZ
Enable-to-Pad, L to Z
4.8
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
3.3 V LVTTL Output Module Timing
3
tDLH
Data-to-Pad LOW to HIGH
5.3
ns
tDHL
Data-to-Pad HIGH to LOW
4.8
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
17.3
ns
tENZL
Enable-to-Pad, Z to L
4.3
ns
tENZLS
Enable-to-Pad, Z to L—low slew
31.9
ns
tENZH
Enable-to-Pad, Z to H
5.5
ns
tENLZ
Enable-to-Pad, L to Z
5.5
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
dTHLS
Delta HIGH to LOW—low slew
ns/pF
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-33
Table 1-16 • A54SX72A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C)
‘Std’ Speed
Parameter
Description
C-Cell Propagation
Delays1
tPD
Internal Array Module
Predicted Routing
Min.
Max.
Units
1.5
ns
Delays2
tDC
FO=1 Routing Delay, Direct Connect
0.1
ns
tFC
FO=1 Routing Delay, Fast Connect
0.5
ns
tRD1
FO=1 Routing Delay
0.6
ns
tRD2
FO=2 Routing Delay
0.8
ns
tRD3
FO=3 Routing Delay
1.0
ns
tRD4
FO=4 Routing Delay
1.2
ns
tRD8
FO=8 Routing Delay
2.4
ns
tRD12
FO=12 Routing Delay
3.4
ns
tRCO
Sequential Clock-to-Q
1.0
ns
tCLR
Asynchronous Clear-to-Q
1.2
ns
tPRESET
Asynchronous Preset-to-Q
1.2
ns
tSUD
Flip-Flop Data Input Set-Up
1.2
ns
tHD
Flip-Flop Data Input Hold
0.0
ns
tWASYN
Asynchronous Pulse Width
2.3
ns
tRECASYN
Asynchronous Recovery Time
0.6
ns
tHASYN
Asynchronous Hold Time
0.5
ns
R-Cell Timing
Input Module Propagation Delays
tINYH
Input Data Pad-to-Y HIGH
1.0
ns
tINYL
Input Data Pad-to-Y LOW
1.6
ns
Input Module Predicted Routing
Delays2
tIRD1
FO=1 Routing Delay
0.6
ns
tIRD2
FO=2 Routing Delay
0.8
ns
tIRD3
FO=3 Routing Delay
1.0
ns
tIRD4
FO=4 Routing Delay
1.2
ns
tIRD8
FO=8 Routing Delay
2.4
ns
tIRD12
FO=12 Routing Delay
3.4
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -3 4
v2.2
Table 1-16 • A54SX72A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
Units
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
2.4
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
2.2
ns
tHPWH
Minimum Pulse Width HIGH
2.5
ns
tHPWL
Minimum Pulse Width LOW
2.5
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
1.1
5.0
ns
ns
199
MHz
4.0
ns
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width HIGH
tRPWL
Min. Pulse Width LOW
tRCKSW
Maximum Skew (Light Load)
tRCKSW
Maximum Skew (50% Load)
tRCKSW
Maximum Skew (100% Load)
ns
4.6
ns
ns
5.3
ns
ns
5.6
ns
ns
6.5
ns
ns
6.9
ns
Dedicated (Hardwired) Array Clock Networks
tHCKH
Input LOW to HIGH
(Pad to R-Cell Input)
2.4
ns
tHCKL
Input HIGH to LOW
(Pad to R-Cell Input)
2.2
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-35
Table 1-16 • A54SX72A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
Min.
Max.
tHPWH
Minimum Pulse Width HIGH
2.5
ns
tHPWL
Minimum Pulse Width LOW
2.5
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
1.1
5.0
Units
ns
ns
199
MHz
4.0
ns
Routed Array Clock Networks
tRCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
tRCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
tRCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
tRCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
tRCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
tRCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
tRPWH
Min. Pulse Width HIGH
tRPWL
Min. Pulse Width LOW
tRCKSW
Maximum Skew (Light Load)
tRCKSW
Maximum Skew (50% Load)
tRCKSW
Maximum Skew (100% Load)
2.5 V LVTTL Output Module
ns
4.7
ns
ns
5.3
ns
ns
5.6
ns
ns
6.5
ns
ns
6.9
ns
Timing3
tDLH
Data-to-Pad LOW to HIGH
6.5
ns
tDHL
Data-to-Pad HIGH to LOW
5.0
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
22.6
ns
tENZL
Enable-to-Pad, Z to L
4.6
ns
tENZLS
Data-to-Pad, Z to L—low slew
22.8
ns
tENZH
Enable-to-Pad, Z to H
6.7
ns
tENLZ
Enable-to-Pad, L to Z
4.1
ns
tENHZ
Enable-to-Pad, H to Z
6.7
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
1 -3 6
v2.2
Table 1-16 • A54SX72A Timing Characteristics
(Worst-Case Automotive Conditions, VCCA = 2.3 V, VCCI = 3.0 V, TJ = 125°C) (Continued)
‘Std’ Speed
Parameter
Description
dTLH
Min.
Max.
Units
Delta LOW to HIGH
0.064
ns/pF
dTHL
Delta HIGH to LOW
0.029
ns/pF
dTHLS
Delta HIGH to LOW—low slew
0.108
ns/pF
4
3.3 V PCI Output Module Timing
tDLH
Data-to-Pad LOW to HIGH
3.8
ns
tDHL
Data-to-Pad HIGH to LOW
3.8
ns
tENZL
Enable-to-Pad, Z to L
2.8
ns
tENZH
Enable-to-Pad, Z to H
2.8
ns
tENLZ
Enable-to-Pad, L to Z
4.8
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
3.3 V LVTTL Output Module Timing
3
tDLH
Data-to-Pad LOW to HIGH
5.3
ns
tDHL
Data-to-Pad HIGH to LOW
4.8
ns
tDHLS
Data-to-Pad HIGH to LOW—low slew
17.3
ns
tENZL
Enable-to-Pad, Z to L
4.3
ns
tENZLS
Enable-to-Pad, Z to L—low slew
31.9
ns
tENZH
Enable-to-Pad, Z to H
5.5
ns
tENLZ
Enable-to-Pad, L to Z
5.5
ns
tENHZ
Enable-to-Pad, H to Z
4.8
ns
dTLH
Delta LOW to HIGH
0.050
ns/pF
dTHL
Delta HIGH to LOW
0.019
ns/pF
dTHLS
Delta HIGH to LOW—low slew
0.092
ns/pF
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Delays based on 35 pF loading.
4. Delays based on 10 pF loading and 25 Ω resistance.
v2.2
1-37
Pin Description
CLKA/B
TCK, I/O
Clock A and B
These pins are clock inputs for clock distribution
networks. Input levels are compatible with standard
LVTTL or 3.3 V PCI specifications. The clock input is
buffered prior to clocking the R-cells. If not used, these
pins must be set LOW or HIGH on the board except
A54SX72A. In A54SX72A these clocks can be configured
as user I/O.
QCLKA/B/C/D,
Quadrant Clock A, B, C, and D
I/O
These four pins are the quadrant clock inputs and are
only for A54SX72A with A, B, C and D corresponding to
bottom-left, bottom-right, top-left and top-right
quadrants, respectively. They are clock inputs for clock
distribution networks. Input levels are compatible with
standard LVTTL and 3.3 V PCI specifications. Each of these
clock inputs can drive up to a quarter of the chip, or they
can be grouped together to drive multiple quadrants.
The clock input is buffered prior to clocking the R-cells. If
not used as a clock it will behave as a regular I/O.
GND
Ground
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with LVTTL or 3.3 V PCI
specifications. This input is directly wired to each R-cell
and offers clock speeds independent of the number of Rcells being driven. If not used, this pin must be set LOW
or HIGH on the board and must not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate or
bidirectional buffer. Based on certain configurations,
input and output levels are compatible with LVTTL or
3.3 V PCI specifications. Unused I/O pins are
automatically tristated by the Designer software.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
Probe A/B
PRB, I/O
The Probe pin is used to output data from any userdefined design node within the device. This independent
diagnostic pin can be used in conjunction with the other
probe pin to allow real-time diagnostic output of any
signal path within the device. The Probe pin can be used
as a user-defined I/O when verification has been
completed. The pin’s probe capabilities can be
permanently disabled to protect programmed design
confidentiality.
1 -3 8
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to Table 1-5 on
page 1-9). This pin functions as an I/O when the
boundary scan state machine reaches the “logic reset”
state.
TDI, I/O
v2.2
Test Data Input
Serial input for boundary scan testing and diagnostic
probe. In flexible mode, TDI is active when the TMS pin is
set LOW (refer to Table 1-5 on page 1-9). This pin
functions as an I/O when the boundary scan state
machine reaches the “logic reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to
Table 1-5 on page 1-9). This pin functions as an I/O when
the boundary scan state machine reaches the "logic
reset" state. When Silicon Explorer II is being used, TDO
will act as an output when the "checksum" command is
run. It will return to user IO when "checksum" is
complete.
TMS
LOW supply voltage.
Test Clock
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO, TRST). In flexible
mode when the TMS pin is set LOW, the TCK, TDI, and
TDO pins are boundary scan pins (refer to Table 1-5 on
page 1-9). Once the boundary scan pins are in test mode,
they will remain in that mode until the internal
boundary scan state machine reaches the “logic reset”
state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The “logic
reset” state is reached 5 TCK cycles after the TMS pin is
set HIGH. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications.
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously
initialize or reset the boundary scan circuit. The TRST pin
is equipped with an internal pull-up resistor. This pin
functions as an I/O when the “Reserve JTAG Reset Pin” is
not selected in Designer.
VCCI
Supply Voltage
Supply voltage for I/Os. See “Recommended Operating
Conditions” on page 1-13. All VCCI power pins in the
device should be connected.
VCCA
Supply Voltage
Supply voltage for Array. See “Recommended Operating
Conditions” on page 1-13. All VCCA power pins in the
device should be connected.
Package Pin Assignments
208-Pin PQFP (Top View)
1
208
208-Pin PQFP
Figure 2-1 • 208-Pin PQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v2.2
2-1
208-Pin PQFP
208-Pin PQFP
Pin
Number
2 -2
Pin
Number
A54SX08A A54SX16A A54SX32A A54SX72A
Function
Function
Function
Function
A54SX08A A54SX16A A54SX32A A54SX72A
Function
Function
Function
Function
1
GND
GND
GND
GND
36
I/O
I/O
I/O
I/O
2
TDI, I/O
TDI, I/O
TDI, I/O
TDI, I/O
37
I/O
I/O
I/O
I/O
3
I/O
I/O
I/O
I/O
38
I/O
I/O
I/O
I/O
4
NC
I/O
I/O
I/O
39
NC
I/O
I/O
I/O
5
I/O
I/O
I/O
I/O
40
VCCI
VCCI
VCCI
VCCI
6
NC
I/O
I/O
I/O
41
VCCA
VCCA
VCCA
VCCA
7
I/O
I/O
I/O
I/O
42
I/O
I/O
I/O
I/O
8
I/O
I/O
I/O
I/O
43
I/O
I/O
I/O
I/O
9
I/O
I/O
I/O
I/O
44
I/O
I/O
I/O
I/O
10
I/O
I/O
I/O
I/O
45
I/O
I/O
I/O
I/O
11
TMS
TMS
TMS
TMS
46
I/O
I/O
I/O
I/O
12
VCCI
VCCI
VCCI
VCCI
47
I/O
I/O
I/O
I/O
13
I/O
I/O
I/O
I/O
48
NC
I/O
I/O
I/O
14
NC
I/O
I/O
I/O
49
I/O
I/O
I/O
I/O
15
I/O
I/O
I/O
I/O
50
NC
I/O
I/O
I/O
16
I/O
I/O
I/O
I/O
51
I/O
I/O
I/O
I/O
17
NC
I/O
I/O
I/O
52
GND
GND
GND
GND
18
I/O
I/O
I/O
GND
53
I/O
I/O
I/O
I/O
19
I/O
I/O
I/O
VCCA
54
I/O
I/O
I/O
I/O
20
NC
I/O
I/O
I/O
55
I/O
I/O
I/O
I/O
21
I/O
I/O
I/O
I/O
56
I/O
I/O
I/O
I/O
22
I/O
I/O
I/O
I/O
57
I/O
I/O
I/O
I/O
23
NC
I/O
I/O
I/O
58
I/O
I/O
I/O
I/O
24
I/O
I/O
I/O
I/O
59
I/O
I/O
I/O
I/O
25
NC
NC
NC
I/O
60
VCCI
VCCI
VCCI
VCCI
26
GND
GND
GND
GND
61
NC
I/O
I/O
I/O
27
VCCA
VCCA
VCCA
VCCA
62
I/O
I/O
I/O
I/O
28
GND
GND
GND
GND
63
I/O
I/O
I/O
I/O
29
I/O
I/O
I/O
I/O
64
NC
I/O
I/O
I/O
30
TRST, I/O
TRST, I/O
TRST, I/O
TRST, I/O
65
I/O
I/O
NC
I/O
31
NC
I/O
I/O
I/O
66
I/O
I/O
I/O
I/O
32
I/O
I/O
I/O
I/O
67
NC
I/O
I/O
I/O
33
I/O
I/O
I/O
I/O
68
I/O
I/O
I/O
I/O
34
I/O
I/O
I/O
I/O
69
I/O
I/O
I/O
I/O
35
NC
I/O
I/O
I/O
70
NC
I/O
I/O
I/O
v2.2
208-Pin PQFP
Pin
Number
208-Pin PQFP
A54SX08A A54SX16A A54SX32A A54SX72A
Function
Function
Function
Function
Pin
Number
A54SX08A A54SX16A A54SX32A A54SX72A
Function
Function
Function
Function
71
I/O
I/O
I/O
I/O
106
NC
I/O
I/O
I/O
72
I/O
I/O
I/O
I/O
107
I/O
I/O
I/O
I/O
73
NC
I/O
I/O
I/O
108
NC
I/O
I/O
I/O
74
I/O
I/O
I/O
QCLKA, I/O
109
I/O
I/O
I/O
I/O
75
NC
I/O
I/O
I/O
110
I/O
I/O
I/O
I/O
76
PRB, I/O
PRB, I/O
PRB, I/O
PRB,I/O
111
I/O
I/O
I/O
I/O
77
GND
GND
GND
GND
112
I/O
I/O
I/O
I/O
78
VCCA
VCCA
VCCA
VCCA
113
I/O
I/O
I/O
I/O
79
GND
GND
GND
GND
114
VCCA
VCCA
VCCA
VCCA
80
NC
NC
NC
NC
115
VCCI
VCCI
VCCI
VCCI
81
I/O
I/O
I/O
I/O
116
NC
I/O
I/O
GND
82
HCLK
HCLK
HCLK
HCLK
117
I/O
I/O
I/O
VCCA
83
I/O
I/O
I/O
VCCI
118
I/O
I/O
I/O
I/O
84
I/O
I/O
I/O
QCLKB, I/O
119
NC
I/O
I/O
I/O
85
NC
I/O
I/O
I/O
120
I/O
I/O
I/O
I/O
86
I/O
I/O
I/O
I/O
121
I/O
I/O
I/O
I/O
87
I/O
I/O
I/O
I/O
122
NC
I/O
I/O
I/O
88
NC
I/O
I/O
I/O
123
I/O
I/O
I/O
I/O
89
I/O
I/O
I/O
I/O
124
I/O
I/O
I/O
I/O
90
I/O
I/O
I/O
I/O
125
NC
I/O
I/O
I/O
91
NC
I/O
I/O
I/O
126
I/O
I/O
I/O
I/O
92
I/O
I/O
I/O
I/O
127
I/O
I/O
I/O
I/O
93
I/O
I/O
I/O
I/O
128
I/O
I/O
I/O
I/O
94
NC
I/O
I/O
I/O
129
GND
GND
GND
GND
95
I/O
I/O
I/O
I/O
130
VCCA
VCCA
VCCA
VCCA
96
I/O
I/O
I/O
I/O
131
GND
GND
GND
GND
97
NC
I/O
I/O
I/O
132
NC
NC
NC
I/O
98
VCCI
VCCI
VCCI
VCCI
133
I/O
I/O
I/O
I/O
99
I/O
I/O
I/O
I/O
134
I/O
I/O
I/O
I/O
100
I/O
I/O
I/O
I/O
135
NC
I/O
I/O
I/O
101
I/O
I/O
I/O
I/O
136
I/O
I/O
I/O
I/O
102
I/O
I/O
I/O
I/O
137
I/O
I/O
I/O
I/O
103
TDO, I/O
TDO, I/O
TDO, I/O
TDO, I/O
138
NC
I/O
I/O
I/O
104
I/O
I/O
I/O
I/O
139
I/O
I/O
I/O
I/O
105
GND
GND
GND
GND
140
I/O
I/O
I/O
I/O
v2.2
2-3
208-Pin PQFP
208-Pin PQFP
Pin
Number
2 -4
Pin
Number
A54SX08A A54SX16A A54SX32A A54SX72A
Function
Function
Function
Function
A54SX08A A54SX16A A54SX32A A54SX72A
Function
Function
Function
Function
141
NC
I/O
I/O
I/O
176
NC
I/O
I/O
I/O
142
I/O
I/O
I/O
I/O
177
I/O
I/O
I/O
I/O
143
NC
I/O
I/O
I/O
178
I/O
I/O
I/O
QCLKD, I/O
144
I/O
I/O
I/O
I/O
179
I/O
I/O
I/O
I/O
145
VCCA
VCCA
VCCA
VCCA
180
CLKA
CLKA
CLKA
CLKA, I/O
146
GND
GND
GND
GND
181
CLKB
CLKB
CLKB
CLKB, I/O
147
I/O
I/O
I/O
I/O
182
NC
NC
NC
NC
148
VCCI
VCCI
VCCI
VCCI
183
GND
GND
GND
GND
149
I/O
I/O
I/O
I/O
184
VCCA
VCCA
VCCA
VCCA
150
I/O
I/O
I/O
I/O
185
GND
GND
GND
GND
151
I/O
I/O
I/O
I/O
186
PRA, I/O
PRA, I/O
PRA, I/O
PRA, I/O
152
I/O
I/O
I/O
I/O
187
I/O
I/O
I/O
VCCI
153
I/O
I/O
I/O
I/O
188
I/O
I/O
I/O
I/O
154
I/O
I/O
I/O
I/O
189
NC
I/O
I/O
I/O
155
NC
I/O
I/O
I/O
190
I/O
I/O
I/O
QCLKC, I/O
156
NC
I/O
I/O
I/O
191
I/O
I/O
I/O
I/O
157
GND
GND
GND
GND
192
NC
I/O
I/O
I/O
158
I/O
I/O
I/O
I/O
193
I/O
I/O
I/O
I/O
159
I/O
I/O
I/O
I/O
194
I/O
I/O
I/O
I/O
160
I/O
I/O
I/O
I/O
195
NC
I/O
I/O
I/O
161
I/O
I/O
I/O
I/O
196
I/O
I/O
I/O
I/O
162
I/O
I/O
I/O
I/O
197
I/O
I/O
I/O
I/O
163
I/O
I/O
I/O
I/O
198
NC
I/O
I/O
I/O
164
VCCI
VCCI
VCCI
VCCI
199
I/O
I/O
I/O
I/O
165
I/O
I/O
I/O
I/O
200
I/O
I/O
I/O
I/O
166
I/O
I/O
I/O
I/O
201
VCCI
VCCI
VCCI
VCCI
167
NC
I/O
I/O
I/O
202
NC
I/O
I/O
I/O
168
I/O
I/O
I/O
I/O
203
NC
I/O
I/O
I/O
169
I/O
I/O
I/O
I/O
204
I/O
I/O
I/O
I/O
170
NC
I/O
I/O
I/O
205
NC
I/O
I/O
I/O
171
I/O
I/O
I/O
I/O
206
I/O
I/O
I/O
I/O
172
I/O
I/O
I/O
I/O
207
I/O
I/O
I/O
I/O
173
NC
I/O
I/O
I/O
208
TCK, I/O
TCK, I/O
TCK, I/O
TCK, I/O
174
I/O
I/O
I/O
I/O
175
I/O
I/O
I/O
I/O
v2.2
100-Pin TQFP (Top View)
100
1
100-Pin
TQFP
Figure 2-2 • 100-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v2.2
2-5
100-TQFP
100-TQFP
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
1
GND
GND
GND
36
GND
GND
GND
2
TDI, I/O
TDI, I/O
TDI, I/O
37
NC
NC
NC
3
I/O
I/O
I/O
38
I/O
I/O
I/O
4
I/O
I/O
I/O
39
HCLK
HCLK
HCLK
5
I/O
I/O
I/O
40
I/O
I/O
I/O
6
I/O
I/O
I/O
41
I/O
I/O
I/O
7
TMS
TMS
TMS
42
I/O
I/O
I/O
8
VCCI
VCCI
VCCI
43
I/O
I/O
I/O
9
GND
GND
GND
44
VCCI
VCCI
VCCI
10
I/O
I/O
I/O
45
I/O
I/O
I/O
11
I/O
I/O
I/O
46
I/O
I/O
I/O
12
I/O
I/O
I/O
47
I/O
I/O
I/O
13
I/O
I/O
I/O
48
I/O
I/O
I/O
14
I/O
I/O
I/O
49
TDO, I/O
TDO, I/O
TDO, I/O
15
I/O
I/O
I/O
50
I/O
I/O
I/O
16
TRST, I/O
TRST, I/O
TRST, I/O
51
GND
GND
GND
17
I/O
I/O
I/O
52
I/O
I/O
I/O
18
I/O
I/O
I/O
53
I/O
I/O
I/O
19
I/O
I/O
I/O
54
I/O
I/O
I/O
20
VCCI
VCCI
VCCI
55
I/O
I/O
I/O
21
I/O
I/O
I/O
56
I/O
I/O
I/O
22
I/O
I/O
I/O
57
VCCA
VCCA
VCCA
23
I/O
I/O
I/O
58
VCCI
VCCI
VCCI
24
I/O
I/O
I/O
59
I/O
I/O
I/O
25
I/O
I/O
I/O
60
I/O
I/O
I/O
26
I/O
I/O
I/O
61
I/O
I/O
I/O
27
I/O
I/O
I/O
62
I/O
I/O
I/O
28
I/O
I/O
I/O
63
I/O
I/O
I/O
29
I/O
I/O
I/O
64
I/O
I/O
I/O
30
I/O
I/O
I/O
65
I/O
I/O
I/O
31
I/O
I/O
I/O
66
I/O
I/O
I/O
32
I/O
I/O
I/O
67
VCCA
VCCA
VCCA
33
I/O
I/O
I/O
68
GND
GND
GND
34
PRB, I/O
PRB, I/O
PRB, I/O
69
GND
GND
GND
35
VCCA
VCCA
VCCA
70
I/O
I/O
I/O
2 -6
v2.2
100-TQFP
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
71
I/O
I/O
I/O
72
I/O
I/O
I/O
73
I/O
I/O
I/O
74
I/O
I/O
I/O
75
I/O
I/O
I/O
76
I/O
I/O
I/O
77
I/O
I/O
I/O
78
I/O
I/O
I/O
79
I/O
I/O
I/O
80
I/O
I/O
I/O
81
I/O
I/O
I/O
82
VCCI
VCCI
VCCI
83
I/O
I/O
I/O
84
I/O
I/O
I/O
85
I/O
I/O
I/O
86
I/O
I/O
I/O
87
CLKA
CLKA
CLKA
88
CLKB
CLKB
CLKB
89
NC
NC
NC
90
VCCA
VCCA
VCCA
91
GND
GND
GND
92
PRA, I/O
PRA, I/O
PRA, I/O
93
I/O
I/O
I/O
94
I/O
I/O
I/O
95
I/O
I/O
I/O
96
I/O
I/O
I/O
97
I/O
I/O
I/O
98
I/O
I/O
I/O
99
I/O
I/O
I/O
100
TCK, I/O
TCK, I/O
TCK, I/O
v2.2
2-7
144-Pin TQFP (Top View)
144
1
144-Pin
TQFP
Figure 2-3 • 144-Pin TQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
2 -8
v2.2
144-Pin TQFP
144-Pin TQFP
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
1
GND
GND
GND
37
I/O
I/O
I/O
2
TDI, I/O
TDI, I/O
TDI, I/O
38
I/O
I/O
I/O
3
I/O
I/O
I/O
39
I/O
I/O
I/O
4
I/O
I/O
I/O
40
I/O
I/O
I/O
5
I/O
I/O
I/O
41
I/O
I/O
I/O
6
I/O
I/O
I/O
42
I/O
I/O
I/O
7
I/O
I/O
I/O
43
I/O
I/O
I/O
8
I/O
I/O
I/O
44
VCCI
VCCI
VCCI
9
TMS
TMS
TMS
45
I/O
I/O
I/O
10
VCCI
VCCI
VCCI
46
I/O
I/O
I/O
11
GND
GND
GND
47
I/O
I/O
I/O
12
I/O
I/O
I/O
48
I/O
I/O
I/O
13
I/O
I/O
I/O
49
I/O
I/O
I/O
14
I/O
I/O
I/O
50
I/O
I/O
I/O
15
I/O
I/O
I/O
51
I/O
I/O
I/O
16
I/O
I/O
I/O
52
I/O
I/O
I/O
17
I/O
I/O
I/O
53
I/O
I/O
I/O
18
I/O
I/O
I/O
54
PRB, I/O
PRB, I/O
PRB, I/O
19
NC
NC
NC
55
I/O
I/O
I/O
20
VCCA
VCCA
VCCA
56
VCCA
VCCA
VCCA
21
I/O
I/O
I/O
57
GND
GND
GND
22
TRST, I/O
TRST, I/O
TRST, I/O
58
NC
NC
NC
23
I/O
I/O
I/O
59
I/O
I/O
I/O
24
I/O
I/O
I/O
60
HCLK
HCLK
HCLK
25
I/O
I/O
I/O
61
I/O
I/O
I/O
26
I/O
I/O
I/O
62
I/O
I/O
I/O
27
I/O
I/O
I/O
63
I/O
I/O
I/O
28
GND
GND
GND
64
I/O
I/O
I/O
29
VCCI
VCCI
VCCI
65
I/O
I/O
I/O
30
VCCA
VCCA
VCCA
66
I/O
I/O
I/O
31
I/O
I/O
I/O
67
I/O
I/O
I/O
32
I/O
I/O
I/O
68
VCCI
VCCI
VCCI
33
I/O
I/O
I/O
69
I/O
I/O
I/O
34
I/O
I/O
I/O
70
I/O
I/O
I/O
35
I/O
I/O
I/O
71
TDO, I/O
TDO, I/O
TDO, I/O
36
GND
GND
GND
72
I/O
I/O
I/O
v2.2
2-9
144-Pin TQFP
144-Pin TQFP
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
73
GND
GND
GND
109
GND
GND
GND
74
I/O
I/O
I/O
110
I/O
I/O
I/O
75
I/O
I/O
I/O
111
I/O
I/O
I/O
76
I/O
I/O
I/O
112
I/O
I/O
I/O
77
I/O
I/O
I/O
113
I/O
I/O
I/O
78
I/O
I/O
I/O
114
I/O
I/O
I/O
79
VCCA
VCCA
VCCA
115
VCCI
VCCI
VCCI
80
VCCI
VCCI
VCCI
116
I/O
I/O
I/O
81
GND
GND
GND
117
I/O
I/O
I/O
82
I/O
I/O
I/O
118
I/O
I/O
I/O
83
I/O
I/O
I/O
119
I/O
I/O
I/O
84
I/O
I/O
I/O
120
I/O
I/O
I/O
85
I/O
I/O
I/O
121
I/O
I/O
I/O
86
I/O
I/O
I/O
122
I/O
I/O
I/O
87
I/O
I/O
I/O
123
I/O
I/O
I/O
88
I/O
I/O
I/O
124
I/O
I/O
I/O
89
VCCA
VCCA
VCCA
125
CLKA
CLKA
CLKA
90
NC
NC
NC
126
CLKB
CLKB
CLKB
91
I/O
I/O
I/O
127
NC
NC
NC
92
I/O
I/O
I/O
128
GND
GND
GND
93
I/O
I/O
I/O
129
VCCA
VCCA
VCCA
94
I/O
I/O
I/O
130
I/O
I/O
I/O
95
I/O
I/O
I/O
131
PRA, I/O
PRA, I/O
PRA, I/O
96
I/O
I/O
I/O
132
I/O
I/O
I/O
97
I/O
I/O
I/O
133
I/O
I/O
I/O
98
VCCA
VCCA
VCCA
134
I/O
I/O
I/O
99
GND
GND
GND
135
I/O
I/O
I/O
100
I/O
I/O
I/O
136
I/O
I/O
I/O
101
GND
GND
GND
137
I/O
I/O
I/O
102
VCCI
VCCI
VCCI
138
I/O
I/O
I/O
103
I/O
I/O
I/O
139
I/O
I/O
I/O
104
I/O
I/O
I/O
140
VCCI
VCCI
VCCI
105
I/O
I/O
I/O
141
I/O
I/O
I/O
106
I/O
I/O
I/O
142
I/O
I/O
I/O
107
I/O
I/O
I/O
143
I/O
I/O
I/O
108
I/O
I/O
I/O
144
TCK, I/O
TCK, I/O
TCK, I/O
2 -1 0
v2.2
144-Pin FBGA (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
G
H
J
K
L
M
Figure 2-4 • 144-Pin FBGA
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v2.2
2-11
144-Pin FGBA
144-Pin FGBA
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
A1
I/O
I/O
I/O
D1
I/O
I/O
I/O
A2
I/O
I/O
I/O
D2
VCCI
VCCI
VCCI
A3
I/O
I/O
I/O
D3
TDI, I/O
TDI, I/O
TDI, I/O
A4
I/O
I/O
I/O
D4
I/O
I/O
I/O
A5
VCCA
VCCA
VCCA
D5
I/O
I/O
I/O
A6
GND
GND
GND
D6
I/O
I/O
I/O
A7
CLKA
CLKA
CLKA
D7
I/O
I/O
I/O
A8
I/O
I/O
I/O
D8
I/O
I/O
I/O
A9
I/O
I/O
I/O
D9
I/O
I/O
I/O
A10
I/O
I/O
I/O
D10
I/O
I/O
I/O
A11
I/O
I/O
I/O
D11
I/O
I/O
I/O
A12
I/O
I/O
I/O
D12
I/O
I/O
I/O
B1
I/O
I/O
I/O
E1
I/O
I/O
I/O
B2
GND
GND
GND
E2
I/O
I/O
I/O
B3
I/O
I/O
I/O
E3
I/O
I/O
I/O
B4
I/O
I/O
I/O
E4
I/O
I/O
I/O
B5
I/O
I/O
I/O
E5
TMS
TMS
TMS
B6
I/O
I/O
I/O
E6
VCCI
VCCI
VCCI
B7
CLKB
CLKB
CLKB
E7
VCCI
VCCI
VCCI
B8
I/O
I/O
I/O
E8
VCCI
VCCI
VCCI
B9
I/O
I/O
I/O
E9
VCCA
VCCA
VCCA
B10
I/O
I/O
I/O
E10
I/O
I/O
I/O
B11
GND
GND
GND
E11
GND
GND
GND
B12
I/O
I/O
I/O
E12
I/O
I/O
I/O
C1
I/O
I/O
I/O
F1
I/O
I/O
I/O
C2
I/O
I/O
I/O
F2
I/O
I/O
I/O
C3
TCK, I/O
TCK, I/O
TCK, I/O
F3
NC
NC
NC
C4
I/O
I/O
I/O
F4
I/O
I/O
I/O
C5
I/O
I/O
I/O
F5
GND
GND
GND
C6
PRA, I/O
PRA, I/O
PRA, I/O
F6
GND
GND
GND
C7
I/O
I/O
I/O
F7
GND
GND
GND
C8
I/O
I/O
I/O
F8
VCCI
VCCI
VCCI
C9
I/O
I/O
I/O
F9
I/O
I/O
I/O
C10
I/O
I/O
I/O
F10
GND
GND
GND
C11
I/O
I/O
I/O
F11
I/O
I/O
I/O
C12
I/O
I/O
I/O
F12
I/O
I/O
I/O
2 -1 2
v2.2
144-Pin FGBA
144-Pin FGBA
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
Pin Number
A54SX08A
Function
A54SX16A
Function
A54SX32A
Function
G1
I/O
I/O
I/O
K1
I/O
I/O
I/O
G2
GND
GND
GND
K2
I/O
I/O
I/O
G3
I/O
I/O
I/O
K3
I/O
I/O
I/O
G4
I/O
I/O
I/O
K4
I/O
I/O
I/O
G5
GND
GND
GND
K5
I/O
I/O
I/O
G6
GND
GND
GND
K6
I/O
I/O
I/O
G7
GND
GND
GND
K7
GND
GND
GND
G8
VCCI
VCCI
VCCI
K8
I/O
I/O
I/O
G9
I/O
I/O
I/O
K9
I/O
I/O
I/O
G10
I/O
I/O
I/O
K10
GND
GND
GND
G11
I/O
I/O
I/O
K11
I/O
I/O
I/O
G12
I/O
I/O
I/O
K12
I/O
I/O
I/O
H1
TRST, I/O
TRST, I/O
TRST, I/O
L1
GND
GND
GND
H2
I/O
I/O
I/O
L2
I/O
I/O
I/O
H3
I/O
I/O
I/O
L3
I/O
I/O
I/O
H4
I/O
I/O
I/O
L4
I/O
I/O
I/O
H5
VCCA
VCCA
VCCA
L5
I/O
I/O
I/O
H6
VCCA
VCCA
VCCA
L6
I/O
I/O
I/O
H7
VCCI
VCCI
VCCI
L7
HCLK
HCLK
HCLK
H8
VCCI
VCCI
VCCI
L8
I/O
I/O
I/O
H9
VCCA
VCCA
VCCA
L9
I/O
I/O
I/O
H10
I/O
I/O
I/O
L10
I/O
I/O
I/O
H11
I/O
I/O
I/O
L11
I/O
I/O
I/O
H12
NC
NC
NC
L12
I/O
I/O
I/O
J1
I/O
I/O
I/O
M1
I/O
I/O
I/O
J2
I/O
I/O
I/O
M2
I/O
I/O
I/O
J3
I/O
I/O
I/O
M3
I/O
I/O
I/O
J4
I/O
I/O
I/O
M4
I/O
I/O
I/O
J5
I/O
I/O
I/O
M5
I/O
I/O
I/O
J6
PRB, I/O
PRB, I/O
PRB, I/O
M6
I/O
I/O
I/O
J7
I/O
I/O
I/O
M7
VCCA
VCCA
VCCA
J8
I/O
I/O
I/O
M8
I/O
I/O
I/O
J9
I/O
I/O
I/O
M9
I/O
I/O
I/O
J10
I/O
I/O
I/O
M10
I/O
I/O
I/O
J11
I/O
I/O
I/O
M11
TDO, I/O
TDO, I/O
TDO, I/O
J12
VCCA
VCCA
VCCA
M12
I/O
I/O
I/O
v2.2
2-13
256-Pin FBGA (Top View)
1
2
3
4
5 6
7 8
9 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Figure 2-5 • 256-Pin FBGA
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
2 -1 4
v2.2
256-Pin FBGA
256-Pin FBGA
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
A1
GND
GND
GND
C4
I/O
I/O
I/O
A2
TCK, I/O
TCK, I/O
TCK, I/O
C5
NC
I/O
I/O
A3
I/O
I/O
I/O
C6
I/O
I/O
I/O
A4
I/O
I/O
I/O
C7
I/O
I/O
I/O
A5
I/O
I/O
I/O
C8
I/O
I/O
I/O
A6
I/O
I/O
I/O
C9
CLKA
CLKA
CLKA, I/O
A7
I/O
I/O
I/O
C10
I/O
I/O
I/O
A8
I/O
I/O
I/O
C11
I/O
I/O
I/O
A9
CLKB
CLKB
CLKB, I/O
C12
I/O
I/O
I/O
A10
I/O
I/O
I/O
C13
I/O
I/O
I/O
A11
I/O
I/O
I/O
C14
I/O
I/O
I/O
A12
NC
I/O
I/O
C15
I/O
I/O
I/O
A13
I/O
I/O
I/O
C16
I/O
I/O
I/O
A14
I/O
I/O
I/O
D1
I/O
I/O
I/O
A15
GND
GND
GND
D2
I/O
I/O
I/O
A16
GND
GND
GND
D3
I/O
I/O
I/O
B1
I/O
I/O
I/O
D4
I/O
I/O
I/O
B2
GND
GND
GND
D5
I/O
I/O
I/O
B3
I/O
I/O
I/O
D6
I/O
I/O
I/O
B4
I/O
I/O
I/O
D7
I/O
I/O
I/O
B5
I/O
I/O
I/O
D8
PRA, I/O
PRA, I/O
PRA, I/O
B6
NC
I/O
I/O
D9
I/O
I/O
QCLKD, I/O
B7
I/O
I/O
I/O
D10
I/O
I/O
I/O
B8
VCCA
VCCA
VCCA
D11
NC
I/O
I/O
B9
I/O
I/O
I/O
D12
I/O
I/O
I/O
B10
I/O
I/O
I/O
D13
I/O
I/O
I/O
B11
NC
I/O
I/O
D14
I/O
I/O
I/O
B12
I/O
I/O
I/O
D15
I/O
I/O
I/O
B13
I/O
I/O
I/O
D16
I/O
I/O
I/O
B14
I/O
I/O
I/O
E1
I/O
I/O
I/O
B15
GND
GND
GND
E2
I/O
I/O
I/O
B16
I/O
I/O
I/O
E3
I/O
I/O
I/O
C1
I/O
I/O
I/O
E4
I/O
I/O
I/O
C2
TDI, I/O
TDI, I/O
TDI, I/O
E5
I/O
I/O
I/O
C3
GND
GND
GND
E6
I/O
I/O
I/O
v2.2
2-15
256-Pin FBGA
256-Pin FBGA
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
E7
I/O
I/O
QCLKC, I/O
G10
GND
GND
GND
E8
I/O
I/O
I/O
G11
VCCI
VCCI
VCCI
E9
I/O
I/O
I/O
G12
I/O
I/O
I/O
E10
I/O
I/O
I/O
G13
GND
GND
GND
E11
I/O
I/O
I/O
G14
NC
I/O
I/O
E12
I/O
I/O
I/O
G15
VCCA
VCCA
VCCA
E13
NC
I/O
I/O
G16
I/O
I/O
I/O
E14
I/O
I/O
I/O
H1
I/O
I/O
I/O
E15
I/O
I/O
I/O
H2
I/O
I/O
I/O
E16
I/O
I/O
I/O
H3
VCCA
VCCA
VCCA
F1
I/O
I/O
I/O
H4
TRST, I/O
TRST, I/O
TRST, I/O
F2
I/O
I/O
I/O
H5
I/O
I/O
I/O
F3
I/O
I/O
I/O
H6
VCCI
VCCI
VCCI
F4
TMS
TMS
TMS
H7
GND
GND
GND
F5
I/O
I/O
I/O
H8
GND
GND
GND
F6
I/O
I/O
I/O
H9
GND
GND
GND
F7
VCCI
VCCI
VCCI
H10
GND
GND
GND
F8
VCCI
VCCI
VCCI
H11
VCCI
VCCI
VCCI
F9
VCCI
VCCI
VCCI
H12
I/O
I/O
I/O
F10
VCCI
VCCI
VCCI
H13
I/O
I/O
I/O
F11
I/O
I/O
I/O
H14
I/O
I/O
I/O
F12
VCCA
VCCA
VCCA
H15
I/O
I/O
I/O
F13
I/O
I/O
I/O
H16
NC
I/O
I/O
F14
I/O
I/O
I/O
J1
NC
I/O
I/O
F15
I/O
I/O
I/O
J2
NC
I/O
I/O
F16
I/O
I/O
I/O
J3
NC
I/O
I/O
G1
NC
I/O
I/O
J4
I/O
I/O
I/O
G2
I/O
I/O
I/O
J5
I/O
I/O
I/O
G3
NC
I/O
I/O
J6
VCCI
VCCI
VCCI
G4
I/O
I/O
I/O
J7
GND
GND
GND
G5
I/O
I/O
I/O
J8
GND
GND
GND
G6
VCCI
VCCI
VCCI
J9
GND
GND
GND
G7
GND
GND
GND
J10
GND
GND
GND
G8
GND
GND
GND
J11
VCCI
VCCI
VCCI
G9
GND
GND
GND
J12
I/O
I/O
I/O
2 -1 6
v2.2
256-Pin FBGA
256-Pin FBGA
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
J13
I/O
I/O
I/O
L16
NC
I/O
I/O
J14
I/O
I/O
I/O
M1
I/O
I/O
I/O
J15
I/O
I/O
I/O
M2
I/O
I/O
I/O
J16
I/O
I/O
I/O
M3
I/O
I/O
I/O
K1
I/O
I/O
I/O
M4
I/O
I/O
I/O
K2
I/O
I/O
I/O
M5
I/O
I/O
I/O
K3
NC
I/O
I/O
M6
I/O
I/O
I/O
K4
VCCA
VCCA
VCCA
M7
I/O
I/O
QCLKA, I/O
K5
I/O
I/O
I/O
M8
PRB, I/O
PRB, I/O
PRB, I/O
K6
VCCI
VCCI
VCCI
M9
I/O
I/O
I/O
K7
GND
GND
GND
M10
I/O
I/O
I/O
K8
GND
GND
GND
M11
I/O
I/O
I/O
K9
GND
GND
GND
M12
NC
I/O
I/O
K10
GND
GND
GND
M13
I/O
I/O
I/O
K11
VCCI
VCCI
VCCI
M14
NC
I/O
I/O
K12
I/O
I/O
I/O
M15
I/O
I/O
I/O
K13
I/O
I/O
I/O
M16
I/O
I/O
I/O
K14
I/O
I/O
I/O
N1
I/O
I/O
I/O
K15
NC
I/O
I/O
N2
I/O
I/O
I/O
K16
I/O
I/O
I/O
N3
I/O
I/O
I/O
L1
I/O
I/O
I/O
N4
I/O
I/O
I/O
L2
I/O
I/O
I/O
N5
I/O
I/O
I/O
L3
I/O
I/O
I/O
N6
I/O
I/O
I/O
L4
I/O
I/O
I/O
N7
I/O
I/O
I/O
L5
I/O
I/O
I/O
N8
I/O
I/O
I/O
L6
I/O
I/O
I/O
N9
I/O
I/O
I/O
L7
VCCI
VCCI
VCCI
N10
I/O
I/O
I/O
L8
VCCI
VCCI
VCCI
N11
I/O
I/O
I/O
L9
VCCI
VCCI
VCCI
N12
I/O
I/O
I/O
L10
VCCI
VCCI
VCCI
N13
I/O
I/O
I/O
L11
I/O
I/O
I/O
N14
I/O
I/O
I/O
L12
I/O
I/O
I/O
N15
I/O
I/O
I/O
L13
I/O
I/O
I/O
N16
I/O
I/O
I/O
L14
I/O
I/O
I/O
P1
I/O
I/O
I/O
L15
I/O
I/O
I/O
P2
GND
GND
GND
v2.2
2-17
256-Pin FBGA
256-Pin FBGA
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
Pin Number
A54SX16A
Function
A54SX32A
Function
A54SX72A
Function
P3
I/O
I/O
I/O
T6
I/O
I/O
I/O
P4
I/O
I/O
I/O
T7
I/O
I/O
I/O
P5
NC
I/O
I/O
T8
I/O
I/O
I/O
P6
I/O
I/O
I/O
T9
VCCA
VCCA
VCCA
P7
I/O
I/O
I/O
T10
I/O
I/O
I/O
P8
I/O
I/O
I/O
T11
I/O
I/O
I/O
P9
I/O
I/O
I/O
T12
NC
I/O
I/O
P10
NC
I/O
I/O
T13
I/O
I/O
I/O
P11
I/O
I/O
I/O
T14
I/O
I/O
I/O
P12
I/O
I/O
I/O
T15
TDO, I/O
TDO, I/O
TDO, I/O
P13
VCCA
VCCA
VCCA
T16
GND
GND
GND
P14
I/O
I/O
I/O
P15
I/O
I/O
I/O
P16
I/O
I/O
I/O
R1
I/O
I/O
I/O
R2
GND
GND
GND
R3
I/O
I/O
I/O
R4
NC
I/O
I/O
R5
I/O
I/O
I/O
R6
I/O
I/O
I/O
R7
I/O
I/O
I/O
R8
I/O
I/O
I/O
R9
HCLK
HCLK
HCLK
R10
I/O
I/O
QCLKB, I/O
R11
I/O
I/O
I/O
R12
I/O
I/O
I/O
R13
I/O
I/O
I/O
R14
I/O
I/O
I/O
R15
GND
GND
GND
R16
GND
GND
GND
T1
GND
GND
GND
T2
I/O
I/O
I/O
T3
I/O
I/O
I/O
T4
NC
I/O
I/O
T5
I/O
I/O
I/O
2 -1 8
v2.2
Package Pin Assignments
484-Pin FBGA (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
Figure 2-6 • 484-Pin FBGA
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v2.2
19
484-Pin FBGA
484-Pin FBGA
20
484-Pin FBGA
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
A1
NC
AA26
I/O
AC9
I/O
A2
NC
AB1
NC
AC10
I/O
A3
I/O
AB2
VCCI
AC11
I/O
A4
I/O
AB3
I/O
AC12
QCLKA, I/O
A5
I/O
AB4
I/O
AC13
I/O
A6
I/O
AB5
I/O
AC14
I/O
A7
I/O
AB6
I/O
AC15
I/O
A8
I/O
AB7
I/O
AC16
I/O
A9
I/O
AB8
I/O
AC17
I/O
A10
I/O
AB9
I/O
AC18
I/O
A11
I/O
AB10
I/O
AC19
I/O
A12
I/O
AB11
I/O
AC20
VCCI
A13
I/O
AB12
PRB, I/O
AC21
I/O
A14
NC
AB13
VCCA
AC22
I/O
A15
I/O
AB14
I/O
AC23
I/O
A16
I/O
AB15
I/O
AC24
I/O
A17
I/O
AB16
I/O
AC25
I/O
A18
I/O
AB17
I/O
AC26
I/O
A19
I/O
AB18
I/O
AD1
I/O
A20
I/O
AB19
I/O
AD2
I/O
A21
I/O
AB20
TDO, I/O
AD3
GND
A22
I/O
AB21
GND
AD4
I/O
A23
I/O
AB22
I/O
AD5
I/O
A24
I/O
AB23
I/O
AD6
I/O
A25
NC
AB24
I/O
AD7
I/O
A26
NC
AB25
I/O
AD8
I/O
AA1
I/O
AB26
I/O
AD9
VCCI
AA2
I/O
AC1
I/O
AD10
I/O
AA3
VCCA
AC2
I/O
AD11
I/O
AA4
I/O
AC3
I/O
AD12
I/O
AA5
I/O
AC4
I/O
AD13
VCCI
AA22
I/O
AC5
VCCI
AD14
I/O
AA23
I/O
AC6
I/O
AD15
I/O
AA24
I/O
AC7
VCCI
AD16
I/O
AA25
I/O
AC8
I/O
AD17
VCCI
v2.2
Package Pin Assignments
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
AD18
I/O
AF1
NC
B10
I/O
AD19
I/O
AF2
NC
B11
I/O
AD20
I/O
AF3
I/O
B12
I/O
AD21
I/O
AF4
I/O
B13
VCCI
AD22
I/O
AF5
I/O
B14
CLKA, I/O
AD23
VCCI
AF6
I/O
B15
I/O
AD24
I/O
AF7
I/O
B16
I/O
AD25
I/O
AF8
I/O
B17
I/O
AD26
I/O
AF9
I/O
B18
VCCI
AE1
NC
AF10
I/O
B19
I/O
AE2
I/O
AF11
I/O
B20
I/O
AE3
I/O
AF12
NC
B21
I/O
AE4
I/O
AF13
HCLK
B22
I/O
AE5
I/O
AF14
QCLKB, I/O
B23
I/O
AE6
I/O
AF15
I/O
B24
I/O
AE7
I/O
AF16
I/O
B25
I/O
AE8
I/O
AF17
I/O
B26
NC
AE9
I/O
AF18
I/O
C1
I/O
AE10
I/O
AF19
I/O
C2
I/O
AE11
I/O
AF20
I/O
C3
I/O
AE12
I/O
AF21
I/O
C4
I/O
AE13
I/O
AF22
I/O
C5
I/O
AE14
I/O
AF23
I/O
C6
VCCI
AE15
I/O
AF24
I/O
C7
I/O
AE16
I/O
AF25
NC
C8
I/O
AE17
I/O
AF26
NC
C9
VCCI
AE18
I/O
B1
NC
C10
I/O
AE19
I/O
B2
NC
C11
I/O
AE20
I/O
B3
I/O
C12
I/O
AE21
I/O
B4
I/O
C13
PRA, I/O
AE22
I/O
B5
I/O
C14
I/O
AE23
I/O
B6
I/O
C15
QCLKD, I/O
AE24
I/O
B7
I/O
C16
I/O
AE25
NC
B8
I/O
C17
I/O
AE26
NC
B9
I/O
C18
I/O
v2.2
21
484-Pin FBGA
22
484-Pin FBGA
484-Pin FBGA
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
C19
I/O
E2
I/O
G1
I/O
C20
VCCI
E3
I/O
G2
I/O
C21
I/O
E4
I/O
G3
I/O
C22
I/O
E5
GND
G4
I/O
C23
I/O
E6
TDI, IO
G5
I/O
C24
I/O
E7
I/O
G22
I/O
C25
I/O
E8
I/O
G23
VCCA
C26
I/O
E9
I/O
G24
I/O
D1
I/O
E10
I/O
G25
I/O
D2
TMS
E11
I/O
G26
I/O
D3
I/O
E12
I/O
H1
I/O
D4
VCCI
E13
VCCA
H2
I/O
D5
I/O
E14
CLKB, I/O
H3
I/O
D6
TCK, I/O
E15
I/O
H4
I/O
D7
I/O
E16
I/O
H5
I/O
D8
I/O
E17
I/O
H22
I/O
D9
I/O
E18
I/O
H23
I/O
D10
I/O
E19
I/O
H24
I/O
D11
I/O
E20
I/O
H25
I/O
D12
QCLKC, I/O
E21
I/O
H26
I/O
D13
I/O
E22
I/O
J1
I/O
D14
I/O
E23
I/O
J2
I/O
D15
I/O
E24
I/O
J3
I/O
D16
I/O
E25
VCCI
J4
I/O
D17
I/O
E26
GND
J5
I/O
D18
I/O
F1
VCCI
J22
I/O
D19
I/O
F2
I/O
J23
I/O
D20
I/O
F3
I/O
J24
I/O
D21
VCCI
F4
I/O
J25
VCCI
D22
GND
F5
I/O
J26
I/O
D23
I/O
F22
I/O
K1
I/O
D24
I/O
F23
I/O
K2
VCCI
D25
I/O
F24
I/O
K3
I/O
D26
I/O
F25
I/O
K4
I/O
E1
I/O
F26
I/O
K5
VCCA
v2.2
Package Pin Assignments
484-Pin FBGA
484-Pin FBGA
484-Pin FBGA
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
K10
GND
M5
I/O
P4
I/O
K11
GND
M10
GND
P5
VCCA
K12
GND
M11
GND
P10
GND
K13
GND
M12
GND
P11
GND
K14
GND
M13
GND
P12
GND
K15
GND
M14
GND
P13
GND
K16
GND
M15
GND
P14
GND
K17
GND
M16
GND
P15
GND
K22
I/O
M17
GND
P16
GND
K23
I/O
M22
I/O
P17
GND
K24
NC
M23
I/O
P22
I/O
K25
I/O
M24
I/O
P23
I/O
K26
I/O
M25
I/O
P24
VCCI
L1
I/O
M26
I/O
P25
I/O
L2
I/O
N1
I/O
P26
I/O
L3
I/O
N2
VCCI
R1
I/O
L4
I/O
N3
I/O
R2
I/O
L5
I/O
N4
I/O
R3
I/O
L10
GND
N5
I/O
R4
I/O
L11
GND
N10
GND
R5
TRST, I/O
L12
GND
N11
GND
R10
GND
L13
GND
N12
GND
R11
GND
L14
GND
N13
GND
R12
GND
L15
GND
N14
GND
R13
GND
L16
GND
N15
GND
R14
GND
L17
GND
N16
GND
R15
GND
L22
I/O
N17
GND
R16
GND
L23
I/O
N22
VCCA
R17
GND
L24
I/O
N23
I/O
R22
I/O
L25
I/O
N24
I/O
R23
I/O
L26
I/O
N25
I/O
R24
I/O
M1
NC
N26
NC
R25
I/O
M2
I/O
P1
I/O
R26
I/O
M3
I/O
P2
I/O
T1
I/O
M4
I/O
P3
I/O
T2
I/O
v2.2
23
484-Pin FBGA
24
484-Pin FBGA
Pin Number
A54SX72A
Function
Pin Number
A54SX72A
Function
T3
I/O
V2
I/O
T4
I/O
V3
I/O
T5
I/O
V4
I/O
T10
GND
V5
I/O
T11
GND
V22
VCCA
T12
GND
V23
I/O
T13
GND
V24
I/O
T14
GND
V25
I/O
T15
GND
V26
I/O
T16
GND
W1
I/O
T17
GND
W2
I/O
T22
I/O
W3
I/O
T23
I/O
W4
I/O
T24
I/O
W5
I/O
T25
I/O
W22
I/O
T26
I/O
W23
VCCA
U1
I/O
W24
I/O
U2
VCCI
W25
I/O
U3
I/O
W26
I/O
U4
I/O
Y1
I/O
U5
I/O
Y2
I/O
U10
GND
Y3
I/O
U11
GND
Y4
I/O
U12
GND
Y5
I/O
U13
GND
Y22
I/O
U14
GND
Y23
I/O
U15
GND
Y24
VCCI
U16
GND
Y25
I/O
U17
GND
Y26
I/O
U22
I/O
U23
I/O
U24
I/O
U25
VCCI
U26
I/O
V1
I/O
v2.2
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version
Changes in current version (v2.2)
Page
v2.1
RoHS information was added to the "Ordering Information".
ii
May 2006
The Product Plan was removed because all of the devices have been fully characterized.
N/A
The "Dedicated Mode" section was updated.
1-8
The "Development Tool Support" section was updated.
1-11
The "Programming" section was updated.
1-11
1.
Note 2 was added to Table 1-7 • Absolute Maximum Ratings
1-13
v2.0
A note was added to the "Ordering Information".
ii
September 2003
Note 1 was added to Table 1-8 • Recommended Operating Conditions.
1-13
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Datasheet
Supplement.” The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Export Administration Regulations (EAR)
The product described in this datasheet is subject to the Export Administration Regulations (EAR). They could require
an approved export license prior to export from the United States. An export includes release of product or disclosure
of technology to a foreign national inside or outside the United States.
v2.2
1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Corporation
Actel Europe Ltd.
Actel Japan
www.jp.actel.com
Actel Hong Kong
www.actel.com.cn
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