TI1 OPA650N-250 Wideband, low power voltage feedback operational amplifier Datasheet

®
OPA650
OPA
650
OPA
650
Wideband, Low Power Voltage Feedback
OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
● LOW POWER: 50mW
The OPA650 is a low power, wideband voltage feedback operational amplifier. It features a high bandwidth of 560MHz as well as a 12-bit settling time of
only 20ns. The low distortion allows its use in communications applications, while the wide bandwidth and
true differential input stage make it suitable for use in
a variety of active filter applications. Its low distortion
gives exceptional performance for telecommunications, medical imaging and video applications.
● UNITY GAIN STABLE BANDWIDTH:
560MHz
● LOW HARMONICS: –77dBc at 5MHz
● FAST SETTLING TIME: 20ns to 0.01%
● LOW INPUT BIAS CURRENT: 5µA
● DIFFERENTIAL GAIN/PHASE ERROR:
0.01%/0.03°
● HIGH OUTPUT CURRENT: 85mA
APPLICATIONS
● HIGH RESOLUTION VIDEO
● BASEBAND AMPLIFIER
● CCD IMAGING AMPLIFIER
● ULTRASOUND SIGNAL PROCESSING
The OPA650 is internally compensated for unity-gain
stability. This amplifier has a fully symmetrical differential input due to its “classical” operational amplifier
circuit architecture. Its unusual combination of speed,
accuracy and low power make it an outstanding choice
for many portable, multi-channel and other high speed
applications, where power is at a premium.
The OPA650 is also available in dual (OPA2650) and
quad (OPA4650) configurations.
● ADC/DAC GAIN AMPLIFIER
● ACTIVE FILTERS
● HIGH SPEED INTEGRATORS
+VS
● DIFFERENTIAL AMPLIFIER
Non-Inverting
Input
Output
Stage
Inverting
Input
Current
Mirror
Output
CC
–VS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1994 Burr-Brown Corporation
SBOS041
PDS-1264F
1
OPA650
Printed in U.S.A. March, 1998
SPECIFICATIONS
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
OPA650P, U, N
PARAMETER
CONDITIONS
FREQUENCY RESPONSE
Closed-Loop Bandwidth(2)
Gain Bandwidth Product
Slew Rate
Over Specified Temperature
Rise Time
Fall Time
Settling Time
0.01%
0.1%
1%
Spurious Free Dynamic Range
Differential Gain
Differential Phase
Bandwidth for 0.1dB Gain Flatness
MIN
G = +1
G = +2
G = +5
G = +10
G = +1, 2V Step
0.2V Step
0.2V Step
G = +1, 2V Step
G = +1, 2V Step
G = +1, 2V Step
G = +1, f = 5.0 MHz, VO = 2Vp-p
RL = 100Ω
RL = 200Ω
G = +1, NTSC, VO = 1.4Vp, RL = 150Ω
G = +1, NTSC, VO = 1.4Vp, RL = 150Ω
G = +2
INPUT OFFSET VOLTAGE
Input Offset Voltage
Average Drift
Power Supply Rejection (+VS)
(–VS)
INPUT BIAS CURRENT
Input Bias Current
Over Temperature
Input Offset Current
Over Temperature
OUTPUT
Voltage Output
Over Specified Temperature
Current Output, Sourcing
Over Specified Temperature
Current Output, Sinking
Over Specified Temperature
Short Circuit Current
Output Resistance
MAX
UNITS
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
ns
ns
ns
ns
73
77
0.01
0.03
25
✻
✻
✻
✻
✻
dBc
dBc
%
Degrees
MHz
5
VCM = 0V
0.5
20
30
1
3
±2.2
65
TYP
✻(1)
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
VCM = 0V
VCM = ±0.5V
MIN
560
140
37
18
180
240
220
1
1
19.6
10.2
6.3
±5
60
47
RS = 10kΩ
RS = 50Ω
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
Over Specified Temperature
OPA650UB, NB
MAX
±1
±3
76
53
|VS| = 4.5V to 5.5V
NOISE
Input Voltage Noise
Noise Density, f = 100Hz
f = 10kHz
f = 1MHz
f = 1MHz to 100MHz
Integrated Noise, BW = 10Hz to 100MHz
Input Bias Current Noise
Current Noise Density, f = 0.1MHz to 100MHz
Noise Figure (NF)
INPUT VOLTAGE RANGE
Common-Mode Input Range
Over Specified Temperature
Common-Mode Rejection
TYP
70
50
0.6
✻
✻
✻
±2.5
mV
µV/°C
dB
dB
✻
10
20
0.5
2
µA
µA
µA
µA
0.2
43
9.4
8.4
8.4
84
✻
✻
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
µVrms
1.2
✻
pA/√Hz
4
19.5
✻
✻
dB
dB
✻
✻
V
V
dB
✻
✻
kΩ || pF
MΩ || pF
±2.8
✻
70
90
15 || 1
16 || 1
VO = ±2V, RL = 100Ω
VO = ±2V, RL = 100Ω
45
43
51
46
44
✻
dB
dB
No Load
RL = 250Ω
RL = 100Ω
±2.2
±2.2
±2.0
75
65
65
35
±3.0
±2.5
±2.3
110
±2.4
±2.4
±2.2
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
mA
mA
mA
mA
mA
Ω
85
✻
✻
150
0.08
0.1MHz, G = +1
POWER SUPPLY
Specified Operating Voltage
Derated Voltage Range
Quiescent Current
Over Specified Temperature
±4.5
TEMPERATURE RANGE
Specification: P, U, N, UB, NB
Thermal Resistance, θJA
P
8-Pin DIP
U
SO-8
N
SOT23-5
±5
±5.1
–40
100
125
150
✻
✻
±5.5
±7.75
±8.75
✻
+85
✻
±5.1
✻
✻
✻
✻
±6.5
±7.5
V
V
mA
mA
✻
°C
°C/W
°C/W
°C/W
NOTES: (1) An asterisk (✻) specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The OPA650
is nominally compensated assuming 2pF parasitic load. The demonstration boards show low parasitic layouts for the different package styles.
®
OPA650
2
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
Supply ............................................................................................... ±5.5V
Internal Power Dissipation .................................. See Thermal Conditions
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: P, U, UB, N, NB ............ –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
(soldering, SOIC 3s) ....................................... +260°C
Junction Temperature (TJ ) ............................................................ +175°C
Top View
DIP/SO-8
NC
1
8
NC
–Input
2
7
+VS
+Input
3
6
Output
–VS
4
5
NC
ELECTROSTATIC
DISCHARGE SENSITIVITY
SOT23-5
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
Output
1
–VS
2
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published specifications.
+Input
3
5
+VS
4
–Input
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
OPA650U
OPA650UB
OPA650N
SO-8 Surface Mount
SO-8 Surface Mount
5-pin SOT23-5
182
182
331
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OPA650U
OPA650UB
A50
OPA650NB
5-pin SOT23-5
331
–40°C to +85°C
A50B
8-Pin Plastic DIP
006
–40°C to +85°C
OPA650P
OPA650P
TEMPERATURE
RANGE
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
OPA650U
OPA650UB
OPA650N-250
OPA650N-3k
OPA650NB-250
OPA650NB-3k
OPA650P
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade of the SO-8 package
will be marked with a “B” by pin 8. The “B” grade of the SOT23-5 will be marked with a “B” near pins 3 and 4. (3) The SOT23-5 is only available on a 7" tape and reel
(e.g. ordering 250 pieces of “OPA650N-250” will get a single 250 piece tape and reel. Ordering 3000 pieces of “OPA650N-3k” will get a single 3000 piece tape and reel).
Please refer to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or
licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support
devices and/or systems.
®
3
OPA650
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for Gain of +1.
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
AOL, PSR AND CMRR vs TEMPERATURE
100
AOL, PSR and CMRR (dB)
Common Mode-Rejection (dB)
100
90
80
70
90
CMRR
80
PSR+
70
PSR–
60
AOL
50
40
60
–4
–3
–2
–1
0
1
2
3
–50
4
–25
0
INPUT BIAS CURRENT AND OFFSET VOLTAGE
vs TEMPERATURE
6
1
5
0
Supply Current (±mA)
VOS
IB
25
50
75
100
4
–40
–20
0
20
40
60
80
Temperature (°C)
OUTPUT CURRENT vs TEMPERATURE
INPUT VOLTAGE AND CURRENT NOISE
vs FREQUENCY
100
100
Input Current Noise (pA/√Hz)
I+
O
90
Input Voltage Noise (nV/√Hz)
Output Current (±mA)
5
Temperature (°C)
110
100
125
6
3
–60
–1
0
75
7
Offset Voltage (mV)
Input Bias Current (mA)
2
–25
50
SUPPLY CURRENT vs TEMPERATURE
7
4
–50
25
Temperature (°C)
Common-Mode Voltage (V)
Voltage Noise
10
Non-inverting and
Inverting Current Noise
IO–
1
80
–50
–25
0
25
50
75
100
100
®
OPA650
1k
10k
Frequency (Hz)
Temperature (°C)
4
100k
1M
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for Gain of +1.
SMALL SIGNAL TRANSIENT RESPONSE
(G = +1)
RECOMMENDED ISOLATION RESISTANCE
vs CAPACITIVE LOAD
40
200
120
30
Output Voltage (mV)
Isolation Resistance, RISO (Ω)
160
25Ω
20
RISO
OPA650
10
CL
80
40
0
–40
–80
–120
1kΩ
–160
0
–200
0
20
40
60
80
100
Time (5ns/div)
Capacitive Load, C (pF)
L
LARGE SIGNAL TRANSIENT RESPONSE
(G = +1)
CLOSED-LOOP BANDWIDTH (G = +1)
2.0
6
1.6
3
SO-8 Bandwidth
= 560MHz
0.8
0.4
Gain (dB)
Output Voltage (V)
1.2
0
–0.4
0
–3
DIP Bandwidth
= 520MHz
–0.8
–1.2
–6
–1.6
–2.0
–9
1M
Time (5ns/div)
10M
100M
1G
Frequency (Hz)
CLOSED-LOOP BANDWIDTH (G = +2)
CLOSED-LOOP BANDWIDTH (G = +5)
12
20
9
17
SO-8/DIP Bandwidth = 140MHz
SO-8/DIP Bandwidth = 37MHz
14
3
Gain (dB)
Gain (dB)
6
0
–3
11
8
5
–6
2
–9
–12
–1
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
1G
Frequency (Hz)
®
5
OPA650
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for Gain of +1.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
CLOSED LOOP BANDWIDTH (G = +10)
26
60
23
50
20
0
Gain
SO-8/DIP Bandwidth = 18MHz
14
11
–45
Phase
30
Phase (°)
40
17
Gain (dB)
Gain (dB)
+45
–90
20
–135
10
–180
8
5
2
0
1M
10M
100M
–225
1k
1G
10k
100k
Frequency (Hz)
10M
100M
1G
Frequency (Hz)
HARMONIC DISTORTION vs TEMPERATURE
(fO = 5MHz, VO = 2Vp-p, G = +1)
HARMONIC DISTORTION vs FREQUENCY
(G = +1, VO = 2Vp-p, RL = 100Ω)
–50
Harmonic Distortion (dBc)
–40
Harmonic Distortion (dBc)
1M
–50
–60
–70
3fO
–80
2fO
–90
100k
1M
10M
–60
3fO
–70
2fO
–80
–90
–60
100M
Frequency (Hz)
–40
–20
0
20
40
60
80
100
Temperature (°C)
5MHz HARMONIC DISTORTION
vs OUTPUT SWING
10MHz HARMONIC DISTORTION
vs OUTPUT SWING
–60
–50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
G = +2
–70
–80
3fO
2fO
–90
–100
–60
3fO
2fO
–70
–80
–90
0.1
1
10
0.1
Output Swing (Vp-p)
®
OPA650
1
Output Swing (Vp-p)
6
10
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for Gain of +1.
HARMONIC DISTORTION vs GAIN
(fO = 5MHz, VO = 2Vp-p)
Harmonic Distortion (dBc)
–40
–50
3fO
2fO
–60
–70
–80
1
2
3
4
5
6
7
8
9
10
Non-Inverting Gain (V/V)
DISCUSSION OF
PERFORMANCE
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.
c) Careful selection and placement of external components will preserve the high frequency performance of the
OPA650. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to
the package pins. Other network components, such as noninverting input termination resistors, should also be placed
close to the package.
Even with a low parasitic capacitance shunting external
resistors, excessively high resistor values can create significant time constants and degrade performance. Good metal
film or surface mount resistors have approximately 0.2pF in
shunt with the resistor. For resistor values > 1.5kΩ, this adds
a pole and/or zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible consistent
with output loading considerations. The 402Ω feedback
used for the Typical Performance Plots is a good starting
point for design. Note that a 25Ω feedback resistor, rather
than a direct short, is suggested for a unity gain follower.
This effectively reduces the Q of what would otherwise be
a parasitic inductance (the feedback wire) into the parasitic
capacitance at the inverting input.
The OPA650 is a low power, wideband voltage feedback
operational amplifier. Each channel is internally compensated to provide unity gain stability. The OPA650’s voltage
feedback architecture features true differential and fully symmetrical inputs. This minimizes offset errors, making the
OPA650 well suited for implementing filter and instrumentation designs. The OPA650’s AC performance is optimized
to provide a gain bandwidth product of 180MHz and a fast
0.1% settling time of 10.2ns, which is an important consideration in high speed data conversion applications. Along
with its excellent settling characteristics, the low DC input
offset of ±1mV and drift of ±3µV/°C support high accuracy
requirements. In applications requiring a higher slew rate and
wider bandwidth, such as video and high bit rate digital
communications, consider the current feedback OPA658.
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high frequency amplifier like the OPA650 requires careful attention to layout
parasitics and selection of external components. Recommendations for PC board layout and component selection include:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1µF decoupling capacitors. At the pins,
®
7
OPA650
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RISO from
the plot of recommended RISO vs capacitive load. Low
parasitic loads may not need an RISO since the OPA650 is
nominally compensated to operate with a 2pF parasitic load.
+VS
VS
2
VOUT =
VS
+ 2•VAC
2
ROUT
VAC
OPA650
RL
402Ω
If a long trace is required and the 6dB signal loss intrinsic to
doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimensions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.
If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.
e) Socketing a high speed part like the OPA650 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.
402Ω
FIGURE 1. Single Supply Operation.
OFFSET VOLTAGE ADJUSTMENT
If additional offset adjustment is needed, the circuit in
Figure 2 can be used without degrading offset drift with
temperature. Avoid external adjustment whenever possible
since extraneous noise, such as power supply noise, can be
inadvertently coupled into the amplifier’s inverting input
terminal. Remember that additional offset errors can be
created by the amplifier’s input bias currents. Whenever
possible, match the impedance seen by both inputs as is
shown with R3. This will reduce input bias current errors to
the amplifier’s offset current.
+VS
R2
RTrim
20kΩ
47kΩ
–VS
NOTE: (1) R3 is
optional and can
be used to cancel
offset errors due
to input bias currents.
OPA650
0.1µF
R1
(1)
R3 = R1 || R2
VIN or Ground
Output Trim Range ≅ +VS
R2 to –V R2
S
RTrim
RTrim
FIGURE 2. Offset Voltage Trim.
The OPA650 is nominally specified for operation using ±5V
power supplies. A 10% tolerance on the supplies, or an ECL
–5.2V for the negative supply, is within the maximum specified total supply voltage of 11V. Higher supply voltages can
break down internal junctions possibly leading to catastrophic
failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common
mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow
non-standard or single supply operation. Figure 1 shows one
approach to single-supply operation.
ESD PROTECTION
ESD damage has been well recognized for MOSFET devices, but any semiconductor device is vulnerable to this
potentially damaging source. This is particularly true for
very high speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers, this may cause a noticeable
degradation of offset voltage and drift. Therefore, ESD
handling precautions are strongly recommended when handling the OPA650.
®
OPA650
+VS
8
OUTPUT DRIVE CAPABILITY
The OPA650 has been optimized to drive 75Ω and 100Ω
resistive loads. The device can drive a 2Vp-p into a 75Ω load.
This high-output drive capability makes the OPA650 an ideal
choice for a wide range of RF, IF, and video applications. In
many cases, additional buffer amplifiers are unneeded.
DRIVING CAPACITIVE LOADS
The OPA650’s output stage has been optimized to drive low
resistive loads. Capacitive loads, however, will decrease the
amplifier’s phase margin which may cause high frequency
peaking or oscillations. Capacitive loads greater than 10pF
should be isolated by connecting a small resistance, usually
15Ω to 30Ω, in series with the output as shown in Figure 4.
This is particularly important when driving high capacitance
loads such as flash A/D converters. Increasing the gain from
+1 will improve the capacitive load drive due to increased
phase margin.
Many demanding high-speed applications such as driving
A/D converters require op amps with low wideband output
impedance. For example, low output impedance is essential
when driving the signal-dependent capacitances at the inputs
of flash A/D converters. As shown in Figure 3, the OPA650
maintains very low-closed loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing.
In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated in
its characteristic impedance.
SMALL-SIGNAL OUTPUT IMPEDANCE
vs FREQUENCY
1k
Output Impedance (Ω)
G = +1
25Ω
100
(RISO typically 15Ω to 30Ω)
10
RISO
OPA650
1
0.1
RL
CL
0.01
10k
100k
1M
10M
100M
Frequency (Hz)
FIGURE 4. Driving Capacitive Loads.
FIGURE 3. Small-Signal Output Impedance vs Frequency.
FREQUENCY RESPONSE COMPENSATION
The OPA650 is internally compensated and is stable in unity
gain with a phase margin of approximately 60°. However,
the unity gain buffer is the most demanding circuit configuration for loop stability and oscillations are most likely to
occur in this gain. If possible, use the device in a noise gain
greater than one to improve phase margin and reduce the
susceptibility to oscillation. (Note that, from a stability
standpoint, an inverting gain of –1V/V is equivalent to a
noise gain of 2.) Frequency response for other gains are
shown in the Typical Performance Curves.
THERMAL CONSIDERATIONS
The OPA650 will not require heatsinking under most operating conditions. Maximum desired junction temperature
will limit the maximum allowed internal power dissipation
as described below. In no case should the maximum junction
temperature be allowed to exceed +175°C.
Operating junction temperature (TJ) is given by TA +
PDθJA. The total internal power dissipation (P D) is a combination of the total quiescent power (PDQ) and the power
dissipated in of the output stage (PDL) to deliver load
power. Quiescent power is simply the specified no-load
supply current times the total supply voltage across the
part. PDL will depend on the required output signal and load
but would, for a grounded resistive load, be at a maximum
when the output is a fixed DC voltage equal to 1/2 of either
supply voltage (assuming equal bipolar supplies). Under
this condition, PDL = VS2/(4•RL) where RL includes feedback network loading. Note that it is the power dissipated
in the output stage and not in the load that determines
internal power dissipation. As an example, compute the
maximum TJ for an OPA650N at AV = +2, RL = 100Ω, RFB
= 402Ω, ±VS = ±5V, with the output at |VS/2|, and the
specified maximum TA = +85°C. PD = 10V•8.75mA + (52)/
(4•(100Ω||804Ω)) = 158mW. Maximum T J = +85°C +
0.158W•150°C/W = 109°C.
The high frequency response of the OPA650 in a good
layout is very flat with frequency. However, some circuit
configurations such as those where large feedback resistances are used, can produce high-frequency gain peaking.
This peaking can be minimized by connecting a small
capacitor in parallel with the feedback resistor. This capacitor compensates for the closed-loop, high-frequency, transfer function zero that results from the time constant formed
by the input capacitance of the amplifier (typically 2pF after
PC board mounting), and the input and feedback resistors.
The selected compensation capacitor may be a trimmer, a
fixed capacitor, or a planned PC board capacitance. The
capacitance value is strongly dependent on circuit layout and
closed-loop gain. Using small resistor values will preserve
®
9
OPA650
the phase margin and avoid peaking by keeping the break
frequency of this zero sufficiently high. When high closedloop gains are required, a three-resistor attenuator (teenetwork) is recommended to avoid using large value resistors with large time constants.
Harmonic Distortion (dBc)
–60
PULSE SETTLING TIME
High speed amplifiers like the OPA650 are capable of
extremely fast settling time with a pulse input. Excellent
frequency response flatness and phase linearity are required
to get the best settling times. As shown in the specifications
table, settling time for a ±1V step at a gain of +1 for the
OPA650 is extremely fast. The specification is defined as
the time required, after the input transition, for the output to
settle within a specified error band around its final value. For
a 2V step, 1% settling corresponds to an error band of
±20mV, 0.1% to an error band of ±2mV, and 0.01% to an
error band of ±0.2mV. For the best settling times, particularly into an ADC capacitive load, little or no peaking in the
frequency response can be allowed. Using the recommended
RISO for capacitive loads will limit this peaking and reduce
the settling times. Fast, extremely fine scale settling (0.01%)
requires close attention to ground return currents in the
supply decoupling capacitors. For highest performance, consider the OPA642 which isolates the output stage decoupling
from the rest of the amplifier.
3fO
–80
2fO
–90
10
100
1k
Load Resistance (Ω)
FIGURE 5. 5MHz Harmonic Distortion vs Load Resistance.
NOISE FIGURE vs SOURCE RESISTANCE
30
NF = 10 LOG 1 +
Noise Figure (dB)
25
DIFFERENTIAL GAIN AND PHASE
Differential Gain (DG) and Differential Phase (DP) are
among the more important specifications for video applications. The percentage change in closed-loop gain over a
specified change in output voltage level is defined as DG.
DP is defined as the change in degrees of the closed-loop
phase over the same output voltage change. DG and DP are
both specified at the NTSC sub-carrier frequency of 3.58MHz.
DG and DP increase closed-loop gain and output voltage
transition. All measurements were performed using a
Tektronix model VM700 Video Measurement Set.
en2 + (InRS)2
4KTRS
20
15
10
5
0
10
100
1k
10k
100k
Source Resistance (Ω)
FIGURE 6. Noise Figure vs Source Resistance.
SPICE MODELS AND EVALUATION BOARD
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE
models are available on a disk from the Burr-Brown Applications Department.
Demonstration boards are available for each OPA650 package style. These boards implement a very low parasitic
layout that will produce the excellent frequency and pulse
responses shown in the Typical Performance Curves. For
each package style, the recommended demonstration board
is:
DISTORTION
The OPA650’s harmonic distortion characteristics into a
100Ω load are shown versus frequency and power output in
the typical performance curves. Distortion can be significantly improved by increasing the load resistance as illustrated in Figure 5. Remember to include the contribution of
the feedback network when calculating the effective load
resistance seen by the amplifier.
NOISE FIGURE
The OPA650 voltage noise spectral density is specified in
the Typical Performance Curves. For RF applications, however, Noise Figure (NF) is often the preferred noise specification since it allows system noise performance to be more
easily calculated. The OPA650’s Noise Figure vs Source
Resistance is shown in Figure 6.
DEM-OPA65xP
8-Pin DIP for the OPA650P
DEM-OPA65xU
SO-8 for the OPA650U
DEM-OPA6xxN
SOT23 for the OPA650N
Contact your local Burr-Brown sales office or distributor to
order demonstration boards.
®
OPA650
–70
10
TYPICAL APPLICATION
402Ω
402Ω
75Ω Transmission Line
75Ω
VOUT
OPA650
Video
Input
75Ω
75Ω
FIGURE 7. Low Distortion Video Amplifier.
R8
R4
R3
J2
–In
402Ω
C1
2.2µF
+
R2
1
C3
0.1µF
2
R6
J1
GND
P1
7
OPA650
3
4
+In
+5V
2
6
R1
J1
Out
1
R5
C2
0.1µF
R7
+
GND
2
–5V
P2
C4
2.2µF
NOTE: Values for R1, R3, R5, R6, and R7 are chosen according to desired gain.
FIGURE 8. Layout Detail For DEM-OPA65xP Demonstration Board.
®
11
OPA650
DEM-OPA65xP Demonstration Board Layout
(A)
(B)
(C)
(D)
FIGURE 9a. Evaluation Board Silkscreen (Bottom). 9b. Evaluation Board Silkscreen (Top). 9c. Evaluation Board Layout
(Solder Side). 9d. Evaluation Board Layout (Layout Side).
®
OPA650
12
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated
Similar pages