AD ADSP-2186BST-133 Dsp microcomputer Datasheet

a
FEATURES
PERFORMANCE
25 ns Instruction Cycle Time 40 MIPS Sustained
Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
DSP Microcomputer
ADSP-2186
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data
Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
ICE-Port is a trademark of Analog Devices, Inc.
All trademarks are the property of their respective holders.
PROGRAM
SEQUENCER
8K ⴛ 24
PROGRAM
MEMORY
8K ⴛ 16
DATA
MEMORY
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
40K Bytes of On-Chip RAM, Configured as
8K Words On-Chip Program Memory RAM and
8K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
MEMORY
MAC
SHIFTER
SERIAL PORTS
SPORT 0
ADSP-2100 BASE
ARCHITECTURE
SPORT 1
TIMER
INTERNAL
DMA
PORT
HOST MODE
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
GENERAL DESCRIPTION
The ADSP-2186 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2186 combines the ADSP-2100 family base architecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2186 integrates 40K bytes of on-chip memory configured as 8K words (24-bit) of program RAM and 8K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equipment. The ADSP-2186 is available in 100-lead LQFP and
144-Ball Mini-BGA packages.
In addition, the ADSP-2186 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking for increased flexibility.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADSP-2186
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2186 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2186’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple operations in parallel. In one processor cycle the ADSP-2186 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Target Board Connector for EZ-ICE Probe section
of this data sheet, for the exact specifications of the EZ-ICE
target board connector.
Additional Information
This data sheet provides a general overview of ADSP-2186
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-218x DSP
Hardware Reference. For more information about the development tools, refer to the ADSP-2100 Family Development Tools
Data Sheet.
Development System
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports the ADSP-2186. The System Builder provides a high level
method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instructionlevel simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. The
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2186 assembly source code.
The source code debugger allows programs to be corrected in
the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
ARCHITECTURE OVERVIEW
The ADSP-2186 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single
processor cycle. The ADSP-2186 assembly language uses an
algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.
POWER-DOWN
CONTROL
DATA ADDRESS
GENERATORS
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the ADSP-218x family: an ADSP218x-based evaluation board with PC monitor software plus
Assembler, Linker, Simulator and PROM Splitter software. The
ADSP-218x EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP
software design. The EZ-KIT Lite includes the following features:
•
•
•
•
•
•
DAG 1 DAG 2
MEMORY
PROGRAM
SEQUENCER
8K ⴛ 24
PROGRAM
MEMORY
8K ⴛ 16
DATA
MEMORY
FULL MEMORY
MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
75 MHz ADSP-2189M
Full 16-bit Stereo Audio I/O with AD73322 Codec
RS-232 Interface
EZ-ICE Connector for Emulator Control
DSP Demo Programs
Evaluation Suite of Visual DSP
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0
TIMER
SPORT 1
ADSP-2100 BASE
ARCHITECTURE
INTERNAL
DMA
PORT
HOST MODE
Figure 1. Block Diagram
Figure 1 is an overall block diagram of the ADSP-2186. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations.
The ADSP-218x EZ-ICE Emulator aids in the hardware debugging of an ADSP-2186 system. The emulator consists of hardware, host computer resident software, and the target board
connector. The ADSP-2186 integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer mechanical
clearance considerations than other ADSP-2100 Family EZICEs. The ADSP-2186 device need not be removed from the
target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector,
emulation can be supported in final board designs.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.
–2–
REV. B
ADSP-2186
serial interface with optional companding in hardware and a wide
variety of framed or frameless data transmit and receive modes of
operation.
The internal result (R) bus connects the computational units so
the output of any unit may be the input of any unit on the next
cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2186 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and program memory. Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2186 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2186 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2186 SPORTs.
For additional information on Serial Ports, refer to the ADSP-218x
DSP Hardware Reference.
• SPORTs are bidirectional and have a separate, double-buffered
transmit and receive section.
• SPORTs can use an external serial clock or generate their own
serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
Program memory can store both instructions and data, permitting the ADSP-2186 to fetch two operands in a single cycle, one
from program memory and one from data memory. The ADSP2186 can fetch an operand from program memory and the next
instruction in the same cycle.
• SPORTs support serial data word lengths from 3 to 16 bits and
provide optional A-law and µ-law companding according to
CCITT recommendation G.711.
When configured in host mode, the ADSP-2186 has a 16-bit
Internal DMA port (IDMA port) for connection to external
systems. The IDMA port is made up of 16 data/address pins and
five control pins. The IDMA port provides transparent, direct
access to the DSPs on-chip program and data RAM.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2186 to continue running from on-chip memory. Normal
execution mode requires the processor to halt while buses are
granted.
The ADSP-2186 can respond to eleven interrupts. There are up
to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port
and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
REV. B
• SPORT0 has a multichannel interface to selectively receive and
transmit a 24- or 32-word, time-division multiplexed, serial
bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONS
The ADSP-2186 is available in a 100-lead LQFP package and a
144-Ball Mini-BGA package. In order to maintain maximum
functionality and reduce package size and pin count, some serial
port, programmable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are configured
during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases
–3–
ADSP-2186
where pin functionality is reconfigurable, the default state is
shown in plain text; alternate functionality is shown in italics.
Memory Interface Pins
The ADSP-2186 processor can be used in one of two modes:
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running.
Common-Mode Pins
Pin
Name(s)
#
of
Pins
Input/
Output
Function
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
1
1
1
1
1
1
1
1
1
1
1
1
I
I
O
O
O
O
O
O
O
O
O
I
PF7
IRQL0/
PF5
IRQL1/
PF6
IRQE/
PF4
PF3
Mode C/
1
1
1
1
1
PF2
Mode B/
I/O
1
PF1
Mode A/
I
I/O
1
PF0
CLKIN, XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
FI, FO
PWD
PWDACK
FL0, FL1, FL2
VDD
GND
VDD
GND
EZ-Port
I/O
I
I/O
I
I/O
I
I/O
I/O
I
I
I/O
2
1
5
5
I
O
I/O
I/O
1
1
3
6
10
11
20
9
I
O
O
I
I
I
I
I/O
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive
Interrupt Request1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
Programmable I/O Pin
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
only During RESET
Programmable I/O Pin During
Normal Operation
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out2
Power-Down Control Input
Power-Down Control Output
Output Flags
Power (LQFP)
Ground (LQFP)
Power (Mini-BGA)
Ground (Mini-BGA)
For Emulation Use
Full Memory Mode Pins (Mode C = 0)
Pin Name
#
of
Pins
Input/
Output
A13:0
14
O
D23:0
24
I/O
Function
Address Output Pins for Program, Data, Byte and I/O Spaces
Data I/O Pins for Program,
Data, Byte and I/O Spaces
(8 MSBs Are Also Used as
Byte Memory Addresses)
Host Mode Pins (Mode C = 1)
Pin Name
#
of
Pins
Input/
Output
IAD15:0
A0
16
1
I/O
O
D23:8
16
I/O
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
I
I
I
I
O
Function
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data, or Byte Access
Data I/O Pins for Program,
Data Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS, and IOMS signals.
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
NOTES
1
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices or
set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
–4–
Pin
Name
I/O
3-State
(Z)
Reset
State
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
D6 or
IRD
D5 or
IAL
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z*
Caused
By
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
Unused
Configuration
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
REV. B
ADSP-2186
Pin Terminations (Continued)
Pin
Name
I/O
3-State
(Z)
Reset
State
Hi-Z*
Caused
By
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
I/O (Z)
I
I/O (Z)
Hi-Z
I
Hi-Z
BR, EBR
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
IRQL1/PF6
I/O (Z)
I
IRQL0/PF5
I/O (Z)
I
IRQE/PF4
I/O (Z)
I
SCLK0
I/O
I
RFS0
DR0
TFS0
DT0
SCLK1
I/O
I
I/O
O
I/O
I
I
O
O
I
RFS1/IRQ0
DR1/FI
TFS1/IRQ1
DT1/FO
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I/O
I
I/O
O
I
I
O
I
O
I
I
I
O
I
I
O
O
I
I
O
I
O
I
I
I
O
BR, EBR
EE
Setting Memory Mode
Unused
Configuration
Float
High (Inactive)
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
NOTES
*Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0
autobuffer control register.
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let them
float.
3. All bidirectional pins have three-stated outputs. When the pins are configured
as an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
REV. B
Memory Mode selection for the ADSP-2186 is made during
chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are passive and active.
Passive configuration involves the use of a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor’s
output driver. For minimum power consumption during
power-down, reconfigure PF2 to be an input, as the pull-up or
pull-down will hold the pin in a known state, and will not switch.
Active configuration involves the use of a three-stateable external driver connected to the Mode C pin. A driver’s output enable should be connected to the DSP’s RESET signal such that
it only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allowing full use of the PF2 pin as either an input or output.
To minimize power consumption during power-down, configure
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2186 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the
PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FI and FO, for a total of six external interrupts.
The ADSP-2186 also supports internal interrupts from the
timer, the byte DMA port, the two serial ports, software and the
power-down control circuit. The interrupt levels are internally
prioritized and individually maskable (except power-down and
RESET). The IRQ2, IRQ0 and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1
are level-sensitive and IRQE is edge-sensitive. The priorities and
vector addresses of all interrupts are shown in Table I.
Table I. Interrupt Priority and Interrupt Vector Addresses
Source Of Interrupt
Interrupt Vector Address (Hex)
Reset (or Power-Up with
PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
–5–
ADSP-2186
Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Interrupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize), and letting the oscillator run to allow 200 CLKIN
cycle start-up.
• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit.
The ADSP-2186 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The
power-down interrupt also can be used as a nonmaskable,
edge- sensitive interrupt.
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
• The RESET pin also can be used to terminate power-down.
The IFC register is a write-only register used to force and clear
interrupts.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
Idle
The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
When the ADSP-2186 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.
ENA INTS;
Slow Idle
DIS INTS;
The IDLE instruction is enhanced on the ADSP-2186 to let the
processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2186 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-2186 will remain in the
idle state for up to a maximum of n processor cycles (n = 16, 32,
64, or 128) before resuming normal operation.
Power-Down
The ADSP-2186 processor has a low power feature that lets the
processor enter a very low power dormant state through hardware or software control. Following is a brief list of power-down
features. Refer to the ADSP-218x DSP Hardware Reference,
“System Interface” chapter, for detailed information about the
power-down feature.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
• Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
200 CLKIN cycle recovery.
–6–
REV. B
ADSP-2186
SYSTEM INTERFACE
Clock Signals
Figure 2 shows typical basic system configurations with the
ADSP-2186, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
connect easily to slow peripheral devices. The ADSP-2186 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
The ADSP-2186 can be clocked by either a crystal or a TTLcompatible clock signal.
FULL MEMORY MODE
ADSP-2186
1/2x CLOCK
OR
CRYSTAL
14
CLKIN
XTAL
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
A13–0
ADDR13–0
D23–16
24
A0–A21
BYTE
MEMORY
D15–8
DATA
DATA23–0
A10–0
ADDR
D23–8
I/O SPACE
DATA (PERIPHERALS)
CS
IOMS
SPORT1
SERIAL
DEVICE
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
SERIAL
DEVICE
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2186 uses an input clock with a frequency equal to
half the instruction rate; a 20.00 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
CS
BMS
2048 LOCATIONS
A13–0
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-down
state. For additional information on this power-down feature,
refer to the ADSP-218x DSP Hardware Reference.
D23–0
ADDR
OVERLAY
MEMORY
DATA
TWO 8K
PM SEGMENTS
PMS
DMS
CMS
TWO 8K
DM SEGMENTS
BR
BG
BGH
PWD
PWDACK
Because the ADSP-2186 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 3. Capacitor values are dependent
on crystal type and should be specified by the crystal manufacturer.
A parallel-resonant, fundamental frequency, microprocessorgrade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and
disabled by the CLKODIS bit in the SPORT0 Autobuffer
Control Register.
HOST MEMORY MODE
ADSP-2186
1/2x CLOCK
OR
CRYSTAL
CLKIN
CLKIN
1
XTAL
CLKOUT
DSP
ADDR0
XTAL
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
16
DATA23–8
Reset
MODE C/PF2
MODE B/PF1
MODE A/PF0
SPORT1
SERIAL
DEVICE
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SERIAL
DEVICE
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
IDMA PORT
SYSTEM
INTERFACE
OR
␮CONTROLLER
16
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15–0
Figure 3. External Crystal Connections
BMS
IOMS
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
Figure 2. Basic System Configuration
The RESET signal initiates a master reset of the ADSP-2186.
The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
REV. B
–7–
ADSP-2186
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
There are 8K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to something other than 0, external accesses occur at addresses 0x2000
through 0x3FFF. The external address is generated as shown in
Table II.
Table II. PMOVLAY Addressing
MEMORY ARCHITECTURE
The ADSP-2186 provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory and I/O.
Program Memory (Full Memory Mode) is a 24-bit-wide space
for storing both instruction opcodes and data. The ADSP-2186
has 8K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces using
the external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.
PMOVLAY Memory
A13
A12:0
0
1
Reserved
External
Overlay 1
2
External
Overlay 2
Not Applicable Not Applicable
13 LSBs of Address
0
Between 0x2000
and 0x3FFF
13 LSBs of Address
1
Between 0x2000
and 0x3FFF
NOTE: Addresses 0x2000 through 0x3FFF should not be accessed when
PMOVLAY = 0.
This organization provides for two external 8K overlay segments
using only the normal 14 address bits, which allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space in that the processor core (i.e., the sequencer)
does not take into account the PMOVLAY register value. For
example, if a loop operation is occurring on one of the external
overlays and the program changes to another external overlay or
internal memory, an incorrect loop operation could occur. In
addition, care must be taken in interrupt service routines as the
overlay registers are not automatically saved and restored on the
processor mode stack.
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2186 has 8K words on Data
Memory RAM on chip, consisting of 8160 user-accessible
locations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus.
Byte Memory (Full Memory Mode) provides access to an
8-bit wide memory space through the Byte DMA (BDMA) port.
The Byte Memory interface provides access to 4 MBytes of
memory by utilizing eight data lines as additional address lines.
This gives the BDMA Port an effective 22-bit address range. On
power-up, the DSP can automatically load bootstrap code from
byte memory.
When Mode B = 1, booting is disabled and overlay memory is
disabled (PMOVLAY must be 0). Figure 5 shows the memory
map in this configuration.
I/O Space (Full Memory Mode) allows access to 2048 locations of 16-bit-wide data. It is intended to be used to communicate with parallel peripheral devices such as data converters and
external registers or latches.
PROGRAM MEMORY
ADDRESS
0x3FFF
RESERVED
Program Memory
0x2000
The ADSP-2186 contains an 8K × 24 on-chip program RAM.
The on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2186 allows the use of 8K
external memory overlays.
0x1FFF
8K EXTERNAL
0x0000
Figure 5. Program Memory (Mode B = 1)
The program memory space organization is controlled by the
Mode B pin and the PMOVLAY register. Normally, the ADSP2186 is configured with Mode B = 0 and program memory
organized as shown in Figure 4.
Data Memory
The ADSP-2186 has 8160 16-bit words of internal data memory.
In addition, the ADSP-2186 allows the use of 8K external memory
overlays. Figure 6 shows the organization of the data memory.
DATA MEMORY
PROGRAM MEMORY
ADDRESS
ADDRESS
0x3FFF
32 MEMORY–
MAPPED REGISTERS
0x3FFF
EXTERNAL 8K
(PMOVLAY = 1 or 2,
MODE B = 0)
0x3FEO
0x3FDF
INTERNAL
8160 WORDS
0x2000
0x2000
0x1FFF
0x1FFF
EXTERNAL 8K
(DMOVLAY = 1, 2)
8K INTERNAL
0x0000
0x0000
Figure 6. Data Memory
Figure 4. Program Memory (Mode B = 0)
–8–
REV. B
ADSP-2186
There are 8160 words of memory accessible internally when the
DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.
Table III. Addressing
The CMS pin functions as the other memory select signals, with
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.
Boot Memory Select (BMS) Disable
DMOVLAY Memory
A13
A12:0
0
1
Reserved
External
Overlay 1
2
External
Overlay 2
Not Applicable Not Applicable
13 LSBs of Address
0
Between 0x0000
and 0x1FFF
13 LSBs of Address
1
Between 0x0000
and 0x1FFF
The ADSP-2186 also lets you boot the processor from one
external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for BDMA
transfers and BMS to select the second external memory space
for booting. The BMS signal can be disabled by setting Bit 3 of
the System Control Register to 1. The System Control Register
is illustrated in Figure 7.
This organization allows for two external 8K overlays using only
the normal 14 address bits. All internal accesses complete in one
cycle. Accesses to external memory are timed using the wait states
specified by the DWAIT register.
Table IV.
Address Range
2
1
0
0
1
1
1
0
0
0
0
0
0
0
0
DM (0ⴛ3FFF)
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0 = ENABLED,
1 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO, IRQ0, IRQ1, SCLK
Figure 7. System Control Register
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 8. The byte memory space consists of 256 pages,
each of which is 16K × 8.
0
0
0
0
0
BMPAGE
0
BDMA CONTROL
9 8 7 6 5
0
0
0
0
0
4
3
2
1
0
0
1
0
0
0
RESERVED
SET TO ZERO
DM (0ⴛ3FE3)
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
Composite Memory Select (CMS)
REV. B
0
SPORT1 ENABLE
1 = ENABLED,
0 = DISABLED
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both program
and data memory, set the PMS and DMS bits in the CMSSEL
register and use the CMS pin to drive the chip select of the
memory and use either DMS or PMS as the additional address bit.
0
SPORT0 ENABLE
1 = ENABLED,
0 = DISABLED
Wait State Register
The ADSP-2186 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS), but can combine their
functionality.
0
RESERVED
SET TO ZERO
15 14 13 12 11 10
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
1
RESERVED
SET TO ZERO
I/O Space (Full Memory Mode)
The ADSP-2186 supports an additional external memory space
called I/O space. This space is designed to support simple connections to peripherals or to bus interface ASIC data registers.
I/O space supports 2048 locations. The lower eleven bits of the
external address bus are used; the upper three bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space. The
I/O space also has four dedicated three-bit wait state registers,
IOWAIT0-3, that specify up to seven wait states to be automatically generated for each of four regions. The wait states act on
address ranges as shown in Table IV.
SYSTEM CONTROL REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3
Figure 8. BDMA Control Register
The byte memory space on the ADSP-2186 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
–9–
ADSP-2186
Byte Memory DMA (BDMA, Full Memory Mode)
Internal Memory DMA Port (IDMA Port; Host Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2186. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memorymapped control registers.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses is done from the byte memory space to build
the word size selected. Table V shows the data formats supported
by the BDMA circuit.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written to while the ADSP-2186
is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
Table V. BDMA Data Formats
BTYPE
Internal
Memory Space
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address for
the on-chip memory involved with the transfer. The 14-bit BEAD
register specifies the starting address for the external byte memory
space. The 8-bit BMPAGE register specifies the starting page for
the external byte memory space. The BDIR register field selects
the direction of the transfer. The 14-bit BWCOUNT register
specifies the number of DSP words to transfer and initiates the
BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.
Once the address is stored, data can then either be read from or
written to the ADSP-2186’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2186 that a particular
transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automatically incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Bootstrap Loading (Booting)
The ADSP-2186 has two mechanisms to allow automatic loading of the internal program memory after reset. The method for
booting is controlled by the Mode A, B and C configuration bits
as shown in Table VI. These four states can be compressed into
two-state bits by allowing an IDMA boot with Mode C = 1.
However, three bits are used to ensure future compatibility with
parts containing internal program memory ROM.
BDMA Booting
When the MODE pins specify BDMA booting, the ADSP-2186
initiates a BDMA boot sequence when RESET is released.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
–10–
REV. B
ADSP-2186
Table VI. Boot Summary Table
Mode C
Mode B
Mode A
Booting Method
0
0
0
BDMA feature is used to load
the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words have
been loaded. Chip is configured in Full Memory Mode.
0
1
0
No Automatic boot operations
occur. Program execution
starts at external memory
location 0. Chip is configured
in Full Memory Mode.
BDMA can still be used but
the processor does not automatically use or wait for these
operations.
1
0
0
BDMA feature is used to load
the first 32 program memory
words from the byte memory
space. Program execution is
held off until all 32 words have
been loaded. Chip is configured in Host Mode. Additional
interface hardware is required.
1
0
1
IDMA feature is used to load
any internal memory as desired. Program execution is
held off until internal program
memory location 0 is written
to. Chip is configured in Host
Mode.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0; the BTYPE register is
set to 0 to specify program memory 24-bit words; and the
BWCOUNT register is set to 32. This causes 32 words of on-chip
program memory to be loaded from byte memory. These 32
words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor
to hold off execution while booting continues through the
BDMA interface. For BDMA accesses while in Host Mode, the
addresses to boot memory must be constructed externally to
the ADSP-2186. The only memory address bit provided by
the processor is A0.
REV. B
IDMA Port Booting
The ADSP-2186 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2186 boots from the IDMA port. The IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
Bus Request and Bus Grant
The ADSP-2186 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2186 is not performing an external memory access, it
responds to the active BR input in the following processor cycle by:
• Three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
• Asserting the bus grant (BG) signal, and
• Halting program execution.
If Go Mode is enabled, the ADSP-2186 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2186 is performing an external memory access
when the external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2186 is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2186 deasserts BG and BGH and executes the external
memory access.
Flag I/O Pins
The ADSP-2186 has eight general purpose programmable input/
output flag pins. They are controlled by two memory mapped
registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin
configured as an input is synchronized to the ADSP-2186’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2186 has five
fixed-mode flags, FI, FO, FL0, FL1 and FL2. FL0–FL2 are
dedicated output flags. FI and FO are available as an alternate configuration of SPORT1.
Note: Pins PF0, PF1 and PF2 are also used for device configuration during reset.
–11–
ADSP-2186
where addr is an address value between 0 and 2047 and dreg is
any of the 16 data registers.
BIASED ROUNDING
A mode is available on the ADSP-2186 to allow biased rounding in addition to the normal unbiased rounding. When the
BIASRND bit is set to 0, the normal unbiased rounding operations occur. When the BIASRND bit is set to 1, biased rounding
occurs instead of the normal unbiased rounding. When operating in biased rounding mode all rounding operations with MR0
set to 0x8000 will round up, rather than only rounding up odd
MR1 values.
Examples: IO(23) = AR0;
AR1 = IO(17);
Description: The I/O space read and write instructions move
data between the data registers and the I/O
memory space.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
For example:
The ADSP-2186 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
Table VII. Biased Rounding Example
MR Value
Before RND
Biased
RND Result
Unbiased
RND Result
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
Emulation Reset and the Mode Pins
The Mode A, B, and C pins are located on the rising edge of the
RESET signal. However, when the emulator reset (ERESET) is
asserted by the EZ-ICE, the DSP performs a chip reset, and the
initial mode information is erased, and the logic values on the
mode pins are latched. You must take into consideration the
value of the mode pins before issuing a chip reset command
from the EZ-ICE user interface. If you are using a passive
method of maintaining mode information (as discussed in Setting Memory Modes) then it does not matter that the mode
information is latched by an emulator reset. However, if you are
using the RESET pin as a method of setting the value of the
mode pins, then you have to take into consideration the effects
of an emulator reset.
This mode only has an effect when the MR0 register contains
0x8000; all other rounding operations work normally. This
mode allows more efficient implementation of bit-specified
algorithms that use biased rounding, for example the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note: BIASRND bit is Bit 12 of the SPORT0 Autobuffer
Control register.
INSTRUCTION SET DESCRIPTION
The ADSP-2186 assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability.
The assembly language, which takes full advantage of the
processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
• Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible
with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP2186’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
I/O Space Instructions
The instructions used to access the ADSP-2186’s I/O memory
space are as follows:
Syntax: IO(addr) = dreg
dreg = IO(addr);
One method of ensuring that the values located on the mode
pins is the one that is desired to construct a circuit like the one
shown in Figure 9. This circuit will force the value located on
the Mode C pin to zero; regardless if it latched via the RESET
or ERESET pin.
ERESET
RESET
ADSP-2186
1k⍀
MODE A/PFO
PROGRAMMABLE I/O
Figure 9. Boot Mode Circuit
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-2186
pins:
EBR
EMS
ELIN
–12–
EBG
EINT
ELOUT
ERESET
ECLK
EE
REV. B
ADSP-2186
These ADSP-2186 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pulldown resistors. The traces for these signals between the ADSP2186 and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE:
BR
RESET
BG
GND
The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2186 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of
the RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 10. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
1
2
3
4
GND
EBG
BR
5
6
7
ⴛ
8
9
10
11
12
EBR
KEY (NO PIN)
BG
EINT
ECLK
EE
PM, DM, BM, IOM, and CM
Design a Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
(CM) external interfaces to comply with worst case device timing
requirements and switching characteristics as specified in this
DSP’s data sheet. The performance of the EZ-ICE may approach
published worst case specifications for some memory access
timing requirements and switching characteristics.
Note: If your target does not meet the worst case chip specifications for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may have
trouble manufacturing your system as DSP components statistically vary in switching characteristics and timing requirements
within published limits.
Restriction: All memory strobe signals on the ADSP-2186 (RD,
WR, PMS, DMS, BMS, CMS and IOMS) used in your target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
EMS
• EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
ERESET
• EZ-ICE emulation ignores RESET and BR when singlestepping.
14
RESET
TOP VIEW
Figure 10. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.
REV. B
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed
below.
ELIN
ELOUT
13
Target Memory Interface
• EZ-ICE emulation ignores RESET and BR when in Emulator
Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
–13–
ADSP-2186–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade
B Grade
Parameter
Min
Max
Min
Max
Unit
VDD
TAMB
4.5
0
5.5
+70
4.5
–40
5.5
+85
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
1, 2
Hi-Level Input Voltage
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
IDD
Supply Current (Idle)9
Supply Current (Dynamic)10, 11
CI
Input Pin Capacitance3, 6
CO
Output Pin Capacitance6, 7, 12
Test Conditions
Min
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDDmax
@ VDD = max
VIN = 0 V
@ VDD = max
VIN = VDDmax8
@ VDD = max
VIN = 0 V8, tCK = 25 ns
@ VDD = 5.0
@ VDD = 5.0
TAMB = +25°C
tCK = 34.7 ns
tCK = 30 ns
tCK = 25 ns
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
@ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C
2.0
2.2
K/B Grades
Typ
Max
Unit
0.8
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
14
µA
mA
48
55
60
mA
mA
mA
8
pF
8
pF
NOTES
1
Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2
Input only pins: RESET, BR, DR0, DR1, PWD.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5
Although specified for TTL outputs, all ADSP-2186 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
8
0 V on BR, CLKIN Inactive.
9
Idle refers to ADSP-2186 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–14–
REV. B
ADSP-2186
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . 280°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2186 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TIMING PARAMETERS
GENERAL NOTES
MEMORY TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
The table below shows common memory device specifications
and the corresponding ADSP-2186 timing parameters, for your
convenience.
TIMING NOTES
Switching characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the processor operates correctly with other devices.
Memory
Device
Specification
ADSP-2186 Timing
Timing
Parameter
Parameter Definition
Address Setup to
Write Start
Address Setup to
Write End
Address Hold Time
tASW
tAW
Data Setup Time
tDW
tWRA
Data Hold Time
tDH
OE to Data Valid
tRDD
Address Access Time tAA
A0–A13, xMS Setup
before WR Low
A0–A13, xMS Setup
before WR Deasserted
A0–A13, xMS Hold before
WR Low
Data Setup before WR
High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data
Valid
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5 tCKI. The ADSP-2186 uses an input clock
with a frequency equal to half the instruction rate; for example,
a 20 MHz input clock (which is equivalent to 50 ns) yields a
25 ns processor cycle (equivalent to 40 MHz). tCK values within
the range of 0.5 tCKI period should be substituted for all relevant
timing parameters to obtain the specification value.
Example: tCKH = 0.5 tCK – 7 ns = 0.5 (25 ns) – 7 ns = 5.5 ns
REV. B
–15–
ADSP-2186
TIMING PARAMETERS
Parameter
Min
Max
Unit
Timing Requirements:
CLKIN Period
tCKI
CLKIN Width Low
tCKIL
tCKIH
CLKIN Width High
50
20
20
150
ns
ns
ns
Switching Characteristics:
CLKOUT Width Low
tCKL
tCKH
CLKOUT Width High
CLKIN High to CLKOUT High
tCKOH
0.5 tCK – 7
0.5 tCK – 7
0
Clock Signals and Reset
20
ns
ns
ns
Control Signals
Timing Requirements:
RESET Width Low1
tRSP
tMS
Mode Setup before RESET High
tMH
Mode Setup after RESET High
5 tCK
2
5
ns
ns
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(2:0)*
tMS
tMH
RESET
*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
tRSP
Figure 11. Clock Signals
–16–
REV. B
ADSP-2186
TIMING PARAMETERS
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements:
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
tIFS
tIFH
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
0.25 tCK + 15
0.25 tCK
Switching Characteristics:
Flag Output Hold after CLKOUT Low5
tFOH
tFOD
Flag Output Delay from CLKOUT Low5
ns
ns
0.25 tCK – 7
0.5 tCK + 5
ns
ns
NOTES
1
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference, for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, FO.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 12. Interrupts and Flags
REV. B
–17–
ADSP-2186
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
tBH
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
tBS
0.25 tCK + 2
0.25 tCK + 17
Switching Characteristics:
CLKOUT High to xMS, RD, WR Disable
tSD
tSDB
xMS, RD, WR Disable to BG Low
tSE
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
tSEC
tSDBH
xMS, RD, WR Disable to BGH Low2
tSEH
BGH High to xMS, RD, WR Enable2
0
0
0.25 tCK – 7
0
0
ns
ns
0.25 tCK + 10
ns
ns
ns
ns
ns
ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-218x DSP Hardware Reference, for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
tSD
tSEC
tSDB
tSE
tSDBH
tSEH
Figure 13. Bus Request–Bus Grant
–18–
REV. B
ADSP-2186
TIMING PARAMETERS
Parameter
Min
Max
Unit
0.5 tCK – 9 + w
0.75 tCK – 12.5 + w
ns
ns
ns
Memory Read
Timing Requirements:
RD Low to Data Valid
tRDD
tAA
A0–A13, xMS to Data Valid
Data Hold from RD High
tRDH
1
Switching Characteristics:
RD Pulsewidth
tRP
tCRD
CLKOUT High to RD Low
tASR
A0–A13, xMS Setup before RD Low
A0–A13, xMS Hold after RD Deasserted
tRDA
tRWR
RD High to RD or WR Low
0.5 tCK – 5 + w
0.25 tCK – 5
0.25 tCK – 6
0.25 tCK – 3
0.5 tCK – 5
0.25 tCK + 7
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D0–D23
tAA
tRDD
WR
Figure 14. Memory Read
REV. B
–19–
tRDH
ns
ns
ns
ns
ns
ADSP-2186
Parameter
Min
Max
Unit
Memory Write
Switching Characteristics:
Data Setup before WR High
tDW
tDH
Data Hold after WR High
WR Pulsewidth
tWP
tWDE
WR Low to Data Enabled
tASW
A0–A13, xMS Setup before WR Low
tDDR
Data Disable before WR or RD Low
tCWR
CLKOUT High to WR Low
A0–A13, xMS, Setup before WR Deasserted
tAW
tWRA
A0–A13, xMS Hold after WR Deasserted
tWWR
WR High to RD or WR Low
0.5 tCK – 7+ w
0.25 tCK – 2
0.5 tCK – 5 + w
0
0.25 tCK – 6
0.25 tCK – 7
0.25 tCK – 5
0.75 tCK – 9 + w
0.25 tCK – 3
0.5 tCK – 5
0.25 tCK + 7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
tDDR
D0–D23
tWDE
tDW
RD
Figure 15. Memory Write
–20–
REV. B
ADSP-2186
TIMING PARAMETERS
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
SCLK Period
tSCK
tSCS
DR/TFS/RFS Setup before SCLK Low
tSCH
DR/TFS/RFS Hold after SCLK Low
SCLKIN Width
tSCP
50
4
8
20
Switching Characteristics:
CLKOUT High to SCLKOUT
tCC
tSCDE
SCLK High to DT Enable
tSCDV
SCLK High to DT Valid
TFS/RFSOUT Hold after SCLK High
tRH
tRD
TFS/RFSOUT Delay from SCLK High
tSCDH
DT Hold after SCLK High
tTDE
TFS (Alt) to DT Enable
tTDV
TFS (Alt) to DT Valid
tSCDD
SCLK High to DT Disable
tRDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
0.25 tCK
0
15
15
0
0
14
15
15
tCC
tSCK
tSCP
tSCS
tSCP
tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFSOUT
ALTERNATE
FRAME MODE
tRDV
RFSOUT
TFSIN
tTDE
tTDV
ALTERNATE
FRAME MODE
tRDV
RFSIN
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 16. Serial Ports
REV. B
0.25 tCK + 10
0
SCLK
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
ns
ns
ns
ns
–21–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2186
Parameter
Min
Max
Unit
IDMA Address Latch
Timing Requirements:
Duration of Address Latch1, 2
tIALP
tIASU
IAD15–0 Address Setup before Address Latch End2
IAD15–0 Address Hold after Address Latch End2
tIAH
tIKA
IACK Low before Start of Address Latch1, 2
tIALS
Start of Write or Read after Address Latch End2, 3
10
5
3
0
3
ns
ns
ns
ns
ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
IAL
tIALP
IS
tIASU
tIAH
IAD15–0
tIALS
IRD OR
IWR
Figure 17. IDMA Address Latch
–22–
REV. B
ADSP-2186
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Write, Short Write Cycle
Timing Requirements:
IACK Low before Start of Write1
tIKW
tIWP
Duration of Write1, 2
tIDSU
IAD15–0 Data Setup before End of Write2, 3, 4
IAD15–0 Data Hold after End of Write2, 3, 4
tIDH
0
15
5
2
Switching Characteristics:
tIKHW
Start of Write to IACK High
15
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
IAD15–0
tIDH
DATA
Figure 18. IDMA Write, Short Write Cycle
REV. B
ns
ns
ns
ns
–23–
ns
ADSP-2186
Parameter
Min
Max
Unit
IDMA Write, Long Write Cycle
Timing Requirements:
IACK Low before Start of Write1
tIKW
tIKSU
IAD15–0 Data Setup before IACK Low2, 3, 4
IAD15–0 Data Hold after IACK Low2, 3, 4
tIKH
0
0.5 tCK + 10
2
Switching Characteristics:
Start of Write to IACK Low4
tIKLW
tIKHW
Start of Write to IACK High
ns
ns
ns
1.5 tCK
15
ns
ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-218x DSP Hardware Reference.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15–0
Figure 19. IDMA Write, Long Write Cycle
–24–
REV. B
ADSP-2186
TIMING PARAMETERS
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
IACK Low before Start of Read1
tIKR
tIRK
End Read after IACK Low2
0
2
Switching Characteristics:
IACK High after Start of Read1
tIKHR
tIKDS
IAD15–0 Data Setup before IACK Low
tIKDH
IAD15–0 Data Hold after End of Read2
tIKDD
IAD15–0 Data Disabled after End of Read2
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
IAD15–0 Previous Data Valid after Start of Read
tIRDV
tIRDH1
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
tIRDH2
IAD15–0 Previous Data Hold after Start of Read (PM2)4
ns
ns
15
0.5 tCK – 10
0
10
0
15
2 tCK – 5
tCK – 5
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDS
tIRDE
PREVIOUS
DATA
IAD15–0
tIKDH
READ
DATA
tIRDV
tIKDD
tIRDH
Figure 20. IDMA Read, Long Read Cycle
REV. B
–25–
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2186
Parameter
Min
Max
Unit
0
15
15
2 tCK – 5
tCK – 5
ns
ns
ns
IDMA Read, Short Read Cycle
Timing Requirements:
IACK Low before Start of Read1
tIKR
tIRP1
Duration of Read (DM, PM1)2
Duration of Read (PM2)3
tIRP2
Switching Characteristics:
IACK High after Start of Read1
tIKHR
tIKDH
IAD15–0 Data Hold after End of Read4
tIKDD
IAD15–0 Data Disabled after End of Read4
tIRDE
IAD15–0 Previous Data Enabled after Start of Read
tIRDV
IAD15–0 Previous Data Valid after Start of Read
15
0
10
0
15
ns
ns
ns
ns
ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
DM Read or First Half of PM Read.
3
Second Half of PM Read.
4
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
DATA
IAD15–0
tIRDV
tIKDD
Figure 21. IDMA Read, Short Read Cycle
–26–
REV. B
ADSP-2186
OUTPUT DRIVE CURRENTS
2186 POWER, INTERNAL1,2,3
500
60
VOH
5.5V, –40ⴗC
40
SOURCE CURRENT – mA
POWER (PINT) – mW
Figure 22 shows typical I-V characteristics for the output drivers
of the ADSP-2186. The curves represent the current drive
capability of the output drivers as a function of output voltage.
5.0V, +25ⴗC
20
400
385mW
VDD = 5.5V
330mW
300mW
300
250mW
200
VDD = 5.0V
180mW
225mW
VDD = 4.5V
100
4.5V, +85ⴗC
0
0
–20
33.33
40
1/tcyc – MHz
4.5V, +85ⴗC
–40
POWER, IDLE1,2,4
5.0V, +25ⴗC
–60
100
5.5V, –40ⴗC
80
VOL
0
1
2
3
4
SOURCE VOLTAGE – Volts
5
POWER (PIDLE) – mW
–80
6
Figure 22. Typical Drive Currents
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
60
40
VDD = 5.5V
91.5mW
VDD = 5.0V
70.5mW
VDD = 4.5V
52mW
82mW
62mW
45mW
20
C × VDD2 × f
0
33.33
40
1/tcyc – MHz
C = load capacitance, f = output switching frequency.
POWER, IDLE n MODES2
Example
80
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:
POWER (PIDLEn) – mW
70.5mW
Assumptions
• External data memory is accessed every cycle with 50% of the
address pins switching.
• External data memory writes occur every other cycle with
50% of the data pins switching.
60
IDLE
62mW
36.6mW
40
34.7mW
32.8mW
34.3mW
IDLE (16)
IDLE (128)
20
• Each address and data pin has a 10 pF total load at the pin.
• The application operates at VDD = 5.0 V and tCK = 30 ns.
0
33.33
Total Power Dissipation = PINT + (C × VDD2 × f)
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 23).
(C × VDD2 × f) is calculated for each output:
# of
Pins ⴛ C
Address
Data Output, WR
RD
CLKOUT, DMS
7
9
1
2
× 10 pF
× 10 pF
× 10 pF
× 10 pF
ⴛ VDD2
ⴛf
×5 V
× 52 V
× 52 V
× 52 V
× 20 MHz = 35 mW
× 20 MHz = 45 mW
× 20 MHz = 5 mW
× 40 MHz = 20 mW
105 mW
2
VALID FOR ALL TEMPERATURE GRADES.
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 TYPICAL POWER DISSIPATION AT 5.0V V
DD AND TA = +25ⴗC EXCEPT WHERE SPECIFIED.
3I
DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
REFERS TO ADSP-2186 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
4 IDLE
Figure 23. Power vs. Frequency
Total power dissipation for this example is PINT + 105 mW.
REV. B
40
1/tcyc – MHz
–27–
ADSP-2186
CAPACITIVE LOADING
Figures 24 and 25 show the capacitive loading characteristics of
the ADSP-2186.
is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop
driving.
30
25
RISE TIME (0.4V–2.4V) – ns
INPUT
OR
OUTPUT
T = +85 C
VDD = 4.5V
1.5V
1.5V
Figure 26. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
20
Output Enable Time
15
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
10
5
0
50
0
100
150
CL – pF
200
250
300
Figure 24. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
REFERENCE
SIGNAL
tMEASURED
tENA
18
VOH
(MEASURED)
VALID OUTPUT DELAY OR HOLD – ns
16
14
OUTPUT
12
10
VOH
(MEASURED)
tDIS
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) + 0.5V
1.0V
VOL
(MEASURED)
8
6
VOL
(MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
4
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
2
NOMINAL
Figure 27. Output Enable/Disable
–2
–4
IOL
–6
0
50
100
150
CL – pF
200
250
Figure 25. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
TO
OUTPUT
PIN
+1.5V
50pF
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the following equation:
tDECAY =
IOH
Figure 28. Equivalent Device Loading for AC Measurements (Including All Fixtures)
CL × 0.5V
iL
from which
tDIS = tMEASURED – tDECAY
–28–
REV. B
ADSP-2186
ENVIRONMENTAL CONDITIONS
10k
Ambient Temperature Rating:
=
=
=
=
=
=
TCASE – (PD x θCA)
Case Temperature in °C
Power Dissipation in W
Thermal Resistance (Case-to-Ambient)
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Package
␪JA
␪JC
␪CA
LQFP
Mini-BGA
50°C/W
70.7°C/W
2°C/W
7.4°C/W
48°C/W
63.3°C/W
VDD @ 5.6V
1k
VDD @ 5.0V
IDD – ␮A
TAMB
TCASE
PD
θCA
θJA
θJC
100
10
1
0
20
60
40
80
TEMPERATURE – ⴗC
100
Figure 29. Power-Down Supply Current
REV. B
–29–
120
ADSP-2186
77 D17
76 D16
78 D18
80 GND
79 D19
82 D21
81 D20
83 D22
84 D23
86 FL1
85 FL2
87 FL0
88 PF3
89 PF2 [MODE C]
90 VDD
92 GND
91 PWD
93 PF1 [MODE B]
94 PF0 [MODE A]
95 BGH
97 A0
96 PWDACK
98 A1/IAD0
100 A3/IAD2
99 A2/IAD1
100-Lead LQFP Package Pinout
A4/IAD3
1
A5/IAD4
2
GND
3
A6/IAD5
4
72 D12
A7/IAD6
5
71 GND
A8/IAD7
6
70 D11
A9/IAD8
7
69 D10
A10/IAD9
8
68 D9
A11/IAD10
9
67 VDD
A12/IAD11 10
66 GND
75 D15
PIN 1
IDENTIFIER
74 D14
73 D13
A13/IAD12 11
65 D8
GND 12
64 D7/IWR
ADSP-2186
CLKIN 13
63 D6/IRD
TOP VIEW
(Not to Scale)
XTAL 14
VDD 15
62 D5/IAL
61 D4/IS
60 GND
CLKOUT 16
GND 17
59 VDD
VDD 18
58 D3/IACK
WR 19
57 D2/IAD15
RD 20
56 D1/IAD14
BMS 21
55 D0/IAD13
DMS 22
54 BG
PMS 23
53 EBG
IOMS 24
52 BR
51 EBR
–30–
ELIN 49
EINT 50
ELOUT 48
EE 46
ECLK 47
EMS 45
SCLK1 42
ERESET 43
RESET 44
GND 41
RFS1/IRQ0 39
DR1/FI 40
TFS1/IRQ1 38
VDD 36
DT1/FO 37
DR0 34
SCLK0 35
DT0 31
TFS0 32
RFS0 33
IRQ2+PF7 30
GND 28
IRQL1+PF6 29
IRQE+PF4 26
IRQL0+PF5 27
CMS 25
REV. B
ADSP-2186
The ADSP-2186 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
LQFP Pin Configurations
LQFP
Number
Pin
Name
LQFP
Number
Pin
Name
LQFP
Number
Pin
Name
LQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
VDD
CLKOUT
GND
VDD
WR
RD
BMS
DMS
PMS
IOMS
CMS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IRQE + PF4
IRQL0 + PF5
GND
IRQL1 + PF6
IRQ2 + PF7
DT0
TFS0
RFS0
DR0
SCLK0
VDD
DT1/FO
TFS1/IRQ1
RFS1/IRQ0
DR1/FI
GND
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
EBR
BR
EBG
BG
D0/IAD13
D1/IAD14
D2/IAD15
D3/IACK
VDD
GND
D4/IS
D5/IAL
D6/IRD
D7/IWR
D8
GND
VDD
D9
D10
D11
GND
D12
D13
D14
D15
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3
PF2 [Mode C]
VDD
PWD
GND
PF1 [Mode B]
PF0 [Mode A]
BGH
PWDACK
A0
A1/IAD0
A2/IAD1
A3/IAD2
REV. B
–31–
ADSP-2186
ADSP-2186 Mini-BGA (CA) Package Pinout
Bottom View
12
11
10
9
8
7
6
5
4
3
2
GND
GND
D22
NC
NC
NC
GND
NC
A0
GND
A1/IAD0
A2/IAD1
A
D16
D17
D18
D20
D23
VDD
GND
NC
NC
GND
A3/IAD2
A4/IAD3
B
D14
NC
D15
D19
D21
VDD
PWD
A7/IAD6
A5/IAD4
RD
A6/IAD5
PWDACK
C
GND
NC
D12
D13
NC
D10
GND
VDD
GND
GND
PF3
D9
NC
D8
D11
D7/IWR
D4/ IS
NC
NC
D5/IAL
GND
NC
GND
VDD
VDD
EBG
PF2
PF1
[MODE C] [MODE B]
1
A9/IAD8
BGH
NC
WR
NC
D
FL2
PF0
[MODE A]
FL0
A8/IAD7
VDD
VDD
E
NC
NC
FL1
A11/
IAD10
A12/
IAD11
NC
A13/
IAD12
F
D6/IRD
NC
NC
NC
A10/IAD9
GND
NC
XTAL
G
D3/IACK
D2/IAD15
TFS0
DT0
VDD
GND
GND
GND
CLKIN
H
D1/IAD14
BG
RFS1/
IRQ0
D0/IAD13
SCLK0
VDD
VDD
NC
VDD
CLKOUT
J
BR
EBR
ERESET
SCLK1
TFS1/
IRQ1
RFS0
DMS
BMS
NC
NC
NC
K
EINT
ELOUT
ELIN
RESET
GND
DR0
PMS
GND
IOMS
IRQL1
+
PF6
NC
IRQE
+
PF4
L
ECLK
EE
EMS
NC
GND
DR1/FI
DT1/FO
GND
CMS
NC
IRQ2
+
PF7
IRQL0
+
PF5
M
–32–
REV. B
ADSP-2186
The ADSP-2186 Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals
enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
Mini-BGA Package Pinout
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
A01
A2/IAD1
D01
N/C
G01
XTAL
K01
N/C
A02
A1/IAD0
D02
WR
G02
N/C
K02
N/C
A03
GND
D03
N/C
G03
GND
K03
N/C
A04
A0
D04
BGH
G04
A10/IAD9
K04
BMS
A05
N/C
D05
A9/IAD8
G05
N/C
K05
DMS
A06
GND
D06
PF1[MODE B]
G06
N/C
K06
RFS0
A07
N/C
D07
PF2[MODE C]
G07
N/C
K07
TFS1/IRQ1
A08
N/C
D08
N/C
G08
D6/IRD
K08
SCLK1
A09
N/C
D09
D13
G09
D5/IAL
K09
ERESET
A10
D22
D10
D12
G10
N/C
K10
EBR
A11
GND
D11
N/C
G11
N/C
K11
BR
A12
GND
D12
GND
G12
D4/IS
K12
EBG
B01
A4/IAD3
E01
VDD
H01
CLKIN
L01
IRQE+PF4
B02
A3/IAD2
E02
VDD
H02
GND
L02
N/C
B03
GND
E03
A8/IAD7
H03
GND
L03
IRQL1+PF6
B04
N/C
E04
FL0
H04
GND
L04
IOMS
B05
N/C
E05
PF0[MODE A]
H05
VDD
L05
GND
B06
GND
E06
FL2
H06
DT0
L06
PMS
B07
VDD
E07
PF3
H07
TFS0
L07
DR0
B08
D23
E08
GND
H08
D2/IAD15
L08
GND
B09
D20
E09
GND
H09
D3/IACK
L09
RESET
B10
D18
E10
VDD
H10
GND
L10
ELIN
B11
D17
E11
GND
H11
N/C
L11
ELOUT
B12
D16
E12
D10
H12
GND
L12
EINT
C01
PWDACK
F01
A13/IAD12
J01
CLKOUT
M01
IRQL0+PF5
C02
A6/IAD5
F02
N/C
J02
VDD
M02
IRQ2+PF7
C03
RD
F03
A12/IAD11
J03
N/C
M03
N/C
C04
A5/IAD4
F04
A11/IAD10
J04
VDD
M04
CMS
C05
A7/IAD6
F05
FL1
J05
VDD
M05
GND
C06
PWD
F06
N/C
J06
SCLK0
M06
DT1/FO
C07
VDD
F07
N/C
J07
D0/IAD13
M07
DR1/FI
C08
D21
F08
D7/IWR
J08
RFS1/IRQ0
M08
GND
C09
D19
F09
D11
J09
BG
M09
N/C
C10
D15
F10
D8
J10
D1/IAD14
M10
EMS
C11
N/C
F11
N/C
J11
VDD
M11
EE
C12
D14
F12
D9
J12
VDD
M12
ECLK
REV. B
–33–
ADSP-2186
OUTLINE DIMENSIONS
Dimensions shown in millimeters.
100-Lead Metric Thin Plastic Quad Flatpack (LQFP)
(ST-100)
16.20
16.00 SQ
15.80
14.05
14.00 SQ
13.95
1.60 MAX
0.75
0.60 TYP
0.50
12ⴗ
TYP
100
1
76
75
SEATING
PLANE
12.00
BSC
TOP VIEW
(PINS DOWN)
0.08
MAX LEAD
COPLANARITY
10ⴗ
6ⴗ
2ⴗ
25
51
50
26
0.15
0.05
7ⴗ
0ⴗ
0.50 BSC
LEAD PITCH
0.27
0.22 TYP
0.17
LEAD WIDTH
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
–34–
REV. B
ADSP-2186
OUTLINE DIMENSIONS
Dimensions shown in millimeters.
144-Ball Mini-BGA
(CA-144)
10.10
10.00 SQ
9.90
10.10
10.00 SQ
9.90
TOP VIEW
12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
8.80
BSC
0.80
BSC
0.80 BSC
8.80 BSC
1.40
MAX
DETAIL A
DETAIL A
NOTES:
1. THE ACTUAL POSITION OF THE BALL
0.40
POPULATION IS WITHIN 0.150 OF ITS
0.25
IDEAL POSITION RELATIVE TO THE
PACKAGE EDGES.
2. THE ACTUAL POSITION OF EACH BALL
IS WITHIN 0.08 OF ITS IDEAL POSITION
RELATIVE TO THE BALL POPULATION.
1.00
0.85
0.55
0.12 SEATING
MAX PLANE
0.50
0.45
BALL DIAMETER
ORDERING GUIDE
Part Number
Ambient
Temperature
Range
Instruction
Rate
(MHz)
Package
Description
Package
Option*
ADSP-2186KST-115
ADSP-2186BST-115
ADSP-2186KST-133
ADSP-2186BST-133
ADSP-2186KST-160
ADSP-2186BST-160
ADSP-2186BCA-160
0°C to 70°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
28.8
28.8
33.3
33.3
40.0
40.0
40.0
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
100-Lead LQFP
144-Ball Mini-BGA
ST-100
ST-100
ST-100
ST-100
ST-100
ST-100
CA-144
*ST = Plastic Thin Quad Flatpack (LQFP); CA = Mini-BGA.
REV. B
–35–
–36–
PRINTED IN U.S.A.
C00190b–2.5–3/01(B)