MSC1200 MS C12 00 SBAS289E – JUNE 2003 – REVISED NOVEMBER 2004 Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with 8051 Microcontroller and Flash Memory FEATURES ANALOG FEATURES ● 24-BITS NO MISSING CODES ● 22-BITS EFFECTIVE RESOLUTION AT 10Hz Low Noise: 75nV ● PGA FROM 1 TO 128 ● PRECISION ON-CHIP VOLTAGE REFERENCE ● 8 DIFFERENTIAL/SINGLE-ENDED CHANNELS ● ON-CHIP OFFSET/GAIN CALIBRATION ● OFFSET DRIFT: 0.02ppm/°C ● GAIN DRIFT: 0.5ppm/°C ● ON-CHIP TEMPERATURE SENSOR ● SELECTABLE BUFFER INPUT ● BURNOUT DETECT ● 8-BIT CURRENT DAC DIGITAL FEATURES Microcontroller Core ● 8051-COMPATIBLE ● HIGH-SPEED CORE: 4 Clocks per Instruction Cycle ● DC TO 33MHz ● ON-CHIP OSCILLATOR ● PLL WITH 32kHz CAPABILITY ● SINGLE INSTRUCTION 121ns ● DUAL DATA POINTER Memory ● 4kB OR 8kB OF FLASH MEMORY ● FLASH MEMORY PARTITIONING ● ENDURANCE 1M ERASE/WRITE CYCLES, 100 YEAR DATA RETENTION ● 128 BYTES DATA SRAM ● IN-SYSTEM SERIALLY PROGRAMMABLE ● FLASH MEMORY SECURITY ● 1kB BOOT ROM Peripheral Features ● 16 DIGITAL I/O PINS ● ADDITIONAL 32-BIT ACCUMULATOR ● TWO 16-BIT TIMER/COUNTERS ● SYSTEM TIMERS ● PROGRAMMABLE WATCHDOG TIMER ● FULL DUPLEX USART ● BASIC SPI™ ● BASIC I2C™ ● POWER MANAGEMENT CONTROL ● INTERNAL CLOCK DIVIDER ● IDLE MODE CURRENT < 200µA ● STOP MODE CURRENT < 100nA ● DIGITAL BROWNOUT RESET ● ANALOG LOW VOLTAGE DETECT ● 20 INTERRUPT SOURCES GENERAL FEATURES ● PACKAGE: TQFP-48 ● LOW POWER: 3mW ● INDUSTRIAL TEMPERATURE RANGE: –40°C to +85°C ● POWER SUPPLY: 2.7V to 5.25V APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● INDUSTRIAL PROCESS CONTROL INSTRUMENTATION LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS INTELLIGENT SENSORS PORTABLE APPLICATIONS DAS SYSTEMS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2003-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com PACKAGE/ORDERING INFORMATION(1) PRODUCT FLASH MEMORY PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING MSC1200Y2 MSC1200Y2 MSC1200Y2 4k 4k TQFP-48 PFB –40°C to +85°C " " " " MSC1200Y3 MSC1200Y3 8k 8k TQFP-48 PFB –40°C to +85°C MSC1200Y3 " " " " NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our web site at www.ti.com/msc. ABSOLUTE MAXIMUM RATINGS(1) Analog Inputs Input Current ............................................................ 100mA, Momentary Input Current .............................................................. 10mA, Continuous Input Voltage ............................................. AGND – 0.3V to AVDD + 0.3V Power Supply DVDD to DGND ...................................................................... –0.3V to 6V AVDD to AGND ...................................................................... –0.3V to 6V AGND to DGND .............................................................. –0.3V to +0.3V VREF to AGND ....................................................... –0.3V to AVDD + 0.3V Digital Input Voltage to DGND .............................. –0.3V to DVDD + 0.3V Digital Output Voltage to DGND ........................... –0.3V to DVDD + 0.3V Maximum Junction Temperature ................................................ +150°C Operating Temperature Range ...................................... –40°C to +85°C Storage Temperature Range ....................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................ +235°C Package Power Dissipation ............................... (TJ Max – TAMBIENT)/θJA Output Current All Pins ................................................................ 200mA Output Pin Short Circuit ..................................................................... 10s Thermal Resistance, Junction-to-Ambient (θJA) ....................... 56.5°C/W Thermal Resistance, Junction-to-Case (θJC) ........................... 12.8°C/W Digital Outputs Output Current ......................................................... 100mA, Continuous I/O Source/Sink Current ............................................................... 100mA Power Pin Maximum .................................................................... 300mA NOTE: (1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. MSC1200Yx FAMILY FEATURES FEATURES(1) MSC1200Y2(2) MSC1200Y3(2) Up to 4k Up to 2k 128 Up to 8k Up to 4k 128 Flash Program Memory (Bytes) Flash Data Memory (Bytes) Internal Scratchpad RAM (Bytes) NOTES: (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents the onboard flash size = (2N)kBytes. ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise noted. MSC1200Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources CONDITION MIN Buffer OFF Buffer ON (In+) – (In–) Buffer OFF Buffer ON AGND – 0.1 AGND + 50mV –3dB –3dB –3dB User-Selectable Gain Ranges Buffer ON Multiplexer Channel Off, T = +25°C Buffer ON ADC OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift 2 TYP MAX UNITS AVDD + 0.1 AVDD – 1.5 ±VREF/PGA V V V MΩ nA 7/PGA 0.5 0.469 • fDATA 0.318 • fDATA 0.262 • fDATA 1 128 7 0.5 ±2 pF pA µA ±VREF/(2 • PGA) V Bits % of Range ppm/°C 8 ±1.0 0.6 MSC1200 www.ti.com SBAS289E ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise noted. MSC1200Yx PARAMETER CONDITION SYSTEM PERFORMANCE Resolution ENOB Output Noise No Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection MIN MAX 24 22 See Typical Characteristics Sinc3 Filter End Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration At DC fCM = 60Hz, fDATA = 10Hz fCM = 50Hz, fDATA = 50Hz fCM = 60Hz, fDATA = 60Hz fSIG = 50Hz, fDATA = 50Hz fSIG = 60Hz, fDATA = 60Hz At DC, dB = –20log(∆VOUT/∆VDD)(3) Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUTS Reference Input Range VREF Common-Mode Rejection Input Current REF IN+, REF IN– VREF ≡ (REF IN+) – (REF IN–) At DC VREF = 2.5V, PGA = 1 ON-CHIP VOLTAGE REFERENCE Output Voltage 24 ±0.0004 1.5 0.02 0.005 0.5 80 –50 100 AGND 0.3 VREFH = 1 at +25°C VREFH = 0 Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Startup Time from Power ON Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient Sink or Source T = +25°C IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage ANALOG POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current ADC Current IADC VREF Supply Current IDAC Supply Current TYP IVREF IIDAC AVDD Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON ADC ON IDAC = 00H 4.75 ±0.0015 120 50 120 130 120 120 100 100 100 2.5 115 1 AVDD(2) AVDD UNITS Bits Bits Bits %FSR ppm of FS ppm of FS/°C % ppm/°C % of FS % of FS dB dB dB dB dB dB dB V V dB µA 2.5 1.25 9 10 Indefinite 0.4 V V mA mA 115 375 mV µV/°C 1 Indefinite AVDD – 1.5 mA 5.0 <1 170 430 230 770 360 230 ms V 5.25 V nA µA µA µA µA µA µA NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain, turn buffer off. (3) DVOUT is change in digital result. MSC1200 SBAS289E www.ti.com 3 ELECTRICAL CHARACTERISTICS: AVDD = 3V All specifications from TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF ≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise noted. MSC1200Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources CONDITION MIN Buffer OFF Buffer ON (In+) – (In–) Buffer OFF Buffer ON AGND – 0.1 AGND + 50mV –3dB –3dB –3dB User-Selectable Gain Ranges Buffer On Multiplexer Channel Off, T = +25°C Buffer ON ADC OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift UNITS AVDD + 0.1 AVDD – 1.5 ±VREF/PGA V V V MΩ nA 7/PGA 0.5 0.469 • fDATA 0.318 • fDATA 0.262 • fDATA 1 128 7 0.5 ±2 pF pA µA ±VREF/(2 • PGA) V Bits % of Range ppm/°C ±1.5 0.6 24 Bits Bits 22 See Typical Characteristics Sinc3 Filter End Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration fCM = fCM = fCM = fSIG = fSIG = At DC, dB Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUTS Reference Input Range VREF Common-Mode Rejection Input Current At DC 60Hz, fDATA = 10Hz 50Hz, fDATA = 50Hz 60Hz, fDATA = 60Hz 50Hz, fDATA = 50Hz 60Hz, fDATA = 60Hz = –20log(DVOUT/DVDD)(3) REF IN+, REF IN– VREF ≡ (REF IN+) – (REF IN–) At DC VREF = 1.25V, PGA = 1 ON-CHIP VOLTAGE REFERENCE Output Voltage Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Startup Time from Power ON Temperature Sensor Temperature Sensor Voltage Temperature Sensor Coefficient 24 ±0.0004 1.3 0.02 0.005 0.5 80 –50 100 AGND 0.3 VREFH = 0 at +25°C Sink or Source T = +25°C IDAC OUTPUT CHARACTERISTICS Full-Scale Output Current Maximum Short-Circuit Current Duration Compliance Voltage VREF Supply Current IDAC Supply Current MAX 8 SYSTEM PERFORMANCE Resolution ENOB Output Noise No Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current ADC Current TYP IADC IVREF IIDAC AVDD Analog OFF, ALVD OFF, PDADC = PDIDAC = 1 PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON ADC ON IDAC = 00H 2.7 ±0.0015 120 50 130 130 120 120 100 100 88 1.25 110 0.5 AVDD(2) AVDD Bits %FSR ppm of FS ppm of FS/°C % ppm/°C % of FS % of FS dB dB dB dB dB dB dB V V dB µA 1.25 4 5 Indefinite 0.2 V mA µA 115 375 mV µV/°C 1 Indefinite AVDD – 1.5 mA 3.0 <1 150 380 200 610 330 220 ms V 3.6 V nA µA µA µA µA µA µA NOTES: (1) Calibration can minimize these errors. (2) The gain calibration cannot have a REF IN+ of more than AVDD – 1.5V with buffer ON. To calibrate gain, turn buffer off. (3) DVOUT is change in digital result. 4 MSC1200 www.ti.com SBAS289E DIGITAL CHARACTERISTICS: DVDD = 2.7V to 5.25V All specifications from TMIN to TMAX, unless otherwise specified. MSC1200Yx PARAMETER POWER-SUPPLY REQUIREMENTS Digital Supply Current DIGITAL INPUT/OUTPUT (CMOS) Logic Level: VIH (except XIN pin) VIL (except XIN pin) Ports 1 and 3, Input Leakage Current, Input Mode Pin XIN Input Leakage Current I/O Pin Hysteresis VOL, Ports 1 and 3, All Output Modes VOL, Ports 1 and 3, All Output Modes VOH, Ports 1 and 3, Strong Drive Output VOH, Ports 1 and 3, Strong Drive Output Ports 1 and 3 Pull-Up Resistors CONDITION MIN TYP MAX UNITS DVDD Normal Mode, fOSC = 1MHz Normal Mode, fOSC = 8MHz, All Peripherals ON Internal Oscillator LF Mode (12.8MHz nominal) Stop Mode, DBOR OFF 2.7 3.0 0.6 5 7.1 100 3.6 V mA mA mA nA DVDD Normal Mode, fOSC = 1MHz Normal Mode, fOSC = 8MHz, All Peripherals ON Internal Oscillator LF Mode (12.8MHz nominal) Internal Oscillator HF Mode (25.6MHz nominal) Stop Mode, DBOR OFF 4.75 5.0 1.2 9 15 29 100 5.25 V mA mA mA mA nA DVDD 0.2 • DVDD V V µA µA mV V V V V kΩ 0.6 • DVDD DGND VIH = DVDD or VIH = 0V IOL = 1mA IOL = 30mA, 3V (20mA) IOH = 1mA IOH = 30mA, 3V (20mA) 0 0 700 DGND DVDD – 0.4 0.4 1.5 DVDD – 0.1 DVDD – 1.5 11 DVDD FLASH MEMORY CHARACTERISTICS: DVDD = 2.7V to 5.25V tUSEC = 1µs, tMSEC = 1ms MSC1200Yx PARAMETER Flash Flash Mass Flash Memory Endurance Memory Data Retention and Page Erase Time Memory Write Time CONDITION MIN TYP 1,000,000 Set with FER Value in FTCON Set with FWR Value in FTCON 100,000 100 10 30 MSC1200 SBAS289E www.ti.com MAX UNITS 40 cycles Years ms µs 5 AC ELECTRICAL CHARACTERISTICS(1): DVDD = 2.7V to 5.25V MSC1200Yx PARAMETER CONDITION PHASE LOCK LOOP (PLL) Input Frequency Range PLL LF Mode PLL HF Mode PLL Lock Time MIN TYP External Crystal/Clock Frequency (fOSC) PLLDIV = 449 (default) PLLDIV = 899 (must be set by user) Within 1% INTERNAL OSCILLATOR (IO) IO LF Mode IO HF Mode Internal Oscillator Settling Time MAX UNITS 2 kHz MHz MHz ms 1 MHz MHz ms 32.768 14.7456 29.4912 See Typical Characteristics 12.8 25.6 Within 1% NOTE: (1) Parameters are valid over operating temperature range, unless otherwise specified. EXTERNAL CLOCK DRIVE CLK TIMING 2.7V to 3.6V SYMBOL MIN 4.75V to 5.25V FIGURE PARAMETER MAX MIN External Clock Mode fOSC(1) MAX UNITS A External Crystal Frequency (fOSC) 1 20 1 33 MHz 1/tOSC(1) A External Clock Frequency (fOSC) 0 20 0 33 MHz fOSC(1) A External Ceramic Resonator Frequency (fOSC) 1 12 1 12 MHz tHIGH A HIGH Time(2) 15 10 tLOW A LOW Time(2) 15 10 tR A Rise Time(2) 5 5 ns tF A Fall Time(2) 5 5 ns ns ns NOTES: (1) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (2) These values are characterized but not 100% production tested. tHIGH VIH VIH VIH 0.8V tF tR 0.8V tLOW VIH 0.8V 0.8V tOSC FIGURE A. External Clock Drive CLK. SERIAL FLASH PROGRAMMING TIMING SYMBOL FIGURE tRW B RST width PARAMETER MIN MAX 2 tOSC — tRRD B RST rise to P1.0 internal pull high tRFD B tRS B tRH B UNIT ns — 5 µs RST falling to CPU start — 18 ms Input signal to RST falling setup time tOSC — ns RST falling to P1.0 hold time 18 — ms tRW RST tRRD tRS tRFD, tRH P1.0/PROG NOTE: P1.0 is internally pulled-up with ~11kΩ during RST high. FIGURE B. Serial Flash Programming Power-On Timing. 6 MSC1200 www.ti.com SBAS289E PIN CONFIGURATION NC DVDD P3.7 P3.6/SCK/SCL/CLKS P3.5/T1 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TxD0 P3.0/RxD0 P1.7/INT5 TQFP DGND Top View 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 36 DVDD XIN 2 35 DVDD XOUT 3 34 DGND DGND 4 33 DGND RST 5 32 P1.6/INT4 NC 6 NC 7 30 P1.4/INT2/SS CAP 8 29 P1.3/DIN AVDD 9 28 P1.2/DOUT 31 P1.5/INT3 MSC1200 AGND 10 27 P1.1 AGND 11 26 P1.0/PROG AIN7 20 21 22 23 24 AIN0 NC 19 AIN1 REFIN– 18 AIN2 17 AIN3 16 AIN4 15 AIN5 14 AIN6 13 REFOUT/REFIN+ 25 NC IDAC AINCOM 12 MSC1200 SBAS289E www.ti.com 7 PIN DESCRIPTIONS PIN # NAME DESCRIPTION 1,6,7,16,25,47 NC No Connection 2 XIN The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. 3 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 4, 33, 34, 48 DGND 5 8 RST CAP 9 10, 11 12 AVDD AGND AINCOM 13 14 IDAC REFOUT/REF IN+ 15 REF IN– 17 AIN7 Analog Input Channel 7 18 AIN6 Analog Input Channel 6 19 AIN5 Analog Input Channel 5 20 AIN4 Analog Input Channel 4 21 AIN3 Analog Input Channel 3 22 AIN2 Analog Input Channel 2 23 AIN1 Analog Input Channel 1 24 AIN0 26-32, 37 P1.0-P1.7 Digital Ground A HIGH on the reset input for two tOSC periods will reset the device. Capacitor (220pF ceramic) Analog Power Supply Analog Ground Analog Input (can be analog common for single-ended inputs or analog input for differential inputs) IDAC Output Internal Voltage Reference Output/Voltage Reference Positive Input Voltage Reference Negative Input (tie to AGND for internal voltage reference) Analog Input Channel 0 Port 1 is a bidirectional I/O port (refer to P1DDRL, SFR AEH, and P1DDRH, SFR AFH, for port pin configuration control). Port 1—Alternate Functions: PORT ALTERNATE MODE P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 38-45 35, 36, 46 8 P3.0-P3.7 DVDD PROG N/A DOUT DIN INT2/SS INT3 INT4 INT5 Serial Programming Mode Serial Data Out Serial Data In External Interrupt External Interrupt External Interrupt External Interrupt 2/Slave Select 3 4 5 Port 3 is a bidirectional I/O port (refer to P3DDRL, SFR B3H, and P3DDRH, SFR B4H, for port pin configuration control). Port 3—Alternate Functions: PORT ALTERNATE P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RxD0 TxD0 INT0 INT1 T0 T1 SCK/SCL/CLKS N/A MODE Serial Port 0 Input Serial Port 0 Output External Interrupt 0 External Interrupt 1 Timer 0 External Input Timer 1 External Input SCK/SCL/Various Clocks (refer to PASEL, SFR F2H) Digital Power Supply MSC1200 www.ti.com SBAS289E TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 22 PGA2 PGA1 PGA4 PGA8 21 PGA1 PGA8 20 PGA32 PGA64 19 PGA128 ENOB (rms) ENOB (rms) EFFECTIVE NUMBER OF BITS vs DATA RATE 18 PGA16 17 PGA32 PGA64 16 15 14 Sinc3 Filter, Buffer OFF Sinc3 Filter, Buffer OFF 13 12 1 10 100 Data Rate (SPS) 1000 0 500 1000 1500 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA2 PGA1 PGA8 PGA4 21 PGA1 20 20 19 19 ENOB (rms) ENOB (rms) fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO PGA8 PGA4 PGA2 21 2000 fMOD Decimation Ratio = 18 17 PGA128 PGA64 PGA32 16 PGA16 15 18 17 PGA16 PGA32 PGA128 PGA64 16 15 14 14 Sinc3 Filter, Buffer ON 13 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF 13 12 12 0 500 1000 1500 Decimation Ratio = 2000 0 fMOD 500 1000 1500 Decimation Ratio = fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 2000 fMOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA2 21 PGA4 PGA2 PGA8 21 PGA1 20 20 19 19 ENOB (rms) ENOB (rms) PGA128 18 17 16 PGA16 15 PGA32 PGA128 PGA64 PGA4 18 17 PGA32 PGA16 PGA64 PGA128 16 15 14 14 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON 13 PGA8 PGA1 Sinc2 Filter 13 12 12 0 500 1000 Decimation Ratio = 1500 2000 fMOD 500 1000 Decimation Ratio = fDATA MSC1200 SBAS289E 0 www.ti.com 1500 2000 fMOD fDATA 9 TYPICAL CHARACTERISTICS (Cont.) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 25 22 21 fMOD = 203kHz 20 20 ENOB (rms) ENOB (rms) 19 18 17 16 fMOD = 15.6kHz fMOD = 110kHz 15 fMOD = 31.25kHz 10 15 14 5 Fast Settling Filter fMOD = 62.5kHz 13 0 12 0 500 1500 1000 Decimation Ratio = 1 2000 10 fMOD DEC = 500 Noise (rms, ppm of FS) ENOB (rms) DEC = 50 DEC = 255 DEC = 20 5 DEC = 10 100 1k Data Rate (SPS) 10k 0.6 0.5 0.4 0.3 0.2 0.1 0 0 –2.5 100k –0.5 0.5 INTEGRAL NONLINEARITY vs INPUT SIGNAL INTEGRAL NONLINEARITY vs INPUT SIGNAL 15 VREF = 2.5V 8 VREF = AVDD = 5V Buffer OFF 10 4 INL (ppm of FS) 6 INL (ppm of FS) –1.5 VIN (V) 10 –40°C +85°C 0 −2 −4 0 −5 −10 −8 −10 −2.5 −2.0 −1.5 −1.0 −0.5 5 +25°C −6 0 0.5 1.0 1.5 2.0 −15 VIN = −VREF 2.5 VIN (V) 10 2.5 0.7 10 2 1.5 NOISE vs INPUT SIGNAL 20 10 100k 0.8 DEC = 2020 15 10k fDATA EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION 25 100 1k Data Rate (SPS) 0 VIN = +VREF VIN (V) MSC1200 www.ti.com SBAS289E TYPICAL CHARACTERISTICS (Cont.) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. INL ERROR vs PGA ADC INTEGRAL NONLINEARITY vs VREF 30 50 VIN = VREF Buffer OFF 25 40 INL (ppm of FS) INL (ppm of FS) AVDD = 5V VREF = 2.5V 45 20 15 AVDD = 3V 10 AVDD = 5V 35 30 25 20 15 10 5 5 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 2 4 VREF (V) 64 128 AVDD = 5V, Buffer = ON 0.6 PGA = 128, ADC = ON VREF = ON, DBOR = ON ALVD = ON, IDAC = ON IADC (µA) Analog Supply Current (mA) 128 0.7 +25°C AVDD = 3V, Buffer = ON 0.5 AVDD = 5V, Buffer = OFF 0.4 1.1 –40°C 1.0 AVDD = 3V, Buffer = OFF 0.3 0.2 1.0 0.1 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 Analog Supply Voltage (V) 4 8 16 32 OFFSET DAC: OFFSET vs TEMPERATURE 4500 10 4000 8 6 Offset (ppm of FSR) 3500 3000 2500 2000 1500 1000 4 2 0 –2 –4 –6 –8 500 –10 0 –12 –2 –1.5 –1 –0.5 0 0.5 1 1.5 –40 2 +25 +85 Temperature (°C) ppm of FS MSC1200 SBAS289E 2 PGA Setting HISTOGRAM OF OUTPUT DATA Number of Occurrences 64 +85°C 1.2 0.9 32 0.8 1.3 1.1 16 ADC CURRENT vs PGA ANALOG SUPPLY CURRENT 1.3 1.2 8 PGA Setting www.ti.com 11 TYPICAL CHARACTERISTICS (Cont.) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. DIGITAL SUPPLY CURRENT vs FREQUENCY OFFSET DAC: GAIN vs TEMPERATURE 1.00006 100 Digital Supply Current (mA) Normalized Gain 1.00004 1.00002 1 0.99998 0.99996 0.99994 10 1 DVDD = 5V 0.1 –40 +25 +85 1 10 Temperature (°C) DIGITAL SUPPLY CURRENT vs CLOCK DIVIDER DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE 100 10 Digital Supply Current (mA) Digital Supply Current (mA) Divider Values 1 2 4 10 8 16 32 1 1024 0.1 +85°C 8 +25°C 6 –40°C 4 2 0 1 10 100 2.7 3.1 3.5 Clock Frequency (MHz) NORMALIZED GAIN vs PGA 4.3 4.7 5.1 CMOS DIGITAL OUTPUT 5.0 Buffer ON 4.5 100 5V Low Output 4.0 Output Voltage (V) Normalized Gain (%) 3.9 Supply Voltage (V) 101 99 98 97 3.5 3V Low Output 3.0 2.5 2.0 1.5 5V 1.0 96 0.5 95 3V 0 1 2 4 8 16 32 64 128 0 PGA Setting 12 100 Clock Frequency (MHz) 10 20 30 40 50 60 70 Output Current (mA) MSC1200 www.ti.com SBAS289E TYPICAL CHARACTERISTICS (Cont.) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fMOD = 15.625kHz, Bipolar, Buffer ON, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified. IO LF MODE vs TEMPERATURE IO HF MODE vs FREQUENCY 14 28 AVDD = DVDD 5.25V 27 13 IO Frequency (MHz) IO Frequency (MHz) AVDD = DVDD 3.3V 4.75V 12 2.7V 11 5.25V 26 4.75V 25 24 10 −40 23 25 85 Temperature (°C) 25 85 Temperature (°C) MSC1200 SBAS289E −40 www.ti.com 13 DESCRIPTION The MSC1200Yx allows the user to uniquely configure the Flash memory map to meet the needs of their application. The Flash is programmable down to 2.7V using serial programming. Flash endurance is typically 1M Erase/Write cycles. The MSC1200Yx is a completely integrated family of mixedsignal devices incorporating a high-resolution delta-sigma ADC, 8-bit IDAC, 8-channel multiplexer, burnout detect current sources, selectable buffered input, offset DAC, programmable gain amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 1. The part has separate analog and digital supplies, which can be independently powered from 2.7V to +5.25V. At +3V operation, the power dissipation for the part is typically less than 4mW. The MSC1200Yx is packaged in a TQFP-48 package. On-chip peripherals include an additional 32-bit accumulator, basic SPI, basic I2C, USART, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, brownout reset, timer/counters, system clock divider, PLL, on-chip oscillator, and external interrupts. The MSC1200Yx is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. ENHANCED 8051 CORE The device accepts low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits of resolution and 24 bits of no-missing-code performance using a Sinc3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolution single-cycle conversion. All instructions in the MSC1200 family perform exactly the same functions as they would in a standard 8051. The effect on bits, flags, and registers is the same. However, the timing is different. The MSC1200 family utilizes an efficient 8051 core which results in an improved instruction execution speed of between 1.5 and 3 times faster than the original core for the same external clock speed (4 clock cycles per instruction versus 12 clock cycles per instruction, as shown in Figure 2). This translates into an effective throughput improvement of more than 2.5 times, using the same code and same external clock speed. Therefore, a device frequency of 33MHz for the MSC1200Yx actually performs at an equivalent execution speed of 82.5MHz compared to the The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 core, given the same clock source. This makes it possible to run the device at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core. AVDD (1) AGND REFOUT/REFIN+ REFIN– DVDD DGND AVDD Burnout Detect VREF Temperature Sensor Timers/ Counters ALVD DBOR 8-Bit Offset DAC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM WDT Alternate Functions MUX BUFFER Digital Filter Modulator PGA 4K or 8K FLASH ACC 128 Bytes SRAM 8051 Burnout Detect SFR AGND POR 8-Bit IDAC IDAC PORT1 DIN DOUT SS EXT (4) PROG PORT3 USART EXT (2) T0 T1 SCK/SCL/CLKS On-Chip Oscillator System Clock Divider RST CAP PLL 220pF Ceramic XIN XOUT NOTE (1) REF IN− must be tied to AGND when using internal VREF. FIGURE 1. Block Diagram. CLK instr_cycle cpu_cycle n+1 C1 C2 n+2 C3 C4 C1 C2 C3 C4 C1 FIGURE 2. Instruction Cycle Timing. 14 MSC1200 www.ti.com SBAS289E The MSC1200 also provides dual data pointers (DPTRs). standard 8051 core. This allows the user to run the device at slower clock speeds, which reduces system noise and power consumption, but provides greater throughput. This performance difference can be seen in Figure 3. The timing of software loops will be faster with the MSC1200. However, the timer/counter operation of the MSC1200 may be maintained at 12 clocks per increment or optionally run at 4 clocks per increment. Furthermore, improvements were made to peripheral features that off-load processing from the core and the user, to further improve efficiency. For instance, a 32-bit accumulator was added to significantly reduce the processing overhead for the multiple byte data from the ADC or other sources. This allows for 24-bit addition and shifting to be accomplished in a few instruction cycles, compared to hundreds of instruction cycles through software implementation. MSC1200 Timing Single-Byte, Single-Cycle Instruction Family Device Compatibility The hardware functionality and pin configuration across the MSC1200 family is fully compatible. To the user, the only difference between family members is the memory configuration. This makes migration between family members simple. Code written for the MSC1200Y2 can be executed directly on an MSC1200Y3. This gives the user the ability to add or subtract software functions and to freely migrate between family members. Thus, the MSC1200 can become a standard device used across several application platforms. ALE PSEN Internal AD0-AD7 Internal A8-A15 4 Cycles CLK Standard 8051 Timing 12 Cycles Family Development Tools ALE The MSC1200 is fully compatible with the standard 8051 instruction set. This means that the user can develop software for the MSC1200 with existing 8051 development tools. Additionally, a complete, integrated development environment is provided with each demo board, and third-party developers also provide support. PSEN AD0-AD7 PORT 2 Power Down Modes Single-Byte, Single-Cycle Instruction The MSC1200 can power several of the peripherals and put the CPU into IDLE. This is accomplished by shutting off the clocks to those sections, as shown in Figure 4. FIGURE 3. Comparison of MSC1200 Timing to Standard 8051 Timing. tSYS SYSCLK C7 tCLK SCL/SCK SPICON/ I2CCON 9A PDCON.0 µs USEC Flash Write FTCON (30µs to 40µs) [3:0] EF Timing FB ms MSECH MSECL FC FD Flash Erase (5ms to 11ms) FTCON [7:4] EF Timing milliseconds interrupt MSINT FA PDCON.1 seconds interrupt SECINT F9 100ms HMSEC WDTCON FF FE watchdog PDCON.2 ACLK F6 divide by 64 ADCON2 DE ADC Output Rate Decimation Ratio ADC Power Down Modulator Clock PDCON.3 Timers 0/1 IDLE ADCON3 DF USART CPU Clock FIGURE 4. MSC1200 Timing Chain and Clock Control. MSC1200 SBAS289E www.ti.com 15 OVERVIEW The MSC1200 ADC structure is shown in Figure 5. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component. AVDD AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Burnout Detect REFIN+ fSAMP Input Multiplexer In+ Sample and Hold Buffer In− Σ PGA Temperature Sensor Burnout Detect D7H ADMUX REFIN+ fMOD Offset DAC REFIN− AGND DCH ADCON0 F6H ACLK E6H ODAC fDATA FAST VIN ∆Σ ADC Modulator SINC2 SINC3 AUTO REFIN− Σ X Offset Calibration Register Gain Calibration Register ADC Result Register Summation Block Σ DDH ADCON1 OCR GCR ADRES DEH ADCON2 D3H D2H D1H D6H D5H D4H DBH DAH D9H SUMR DFH ADCON3 E5H E4H E3H E2H E1H SSCON FIGURE 5. MSC1200 ADC Structure. 16 MSC1200 www.ti.com SBAS289E INPUT MULTIPLEXER BURNOUT DETECT The input multiplexer provides for any combination of differential inputs to be selected as the input channel, as shown in Figure 6. If AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels. It is also possible to switch the polarity of the differential input pair to negate any offset voltages. When the Burnout Detect (BOD) bit is set in the ADC control configuration register (ADCON0 DCH), two current sources are enabled. The current source on the positive input channel sources approximately 2µA of current. The current source on the negative input channel sinks approximately 2µA. This allows for the detection of an open circuit (full-scale reading) or short circuit (small differential reading) on the selected input differential pair. Enabling the buffer is recommended when BOD is enabled. INPUT BUFFER The analog input impedance is always high, regardless of PGA setting (when the buffer is enabled). With the buffer enabled, the input voltage range is reduced and the analog power-supply current is higher. If the limitation of input voltage range is acceptable, then the buffer is always preferred. AIN0 AIN1 AVDD The input impedance of the MSC1200 without the buffer is 7MΩ/PGA. The buffer is controlled by the state of the BUF bit in the ADC control register (ADCON0 DCH). Burnout Detect (2µA) AIN2 AIN3 ANALOG INPUT When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK F6H) and gain (PGA). The relationship is: In+ Buffer AIN4 In– 7MΩ 1MHz AIN Im pedance (Ω) = • ACLK Frequency PGA f CLK where ACLK frequency (fACLK) = ACLK + 1 f ACLK and fMOD = . 64 AIN5 AIN6 AGND Burnout Detect (2µA) Temperature Sensor AVDD AVDD AIN7 80 • I Figure 7 shows the basic input structure of the MSC1200. I AINCOM RSWITCH (3kΩ typical) High Impedance > 1GΩ AIN CS Sampling Frequency = fSAMP FIGURE 6. Input Multiplexer Configuration. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the pins. TEMPERATURE SENSOR On-chip diodes provide temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diodes are connected to the input of the ADC. All other channels are open. fSAMP fMOD 2 × fMOD 4 × fMOD 8 × fMOD 16 × fMOD AGND CS 1 2 4 to 128 9pF 18pF 36pF FIGURE 7. Analog Input Structure (without buffer). MSC1200 SBAS289E PGA 1, 2, 4 8 16 32 64, 128 PGA www.ti.com 17 PGA The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For instance, with a PGA of 1 on a ±2.5V fullscale range, the ADC can resolve to 1.5µV. With a PGA of 128 on a ±19mV full-scale range, the ADC can resolve to 75nV. With a PGA of 1 on a ±2.5V full-scale range, it would require a 26-bit ADC to resolve 75nV, as shown in Table I. PGA SETTING FULL-SCALE RANGE (V) ENOB AT 10Hz (BITS) RMS MEASUREMENT RESOLUTION (nV) 1 2 4 8 16 32 64 128 ±2.5 ±1.25 ±0.625 ±0.313 ±0.156 ±0.0781 ±0.039 ±0.019 21.7 21.5 21.4 21.2 20.8 20.4 20 19 1468 843 452 259 171 113 74.5 74.5 requires a positive full-scale differential input signal. It then computes a gain value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. Calibration should be performed after power on, a change in temperature, power supply, voltage reference, decimation ratio, buffer, or a change of the PGA. Calibration will remove the effects of the Offset DAC; therefore, changes to the Offset DAC register should be done after calibration. At the completion of calibration, the ADC Interrupt bit goes high, which indicates the calibration is finished and valid data is available. DIGITAL FILTER TABLE I. ENOB Versus PGA. OFFSET DAC The analog output from the PGA can be offset by up to half the full-scale input range of the PGA by using the ODAC register (SFR E6H). The ODAC (Offset DAC) register is an 8bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Since the ODAC introduces an analog (instead of digital) offset to the PGA, using the ODAC does not reduce the range of the ADC. The Digital Filter can use either the Fast Settling, Sinc2, or Sinc3 filter, as shown in Figure 8. In addition, the Auto mode changes the Sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the Fast Settling filter, for the next two conversions the first of which should be discarded. It will then use the Sinc2 followed by the Sinc3 filter to improve noise performance. This combines the low-noise advantage of the Sinc3 filter with the quick response of the Fast Settling Time filter. The frequency response of each filter is shown in Figure 9. Adjustable Digital Filter Sinc3 MODULATOR The modulator is a single-loop 2nd-order system. The modulator runs at a clock speed (fMOD) that is derived from the CLK using the value in the Analog Clock register (ACLK, F6H). The data output rate is: Data Rate = fDATA where fMOD = Modulator Data Out Fast Settling fMOD = Decimation Ratio fCLK f = ACLK (ACLK + 1) • 64 64 FILTER SETTLING TIME CALIBRATION The offset and gain errors in the MSC1200, or the complete system, can be reduced with calibration. Calibration is controlled through the ADCON1 register (SFR DDH), bits CAL2:CAL0. Each calibration process takes seven tDATA periods (data conversion time) to complete. Therefore, it takes 14 tDATA periods to complete both an offset and gain calibration. For system calibration, the appropriate signal must be applied to the inputs. The system offset calibration requires a zero-differential input signal. It then computes an offset value that will nullify offset in the system. The system gain calibration 18 Sinc2 FILTER SETTLING TIME (Conversion Cycles) Sinc3 Sinc2 Fast 3(1) 2(1) 1(1) NOTE: (1) With Synchronized Channel Changes. AUTO MODE FILTER SELECTION CONVERSION CYCLE 1 2 3 4+ Discard Fast Sinc2 Sinc3 FIGURE 8. Filter Step Responses. MSC1200 www.ti.com SBAS289E If the internal VREF is not used, then VREF should be disabled in ADCON0. SINC3 FILTER RESPONSE 0 (–3dB = 0.262 • fDATA) If the external voltage reference is selected it can be used as either a single-ended input of differential input, for ratiometric measures. When using an external reference, it is important to note that the input current will increase for VREF with higher PGA settings and with a higher modulator frequency. The external voltage reference can be used over the input range specified in the electrical characteristics section. –20 Gain (dB) –40 –60 –80 –100 IDAC –120 0 1 2 3 4 5 The 8-bit IDAC in the MSC1200 can be used to provide a current source that can be used for ratiometric measurements. The IDAC operates from its own voltage reference and is not dependent on the ADC voltage reference. The fullscale output current of the IDAC is approximately 1mA. The equation for the IDAC output current is: fDATA SINC2 FILTER RESPONSE 0 (–3dB = 0.318 • fDATA) –20 Gain (dB) –40 IDACOUT = IDAC • 3.6µA –60 RESET –80 Taking the RST pin HIGH will stop the operation of the device, and taking the RST pin LOW will initiate a reset. The device can also be reset by the power on reset circuitry, digital brownout Reset, or software reset. The timing of the reset operation is shown in the Electrical Characteristics section. –100 –120 0 1 2 3 4 5 fDATA FAST SETTLING FILTER RESPONSE 0 If the P1.0/PROG pin is unconnected or tied HIGH, the device will enter User Application mode on reset. If P1.0/ PROG is tied LOW during reset, the device will enter Serial Programming mode. (–3dB = 0.469 • fDATA) –20 Gain (dB) –40 –60 POWER ON RESET –80 –100 –120 0 1 2 3 4 5 fDATA NOTE: fDATA = Data Output Rate = 1/tDATA FIGURE 9. Filter Frequency Responses. VOLTAGE REFERENCE The MSC1200 can use either an internal or external voltage reference. The voltage reference selection is controlled via ADC Control Register 0 (ADCON0, SFR DCH). The default power-up configuration for the voltage reference is 2.5V internal. The internal voltage reference can be selected as either 1.25V or 2.5V. The analog power supply (AVDD) must be within the specified range for the selected internal voltage reference. The valid ranges are: VREF = 2.5 internal (AVDD = 4.1V to 5.25V) and VREF = 1.25 internal (AVDD = 2.7V to 5.25V). If the internal VREF is selected then AGND must be connected to REFIN–. The REFOUT/REFIN+ pin should also have a 0.1µF capacitor connected to AGND as close as possible to the pin. The on-chip Power On Reset (POR) circuitry releases the device from reset at approximately DVDD = 2.0V. The POR accommodates power-supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically. Note that, as the device is released from reset and program execution begins, the device current consumption may increase, which may result in a power-supply voltage drop. If the power supply ramps at a slower rate, is not monotonic, or a brownout condition occurs (where the supply does not drop below the 2.0V threshold), then improper device operation may occur. The on-chip Brownout Reset (BOR) may provide benefit in these conditions. A POR circuit is shown in Figure 10. DVDD MSC1200 0.1µF 10kΩ 1MΩ FIGURE 10. Typical Reset Circuit. MSC1200 SBAS289E 5 RST www.ti.com 19 DIGITAL BROWNOUT RESET POWER-UP—SUPPLY VOLTAGE RAMP RATE The Digital Brownout Reset (DBOR) is enabled through Hardware Configuration Register 1 (HCR1). If the conditions for proper POR are not met or the device encounters a brownout condition which does not generate a POR, DBOR can be used to ensure proper device operation. The DBOR will hold the state of the device when the power supply drops below the threshold level programmed in HCR1 and then generate a reset when the supply rises above the threshold level. Note that, as the device is released from reset and program execution begins, the device current consumption may increase, which can result in a power-supply voltage drop, which may initiate another brownout condition. Additionally, the DBOR comparison is done against an analog reference; therefore, AVDD must be within its valid operating range for DBOR to function. The built-in (on-chip) power-on reset circuitry was designed to accommodate analog or digital supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically at the specified rate. If DBOR is enabled, the ramp rate can be slower. CLOCKS The MSC1200 can operate in three separate clock modes: internal oscillator mode (IOM), external clock mode (ECM), and PLL mode. A block diagram is shown in Figure 11. The clock mode for the MSC1200 is selected via the CLKSEL bits in HCR2. IOM is the default mode for the device. Serial Flash Programming mode uses IO LF mode (the HCR2 and CLKSEL bits have no effect). Table II shows the active clock mode for the various startup conditions. The DBOR level should be chosen to match closely with the application. That is, with a high external clock frequency, the BOR level should match the minimum operating voltage range for the device, or improper operation may still occur. Internal Oscillator In IOM, the CPU executes either in LF mode (if HCR2, CLKSEL = 111) or HF mode (if HCR2, CLKSEL = 110). ANALOG LOW VOLTAGE DETECT External Clock The MSC1200 contains an analog low-voltage detect. When the analog supply drops below the value programmed in LVDCON (SFR E7H), an interrupt is generated. In ECM (HCR2, CLKSEL = 011), the CPU can execute from an external crystal, external ceramic resonator, external tOSC STOP XIN Phase Detector 100kΩ Charge Pump tPLL/tIOM tSYS VCO tCLK SYSDIV CAP(1) 220pF Ceramic Int Osc LF/HF Mode XOUT PLL DAC PLLDIV NOTE: (1) The trace length connecting the CAP pin to the 220pF ceramic capacitor should be as short as possible. FIGURE 11. Clock Block Diagram. SELECTED CLOCK MODE (HCR2, CLKCON2:0) STARTUP CONDITION(1) ACTIVE CLOCK MODE (fSYS) Active Clock Present at XIN No Clock Present at XIN External Clock Mode IO LF Mode N/A N/A IO LF Mode IO HF Mode Active 32.768kHz Clock at XIN No Clock Present at XIN PLL LF Mode Nominal: 50% of IO LF Mode Rate Active 32.768kHz Clock at XIN No Clock Present at XIN PLL HF Mode Nominal: 50% of IO HF Mode Rate External Clock Mode (ECM) Internal Oscillator Mode (IOM) IO LF Mode IO HF Mode PLL(2) PLL LF Mode PLL HF Mode NOTES: (1) Clock detection is only done at startup; refer to Electrical Characteristics parameter tRFD in Figure B. (2) PLL operation requires that both AVDD and DVDD are within their specified operating range. TABLE II. Active Clock Modes. 20 MSC1200 www.ti.com SBAS289E clock, or external oscillator. If an external clock is detected at startup, then the CPU will begin execution in ECM after startup. If an external clock is not detected at startup, then the device will revert to the mode shown in Table II. XIN C1 PLL XOUT C2 In Phase Lock Loop (PLL) mode (HCR2, CLKSEL = 101 or HCR2, CLKSEL = 100), the CPU can execute from an external 32.768 kHz crystal. This mode enables the use of a phase-lock loop (PLL) circuit that synthesizes the selected clock frequencies (PLL LF mode or PLL HF mode). If an external clock is detected at startup, then the CPU will begin execution in PLL mode after startup. If an external clock is not detected at startup, then the device will revert to the mode shown in Table II. The status of the PLL can be determined by first writing the PLLLOCK bit (enable) and then reading the PLLLOCK status bit in the PLLH SFR. NOTE: Refer to the crystal manufacturer's specification for C1 and C2 values. FIGURE 12. External Crystal Connection. The frequency of the PLL is preloaded with default trimmed values. However, the PLL frequency can be fine-tuned by writing to the PLLDIV1 and PLLDIV0 SFRs. The equation for the PLL frequency is: External Clock PLL Frequency = ((PLLDIV9:PLLDIV0) + 1) • fOSC XIN FIGURE 13. External Clock Connection. where fOSC = 32.768kHz. The default value for PLL LF mode is automatically loaded into the PLLDIV SFR. For PLL HF mode, the user must load PLLDIV with the appropriate value (0383H). XIN C1 For different connections to external clocks, see Figures 12, 13, and 14. 32.768kHz RS XOUT SPI C2 The MSC1200 implements a basic SPI interface which includes the hardware for simple serial data transfers. Figure 15 shows a block digram of the SPI. The peripheral supports master and slave mode, full duplex data transfers, both clock polarities, both clock phases, bit order, and slave select. NOTE: Typical configuration is shown. FIGURE 14. PLL Connection. DOUT SPI /I2C Data Write P1.2 DOUT TX_CLK SPICON I2CCON CNT INT Counter I2C INT Start/Stop Detect SS P1.4 CNT_CLK SS Logic SCK/SCL Pad Control P3.6 SCK I2C Stretch Control P1.3 RX_CLK DIN SPI /I2C Data Read DIN CLKS (refer to PASEL, SFR F2H) FIGURE 15. SPI/I2C Block Diagram. MSC1200 SBAS289E www.ti.com 21 The SS pin can be used to control the output of data on DOUT when the MSC1200 is in slave mode. The SS function is enabled or disabled by the ESS bit of the SPICON SFR. When enabled, the SS input of a slave device must be externally asserted before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. When SS is high then data will not be shifted into the shift register nor will the counter increment. When SPI is enabled, SS also controls the drive of the line DOUT (P1.2). When SS is low in slave mode, the DOUT pin will be driven and when SS is high then DOUT will be high impedance. The timing diagram for supported SPI data transfers is shown in Figure 16. The I/O pins needed for data transfer are Data In (DIN), Data Out (DOUT) and serial clock (SCK). The slave select (SS) pin can also be used to control the output of data on DOUT. The DIN pin is used for shifting data in for both master and slave modes. The DOUT pin is used for shifting data out for both master and slave modes. The SCK pin is used to synchronize the transfer of data for both master and slave modes. SCK is always generated by the master. The generation of SCK in master mode can be done in SW by simply toggling the port pin, or the generation of SCK can be accomplished by configuring the output on the SCK pin via PASEL (SFR F2H). A list of the most common methods of generating SCK follows, but the complete list of clock sources can be found by referring to the PASEL SFR. The SPI generates an interrupt ECNT (AIE.2) to indicate that the transfer/reception of the byte is complete. The interrupt goes high whenever the counter value is equal to 8 (indicating that 8 SCKs have occurred). The interrupt is cleared on reading or writing to the SPIDATA register. During the data transfer, the actual counter value can be read from the SPICON SFR. • Toggle SCK by setting and clearing the port pin. Power Down • Memory Write Pulse (WR) which is idle high. Whenever a external memory write command (MOVX) is executed then a pulse is seen on P3.6. This method can be used only if CPOL is set to ‘1’. The SPI is powered down by the PDSPI bit in the power control register (PDCON). This bit needs to be cleared to enable the SPI function. When the SPI is powered down the pins P1.2, P1.3, P1.4, and P3.6 revert to general-purpose I/O pins. • Memory Write Pulse toggle version: In this mode, SCK toggles whenever an external write command (MOVX) is executed. Application Flow • T0_Out signal can be used as a clock. A pulse is generated on SCK whenever Timer 0 expires. The idle state of the signal is low, so this can be used only if CPOL is cleared to ‘0’. Explained below are the steps of the typical application usage flow of SPI in master and slave mode: Master Mode Application Flow 1. Configure the port pins. • T0_Out Toggle: SCK toggles whenever Timer 0 expires. 2. Configure the SPI. • T1_Out signal can be used as a clock. A pulse is generated whenever Timer 1 expires. The idle state of the signal is low, so this can be used only if CPOL is cleared to ‘0’. 3. Assert SS to enable slave communications (if applicable). 4. Write data to SPIDATA. • T1_Out Toggle: SCK toggles whenever Timer 1 expires. 5. Generate 8 SCKs. 6. Read the received data from SPIDATA. SCK Cycle # 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) Sample Input MSB 6 5 4 3 2 1 LSB (CPHA = 0) Data Out Sample Input MSB 6 5 4 3 2 1 LSB (CPHA = 1) Data Out SS to Slave Slave CPHA = 1 Transfer in Progress 2 1) SS Asserted 1 2) First SCK Edge 3) CNTIF Set (dependent on CPHA bit) 4) SS Negated Slave CPHA = 0 Transfer in Progress 3 4 FIGURE 16. SPI Timing Diagram. 22 MSC1200 www.ti.com SBAS289E Slave Mode Application Flow 1. Configure the ports pins. 2. Enable SS (if applicable). 3. Configure the SPI. 4. Write data to SPIDATA. 5. Wait for the Count Interrupt (8 SCKs). 6. Read the data from SPIDATA. Caution: If SPIDATA is not read before the next SPI transaction the ECNT interrupt will be removed and the previous data will be lost. transferred. I2C mode also allows for interrupt generation on one bit of data transfer (I2CCON.CNTSEL). This can be used for ACK/NACK interrupt generation. For instance, the I2C interrupt can be configured for 8-bit interrupt detection, on the eighth bit the interrupt is generated. Following this interrupt, the clock will be stretched (SCL held low). The interrupt can then be configured for 1-bit detection. The ACK/NACK can be written by the software, which will terminate clock stretching. The next interrupt will be generated after the ACK/NACK has been latched by the receiving device. The interrupt is cleared on reading or writing to the I2CDATA register. If I2CDATA is not read before the next data transfer, the interrupt will be removed and the previous data will be lost. I2C Master Operation The I/O pins needed for I2C transfer are: serial clock (SCL) and serial data (SDA—implemented by connecting DIN and DOUT externally). The source for the SCL is controlled in the PASEL register or can be generated in software. The MSC1200 I2C supports: 1) Master or slave I2C operation (control in software) 2) Standard or fast modes of transfer 3) Clock stretching 4) General call When used in I2C mode, pins DIN (P1.3) and DOUT (P1.2) should be tied together externally. The DIN pin should be configured as an input pin and the DOUT pin should be configured as open drain or standard 8051 by setting the P1DDR (DOUT should be set high so that the bus is not pulled low). Transmit The serial data must be stable on the bus while SCL is high. Therefore, the writing of serial data to I2CDATA must be coordinated with the generation of the SCL, since SDA transitions on the bus may be interpreted as a START or STOP while SCL is high. The START and STOP conditions on the bus must be generated in software. After the serial data has been transmitted, the generation of the ACK/NACK clock must be enabled by writing 0xFFH to I2CDATA. This allows the master to read the state of ACK/NACK. Receive The serial data is latched into the receive buffer on the rising edge of SCL. After the serial data has been received, ACK/NACK is generated by writing 0x7FH (for ACK) or 0xFFH (for NACK) to I2CDATA. The MSC1200 I2C can generate two interrupts: 1) I2C interrupt for START/STOP interrupt (AIE.3) 2) CNT interrupt for bit counter interrupt (AIE.2) The START/STOP interrupt is generated when a START condition or STOP condition is detected on the bus. The bit counter generates an interrupt on a complete (8-bit) data transfer and also after the transfer of the ACK/NACK. The bit counter for serial transfer is always incremented on the falling edge of SCL and can be reset by reading or writing to I2CDATA (SFR 9BH) or when a START/STOP condition is detected. The bit counter can be polled or used as an interrupt. The bit counter interrupt occurs when the bit counter value is equal to 8, indicating that eight bits of data have been Slave Operation Slave operation is supported, but address recognition, R/W determination, and ACK/NACK must be done under software control. Transmit Once address recognition, R/W determination, and ACK/NACK are complete, the serial data to be transferred can be written to I2CDATA. The data is automatically shifted out based on the master SCL. After data transmission, SDA 1-7 SCL 8 9 1-7 8 9 1-7 8 9 S P START ADDRESS(2) Condition(1) R/W(2) ACK(3) DATA(2) ACK(3) DATA(2) ACK(3) STOP Condition(4) NOTES: (1) Generate in software; write 0x7F to I2CDATA. (2) I2CDATA register. (3) Generate in software. Can enable bit count = 1 interrupt prior to ACK/NACK for interrupt use. Generate ACK by writing 0x7F to I2CDATA; generate NACK by writing 0xFF to I2CDATA. (4) Generate in software; write 0xFF to I2CDATA. FIGURE 17. Timing Diagram for I2C Transmission and Reception. MSC1200 SBAS289E www.ti.com 23 CNTIF is generated and SCL is stretched by the MSC1200 until the I2CDATA register is written with a 0xFFH. The ACK/NACK from the master can then be read. Receive Once address recognition, R/W determination, and ACK/NACK are complete, I2CDATA must be written with 0xFFH to enable data reception. Upon completion of the data shift, the MSC1200 generates the CNT interrupt and stretches SCL. Received data can then be read from I2CDATA. After the serial data has been received, ACK/NACK is generated by writing 0x7FH (for ACK) or 0xFFH (for NACK) to I2CDATA. The write to I2CDATA clears the CNT interrupt and clock stretch. MEMORY MAP The MSC1200 contains on-chip SFR, Flash Memory, Scratchpad RAM Memory, and Boot ROM. The SFR registers are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1200 are controlled through the SFR. Reading from undefined SFR will return zero; writing to undefined SFR registers is not recommended and may have indeterminate effects. Flash Memory is used for both Program Memory and Data Memory. The user has the ability to select the partition size of Program and Data Memories. The partition size is set through hardware configuration bits, which are programmed through serial programming. Both Program and Data Flash Memories are erasable and writable (programmable) in user application mode. However, program execution can only occur from Program Memory. As an added precaution, a lock feature can be activated through the hardware configuration bits, which disables erase and writes to the first 4kB of Program Flash Memory or the entire Program Flash Memory in user application mode. FLASH MEMORY The MSC1200 uses a memory addressing scheme that separates Program Memory from Data Memory. The program and data segments can overlap since they are accessed by different instructions. Program Memory is fetched by the microcontroller automatically. There is one instruction (MOVC) that is used to explicitly read the program area. This is commonly used to read lookup tables. The MSC1200 has three Hardware (HW) Configuration registers (HCR0, HCR1, and HCR2) that are programmable only during Flash Memory Programming mode. The MSC1200 allows the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1200Y3 contains 8kB of Flash Memory on-chip. Through the HW configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Tables III and IV and Figure 18. The MSC1200 family offers two memory configurations. HCR0 Select in HCR0 MSC1200Y3 PM DM PM DM 00 2kB 2kB 4kB 4kB 01 2kB 2kB 6kB 2kB 10 3kB 1kB 7kB 1kB 11 (default) 4kB 0kB 8kB 0kB TABLE III. MSC1200Y Flash Partitioning. HCR0 DFSEL MSC1200Y2 MSC1200Y3 PM DM PM DM 0000-07FF 0400-0BFF 0000-0FFF 0400-13FF 01 0000-07FF 0400-0BFF 0000-17FF 0400-0BFF 10 0000-0BFF 0400-07FF 0000-1BFF 0400-07FF 11 (default) 0000-0FFF 0000 0000-1FFF 0000 00 TABLE IV. Flash Memory Partitioning Addresses. Program Memory Unused MSC1200Y2 DFSEL Data Memory FFFFH FFFFH FC00H 1K Internal Boot ROM F800H Unused Unused On 2000H, 8k (Y3) -Ch ip F lash 1400H, 5k (Y3) On-C h 1000H, 4k (Y2) ip Fla 0000H, 0k sh 0C00H, 3k (Y2) 0400H, 1k FIGURE 18. Memory Map. 24 MSC1200 www.ti.com SBAS289E The effect of memory mapping on Program and Data Memory is straightforward. The Program Memory is decreased in size from the top of Flash Memory. To maintain compatibility with the MSC121x, the Flash Data Memory maps to addresses 0400H. Therefore, access to Data Memory (through MOVX) will access Flash Memory for the addresses shown in Table IV. SFRs are accessed directly between 80H and FFH (128 to 255). Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data contents are small. Within the 128 bytes of RAM, there are several special-purpose areas. Bit Addressable Locations In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM and SFR area. In the Scratchpad RAM area, registers 20H to 2FH are bit addressable. This provides 128 (16 • 8) individual bits available to software. A bit access is distinguished from a full-register access by the type of instruction. In the SFR area, any register location ending in a 0H or 8H is bit addressable. Figure 20 shows details of the on-chip RAM addressing including the locations of individual RAM bits. 7FH Direct RAM Data Memory 2FH The MSC1200 has on-chip Flash Data Memory, which is readable and writable (depending on Memory Write Select register) during normal operation (full VDD range). This memory is mapped into the external Data Memory space, which requires the use of the MOVX instruction to program. Note that the page size is 64 bytes for both Program and Data Memory and the page must be erased before it can be written. 7F 7E 7D 7C 7B 7A 79 78 2EH 77 76 75 74 73 72 71 70 2DH 6F 6E 6D 6C 6B 6A 69 68 2CH 67 66 65 64 63 62 61 60 2BH 5F 5E 5D 5C 5B 5A 59 58 2AH 57 56 55 54 53 52 51 50 29H 4F 4E 4D 4C 4B 4A 49 48 28H 47 46 45 44 43 42 41 40 REGISTER MAP 27H 3F 3E 3D 3C 3B 3A 39 38 The Register Map is illustrated in Figure 19. It is entirely separate from the Program and Data Memory areas mentioned before. A separate class of instructions is used to access the registers. There are 128 register locations. In practice, the MSC1200 has 128 bytes of Scratchpad RAM and up to 128 SFRs. Thus, a direct reference to one of the upper 128 locations will be an SFR access. Direct RAM is reached at locations 0 to 7FH (0 to 127). 26H 37 36 35 34 33 32 31 30 25H 2F 2E 2D 2C 2B 2A 29 28 24H 27 26 25 24 23 22 21 20 23H 1F 1E 1D 1C 1B 1A 19 18 22H 17 16 15 14 13 12 11 10 21H 0F 0E 0D 0C 0B 0A 09 08 20H 07 06 05 04 03 02 01 00 Bit Addressable It is important to note that the Flash Memory is readable and writable (depending on the MXWS bit in the MWS SFR) by the user through the MOVX instruction when configured as either Program or Data Memory. This means that the user may partition the device for maximum Flash Program Memory size (no Flash Data Memory) and use Flash Program Memory as Flash Data Memory. This may lead to undesirable behavior if the PC points to an area of Flash Program Memory that is being used for data storage. Therefore, it is recommended to use Flash partitioning when Flash Memory is used for data storage. Flash partitioning prohibits execution of code from Data Flash Memory. Additionally, the Program Memory erase/ write can be disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) to Data Flash Memory. 1FH Bank 3 255 FFH 80H 7FH 00H 18H 17H Direct Special Function Registers Direct Scratchpad RAM Bank 2 10H 0FH Bank 1 128 127 08H 07H Bank 0 00H 0 MSB FIGURE 19. Register Map. FIGURE 20. Scratchpad Register Addressing. MSC1200 SBAS289E LSB www.ti.com 25 Working Registers As part of the lower 128 bytes of RAM, there are four banks of Working Registers, as shown in Figure 20. The Working Registers are general-purpose RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently selected bank will be used by any instruction using R0-R7. This allows software to change context by simply switching banks. This is controlled via the Program Status Word register (PSW; 0D0H) in the SFR area described below. The 16 bytes immediately above the R0-R7 registers are bit addressable. So any of the 128 bits in this area can be directly accessed using bit addressable instructions. last used value. Therefore, the next value placed on the Stack is put at SP + 1. Each PUSH or CALL will increment the SP by the appropriate value. Each POP or RET will decrement as well. Program Memory After reset, the CPU begins execution from Program Memory location 0000H. The standard internal Program Memory size for MSC1200 family members is shown in Table V. If enabled the Boot ROM will appear from address F800H to FBFFH. MODEL NUMBER STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES) MSC1200Y3 MSC1200Y2 8k 4k Stack Another use of the Scratchpad area is for the programmer’s stack. This area is selected using the Stack Pointer (SP; 81H) SFR. Whenever a call or interrupt is invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the Stack can be moved and there is no fixed location within the RAM designated as Stack. The Stack Pointer will default to 07H on reset. The user can then move it as needed. The SP will point to the TABLE V. MSC1200 Maximum Internal Program Memory Sizes. Boot ROM There is a 1kB Boot ROM that controls operation during serial programming. Additionally, the Boot ROM routines shown in Table VI can be accessed during the user mode if it is enabled. When enabled, the Boot ROM routines will be located at memory addresses F800H-FBFFH during user mode. HEX ADDRESS ROUTINE C DECLARATIONS DESCRIPTION F802 sfr_rd char sfr_rd(void); Return SFR value pointed to by CADDR(1) F805 sfr_wr void sfr_wr(char d); Write to SFR pointed to by CADDR(1) FBD8 monitor_isr void monitor_isr() interrupt 6; Push registers and call cmd_parser FBDA cmd_parser void cmd_parser(void); See SBAA076B.pdf FBDC put_string void put_string(char code *string); Output string FBDE page_erase char page_erase (int faddr, char fdata, char fdm); Erase flash page FBE0 write_flash Assembly only; DPTR = address, ACC = data Flash write(2) FBE2 write_flash_chk char write_flash_chk (int faddr, char fdata, char fdm); Write flash byte, verify FBE4 write_flash_byte void write_flash_byte (int faddr, char fdata); Write flash byte(2) FBE6 faddr_data_read char faddr_data_read(char faddr); Read HW config byte from faddr FBE8 data_x_c_read char data_x_c_read(int faddr, char fdm); Read xdata or code byte FBEA tx_byte void tx_byte(char); Send byte to USART0 FBEC tx_hex void tx_hex(char); Send hex value to USART0 FBEE putx void putx(char); Send “x” to USART0 on R7 = 1 FBF0 rx_byte char rx_byte(void); Read byte from USART0 FBF2 rx_byte_echo char rx_byte_echo(void); Read and echo byte on USART0 FBF4 rx_hex_echo char rx_hex_echo(void); Read and echo hex on USART0 FBF6 rx_hex_dbl_echo int rx_hex_dbl_echo(void); Read int as hex and echo: USART0 FBF8 rx_hex_word_echo int rx_hex_word_echo(void); Read int reversed as hex and echo: USART0 FBFA autobaud void autobaud(void); Set baud with received CR(3) FBFC putspace1 void putspace1(void); Output 1 space to USART0 FBFE putcr void putcr(void); Output CR, LF to USART0 NOTES: (1) CADDR must be set using the faddr_data_read routine. (2) MWS register (SFR 8FH) defines Data Memory or Program Memory write. (3) SFR registers CKCON and TCON must be initialized: CKCON = 0x10 and TCON = 0x00. TABLE VI. MSC1200 Boot ROM Routines. 26 MSC1200 www.ti.com SBAS289E Serial Flash Programming Mode INTERRUPTS Two methods of programming are available: serial programming mode and user application mode. Serial programming mode is initiated by holding the P1.0/PROG pin low during POR, as shown in Figure 21. User Application mode also allows for Flash programming. Code execution from Flash Memory cannot occur in this mode while programming, but code execution can occur from Boot ROM while programming. The MSC1200 uses a three-priority interrupt system. As shown in Table VII, each interrupt source has an independent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxiliary Interrupt (AI) at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the original 8051 family. All of the standard interrupts are available. MSC1200 P3.0/RxD0 P3.1/TxD0 HARDWARE CONFIGURATION MEMORY The 64 configuration bytes can only be written during the program mode. The bytes are accessed through SFR registers CADDR (SFR 93H) and CDATA (SFR 94H). Three of the configuration bytes control Flash partitioning and system control. If the security bit is set, these bits cannot be changed except with a Mass Erase command that erases all of the Flash Memory including the 64 configuration bytes. Programmer P1.0/PROG NOTE: For user application mode, avoid heavy loading on P1.0/PROG, which may result in erroneously entering serial programming mode on power-up. FIGURE 21. Serial Programming Mode. INTERRUPT INTERRUPT ENABLE CONTROL ALVDIP (AIPOL.1)(1) EALV (AIE.1)(1) N/A CNTIP (AIPOL.2)(1) ECNT (AIE.2)(1) N/A 0 I2CIP (AIPOL.3)(1) EI2C (AIE.3)(1) N/A 6 0 MSECIP (AAIPOLIE.4)(1) EMSEC (AIE.4)(1) N/A 33H 6 0 ADCIP (AIPOL.5)(1) EADC (AIE .5)(1) N/A Summation Register 33H 6 0 SUMIP (AIPOL.6)(1) ESUM (AIE.6)(1) N/A Seconds Timer 33H 6 0 SECIP (AIPOL.7)(1) ESEC (AIE.7)(1) N/A External Interrupt 0 03H 0 1 IE0 (TCON.1)(2) EX0 (IE.0)(4) PX0 (IP.0) INTERRUPT/EVENT ADDR NUM PRIORITY FLAG AVDD Low Voltage Detect 33H 6 HIGH 0 Count (SPI/ I2C) 33H 6 0 I2C Start/Stop 33H 6 Milliseconds Timer 33H ADC Timer 0 Overflow 0BH 1 2 TF0 (TCON.5)(3) ET0 (IE.1)(4) PT0 (IP.1) External Interrupt 1 13H 2 3 IE1 (TCON.3)(2) EX1 (IE.2)(4) PX1 (IP.2) Timer 1 Overflow 1BH 3 4 TF1 (TCON.7)(3) ET1 (IE.3)(4) PT1 (IP.3) Serial Port 0 23H 4 5 RI_0 (SCON0.0) TI_0 (SCON0.1) ES0 (IE.4)(4) PS0 (IP.4) External Interrupt 2 43H 8 6 IE2 (EXIF.4) EX2 (EIE.0)(4) PX2 (EIP.0) External Interrupt 3 4BH 9 7 IE3 (EXIF.5) EX3 (EIE.1)(4) PX3 (EIP.1) External Interrupt 4 53H 10 8 IE4 (EXIF.6) EX4 (EIE.2)(4) PX4 (EIP.2) External Interrupt 5 5BH 11 9 IE5 (EXIF.7) EX5 (EIE.3)(4) PX5 (EIP.3) Watchdog 63H 12 10 LOW WDTI (EICON.3) EWDI (EIE.4)(4) PWDI (EIP.4) NOTES: (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge triggered, cleared automatically by hardware when the service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs. (4) Globally enabled by EA (IE.7). TABLE VII. Interrupt Summary. MSC1200 SBAS289E www.ti.com 27 Hardware Configuration Register 0 (HCR0)—Accessed Using SFR Registers CADDR and CDATA. CADDR 3FH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR 1 DFSEL1 DFSEL0 To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. EPMA bit 7 Enable Programming Memory Access (Security Bit). 0: After reset in programming modes, Flash Memory can only be accessed in UAM mode until a mass erase is done. 1: Fully Accessible (default) PML bit 6 Program Memory Lock (PML has Priority Over RSL). 0: Enable all Flash Programming Modes in Program Memory; can be written in UAM. 1: Enable read only for Program Memory; cannot be written in UAM (default). RSL bit 5 Reset Sector Lock. The reset sector can be used to provide another method of Flash Memory programming. This will allow Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. 0: Enable Reset Sector Writing 1: Enable Read Only Mode for Reset Sector (4kB) (default) EBR bit 4 Enable Boot ROM. Boot ROM is 1kB of code located in ROM, not to be confused with the 4kB Boot Sector located in Flash Memory. 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR bit 3 Enable Watchdog Reset. 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL1-0 Data Flash Memory Size (see Table II). bits 1-0 00: 4kB Data Flash Memory (MSC1200Y3 Only) 01: 2kB Data Flash Memory 10: 1kB Data Flash Memory 11: No Data Flash Memory (default) 28 MSC1200 www.ti.com SBAS289E Hardware Configuration Register 1 (HCR1) CADDR 3EH 7 6 5 4 3 2 1 0 1 1 1 1 1 DDB 1 1 To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. DDB bit 2 Disable Digital Brownout Detection 0: Enable Digital Brownout Detection (2.7V) 1: Disable Digital Brownout Detection (default) Hardware Configuration Register 2 (HCR2) CADDR 3DH 7 6 5 4 3 2 1 0 0 0 0 0 0 CLKSEL2 CLKSEL1 CLKSEL0 To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. CLKSEL2-0 Clock Select bits 2-0 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode 101: PLL Low-Frequency (LF) Mode 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode Configuration Memory Programming Certain key functions such as Brownout Reset and Watchdog Timer are controlled by the hardware configuration bits. These bits are nonvolatile and can only be changed through serial flash programming. Other peripheral control and status functions, such as ADC configuration timer setup, and Flash control are controlled through the SFRs. MSC1200 SBAS289E www.ti.com 29 SFR Definitions ADDRESS REGISTER 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON TMOD 8AH 8BH 8CH 8DH 8EH 8FH 90H TL0 TL1 TH0 TH1 CKCON MWS P1 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH EXIF 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH 30 BIT 7 BIT 6 BIT 5 BIT 4 0 0 0 0 SMOD 0 1 1 TF1 TR1 TF0 TR0 |---------------------------Timer 1 --------------------------| C/T GATE M1 M0 0 0 P1.7 INT5 IE5 0 0 P1.6 INT4 IE4 0 0 P1.5 INT3 IE3 T1M 0 P1.4 INT2/SS IE2 BIT 3 BIT 2 0 0 GF1 GF0 IE1 IT1 |--------------------------Timer C/T GATE T0M 0 P1.3 DIN 1 MD2 0 P1.2 DOUT 0 BIT 1 BIT 0 0 SEL STOP IDLE IE0 IT0 0 ---------------------------| M1 M0 07H 00H 00H 00H 00H 00H 30H 00H 00H MD1 0 P1.1 MD0 MXWS P1.0 00H 00H 00H 00H 01H 00H FFH 0 0 08H CADDR CDATA SCON0 SBUF0 SPICON I2CCON SPIDATA I2CDATA RESET VALUES 00H 00H SM0_0 SBIT3 SBIT3 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 SBIT2 SBIT2 SBIT1 SBIT1 SBIT0 SBIT0 ORDER STOP CPHA START ESS DCS CPOL CNTSEL 00H 00H 00H 00H AIPOL PAI AIE AISTAT IE SECIP 0 ESEC SEC EA P1DDRL P1DDRH P3 P13H P17H P3.7 SUMIP 0 ESUM SUM 0 ADCIP 0 EADC ADC 0 MSECIP 0 EMSEC MSEC ES0 I2CIP PAI3 EI2C I2C ET1 CNTIP PAI2 ECNT CNT EX1 ALVDIP PAI1 EALV ALVD ET0 0 PAI0 0 0 EX0 00H 00H 00H 00H 00H P13L P17L P3.6 P12H P16H P3.5 P12L P16L P3.4 P11H P15H P3.3 P11L P15L P3.2 P10H P14H P3.1 P10L P14L P3.0 00H 00H FFH SCK/SCL/CLKS T1 T0 INT1 INT0 TXD0 RXD0 P3DDRL P3DDRH IDAC P33H P37H P33L P37L P32H P36H P32L P36L P31H P35H P31L P35L P30H P34H P30L P34L 00H 00H 00H IP 1 0 0 PS0 PT1 PX1 PT0 PX0 80H MSC1200 www.ti.com SBAS289E SFR Definitions (Cont.) ADDRESS BFH C0H C1H C2H C3H C4H C5H C6H C7H REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EWU SYSCLK 0 0 DIVMOD1 DIVMOD0 0 EWUWDT DIV2 EWUEX1 DIV1 EWUEX0 DIV0 C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH PSW OCL OCM OCH GCL GCM GCH ADMUX EICON ADRESL ADRESM ADRESH ADCON0 ADCON1 ADCON2 ADCON3 ACC SSCON SUMR0 SUMR1 SUMR2 SUMR3 ODAC LVDCON EIE HWPC0 HWPC1 HWVER Reserved Reserved FMCON FTCON B PDCON PASEL Reserved PLLL PLLH ACLK SRST EIP SECINT MSINT USEC MSECL MSECH HMSEC WDTCON CY AC F0 RS1 RS0 OV F1 P LSB MSB LSB 00H 00H 00H 00H 00H 00H 5AH ECH 5FH 01H 40H 00H 00H 00H 30H 00H 1BH 06H 00H 00H 00H 00H 00H 00H 00H 8FH E0H 0000_000xB 20H MSB INP3 0 INP2 1 INP1 EAI INP0 AI INN3 WDTI INN2 0 INN1 0 INN0 0 LSB MSB — OF_UF DR7 0 BOD POL DR6 0 EVREF SM1 DR5 0 VREFH SM0 DR4 0 EBUF — DR3 0 PGA2 CAL2 DR2 DR10 PGA1 CAL1 DR1 DR9 PGA0 CAL0 DR0 DR8 SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 LSB ALVDIS 1 0 0 0 1 0 0 0 1 0 1 0 EWDI 0 0 1 EX5 0 0 1 EX4 0 0 1 EX3 0 0 1 EX2 MEMORY 0 0 FER3 PGERA FER2 0 FER1 FRCM FER0 0 FWR3 BUSY FWR2 1 FWR1 0 FWR0 PDICLK PSEN4 PDIDAC PSEN3 PDI2C PSEN2 0 PSEN1 PDADC PSEN0 PDWDT 0 PDST 0 PDSPI 0 02H A5H 00H 6FH 00H PLL7 CLKSTAT2 0 0 1 WRT WRT 0 MSECL7 MSECH7 HMSEC7 EWDT PLL6 CLKSTAT1 FREQ6 0 1 SECINT6 MSINT6 0 MSECL6 MSECH6 HMSEC6 DWDT PLL5 CLKSTAT0 FREQ5 0 1 SECINT5 MSINT5 FREQ5 MSECL5 MSECH5 HMSEC5 RWDT PLL4 PLLLOCK FREQ4 0 PWDI SECINT4 MSINT4 FREQ4 MSECL4 MSECH4 HMSEC4 WDCNT4 PLL3 0 FREQ3 0 PX5 SECINT3 MSINT3 FREQ3 MSECL3 MSECH3 HMSEC3 WDCNT3 PLL2 0 FREQ2 0 PX4 SECINT2 MSINT2 FREQ2 MSECL2 MSECH2 HMSEC2 WDCNT2 PLL1 PLL9 FREQ1 0 PX3 SECINT1 MSINT1 FREQ1 MSECL1 MSECH1 HMSEC1 WDCNT1 PLL0 PLL8 FREQ0 RSTREQ PX2 SECINT0 MSINT0 FREQ0 MSECL0 MSECH0 HMSEC0 WDCNT0 C1H x1H 03H 00H E0H 7FH 7FH 03H 9FH 0FH 63H 00H MSB MSC1200 SBAS289E RESET VALUES www.ti.com 31 Stack Pointer (SP) SFR 81H SP.7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 07H Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07H after reset. Data Pointer Low 0 (DPL0) SFR 82H DPL0.7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 00H Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H). Data Pointer High 0 (DPH0) SFR 83H 7 6 5 4 3 2 1 0 Reset Value DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 00H DPH0.7-0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H). Data Pointer Low 1 (DPL1) SFR 84H DPL1.7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 00H Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer High 1 (DPH1) SFR 85H 7 6 5 4 3 2 1 0 Reset Value DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 00H DPH1.7-0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer Select (DPS) SFR 86H 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 SEL 00H SEL Data Pointer Select. This bit selects the active data pointer. bit 0 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1. 32 MSC1200 www.ti.com SBAS289E Power Control (PCON) SFR 87H 7 6 5 4 3 2 1 0 Reset Value SMOD 0 1 1 GF1 GF0 STOP IDLE 30H SMOD bit 7 Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation. GF1 bit 3 General-Purpose User Flag 1. This is a general-purpose flag for software control. GF0 bit 2 General-Purpose User Flag 0. This is a general-purpose flag for software control. STOP bit 1 Stop Mode Select. Setting this bit will halt the oscillator and block external clocks. This bit will always read as a 0. Exit with RESET. In this mode, internal peripherals are frozen and I/O pins are held in their current state. The ADC is frozen, but IDAC and VREF remain active. IDLE bit 0 Idle Mode Select. Setting this bit will freeze the CPU, Timer 0 and 1, and the USART; other peripherals remain active. This bit will always be read as a 0. Exit with AIE (A6H) and EWU (C6H) interrupts (refer to Figure 4 for clocks affected during IDLE). Timer/Counter Control (TCON) SFR 88H 7 6 5 4 3 2 1 0 Reset Value TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H TF1 bit 7 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current bit 6 count in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 bit 5 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 bit 4 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the current count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 bit 3 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 bit 2 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts. 0: INT1 is level triggered. 1: INT1 is edge triggered. IE0 bit 3 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 bit 2 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts. 0: INT0 is level triggered. 1: INT0 is edge triggered. MSC1200 SBAS289E www.ti.com 33 Timer Mode Control (TMOD) 7 6 5 4 3 2 TIMER 1 SFR 89H GATE C/T 1 M1 M0 GATE Reset Value C/T M1 GATE bit 7 Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T bit 6 Timer 1 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88H) is 1. M1, M0 bits 5-4 Timer 1 Mode Select. These bits select the operating mode of Timer 1. M1 M0 MODE 0 0 1 1 0 1 0 1 Mode Mode Mode Mode 0: 1: 2: 3: 0 TIMER 0 M0 8-bit counter with 5-bit prescale. 16 bits. 8-bit counter with auto reload. Two 8-bit counters. GATE bit 3 Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T bit 2 Timer 0 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88H) is 1. M1, M0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. bits 1-0 M1 M0 MODE 0 0 1 1 0 1 0 1 Mode Mode Mode Mode 0: 1: 2: 3: 00H 8-bit counter with 5-bit prescale. 16 bits. 8-bit counter with auto reload. Two 8-bit counters. Timer 0 LSB (TL0) SFR 8AH TL0.7-0 7 6 5 4 3 2 1 0 Reset Value TL0.7 TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 00H Timer 0 LSB. This register contains the least significant byte of Timer 0. bits 7-0 Timer 1 LSB (TL1) SFR 8BH TL1.7-0 7 6 5 4 3 2 1 0 Reset Value TL1.7 TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 00H Timer 1 LSB. This register contains the least significant byte of Timer 1. bits 7-0 Timer 0 MSB (TH0) SFR 8CH TH0.7-0 7 6 5 4 3 2 1 0 Reset Value TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00H Timer 0 MSB. This register contains the most significant byte of Timer 0. bits 7-0 34 MSC1200 www.ti.com SBAS289E Timer 1 MSB (TH1) SFR 8DH TH1.7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value TH1.7 TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00H Timer 1 MSB. This register contains the most significant byte of Timer 1. Clock Control (CKCON) SFR 8EH 7 6 5 4 3 2 1 0 Reset Value 0 0 0 T1M T0M MD2 MD1 MD0 01H T1M bit 4 Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide by 12 of the crystal frequency. 1: Timer 1 uses a divide by 4 of the crystal frequency. T0M bit 3 Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide by 12 of the crystal frequency. 1: Timer 0 uses a divide by 4 of the crystal frequency. MD2, MD1, MD0 Stretch MOVX Select. These bits select the time by which MOVX cycles are to be stretched. Since the MSC1200 bit 3 does not allow external memory access, these bits should be set to 000B to allow for the fastest flash data memory access. SFR 8FH 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 MXWS 00H Memory Write Select (MWS) MXWS bit 0 MOVX Write Select. This allows writing to the internal Flash program memory. 0: No writes are allowed to the internal Flash program memory. 1: Writing is allowed to the internal Flash program memory, unless PML (HCR0) or RSL (HCR0) are on. Port 1 (P1) SFR 90H 7 6 5 4 3 2 1 0 Reset Value P1.7 INT5 P1.6 INT4 P1.5 INT3 P1.4 INT2/SS P1.3 DIN P1.2 DOUT P1.1 P1.0 PROG FFH P1.7-0 bits 7-0 General-Purpose I/O Port 1. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 1 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. To use the alternate function, set the appropriate mode in P1DDRL (SFR AEH), P1DDRH (SFR AFH). INT5 bit 7 External Interrupt 5.A falling edge on this pin will cause an external interrupt 5 if enabled. INT4 bit 6 External Interrupt 4. A rising edge on this pin will cause an external interrupt 4 if enabled. INT3 bit 5 External Interrupt 3. A falling edge on this pin will cause an external interrupt 3 if enabled. INT2/SS bit 4 External Interrupt 2. A rising edge on this pin will cause an external interrupt 2 if enabled. This pin can be used as slave select (SS) in SPI slave mode. DIN bit 3 Serial Data In. This pin receives serial data in SPI and I2C modes (in I2C mode, this pin should be configured as an input) or standard 8051. DOUT bit 2 Serial Data Out. This pin transmits serial data in SPI and I2C modes (in I2C mode, this pin should be configured as an open drain) or standard 8051. PROG bit 0 Program Mode. When this pin is pulled low at power-up, the device enters Serial Programming mode (refer to Figure B). MSC1200 SBAS289E www.ti.com 35 External Interrupt Flag (EXIF) SFR 91H 7 6 5 4 3 2 1 0 Reset Value IE5 IE4 IE3 IE2 1 0 0 0 08H IE5 bit 7 External Interrupt 5 Flag. This bit will be set when a falling edge is detected on INT5. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE4 bit 6 External Interrupt 4 Flag. This bit will be set when a rising edge is detected on INT4. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE3 bit 5 External Interrupt 3 Flag. This bit will be set when a falling edge is detected on INT3. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. IE2 bit 4 External Interrupt 2 Flag. This bit will be set when a rising edge is detected on INT2. This bit must be cleared manually by software. Setting this bit in software will cause an interrupt if enabled. Configuration Address Register (CADDR) (write only) 7 6 5 4 3 2 1 0 00H SFR 93H CADDR bits 7-0 Reset Value Configuration Address Register. This register supplies the address for reading bytes in the 64 bytes of Flash Configuration Memory. Always use the Boot ROM CADDR access routine. This register is also used for SFR read and write routines. WARNING: If this register is written to while executing from Flash Memory, the CDATA register will be incorrect. Configuration Data Register (CDATA) 7 6 5 4 3 36 1 0 Reset Value 00H SFR 94H CDATA bits 7-0 2 Configuration Data Register. This register will contain the data in the 64 bytes of Flash Configuration Memory that is located at the last written address in the CADDR register. This is a read-only register. MSC1200 www.ti.com SBAS289E Serial Port 0 Control (SCON0) SFR 98H SM0-2 bits 7-5 7 6 5 4 3 2 1 0 Reset Value SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00H Serial Port 0 Mode. These bits control the mode of serial Port 0. Modes 1, 2, and 3 have 1 start and 1 stop bit in addition to the 8 or 9 data bits. MODE SM0 SM1 SM2 FUNCTION LENGTH PERIOD 0 0 0 0 0 0 0 1 Synchronous Synchronous 8 bits 8 bits 12 pCLK(1) 4 pCLK(1) 1 1 0 0 1 1 0 1 Asynchronous Asynchronous—Valid Stop Required(2) 10 bits 10 bits Timer 1 Baud Rate Equation Timer 1 Baud Rate Equation 2 1 0 0 Asynchronous 11 bits 2 1 0 1 Asynchronous with Multiprocessor Communication 11 bits 64 32 64 32 3 3 1 1 1 1 0 1 Asynchronous Asynchronous with Multiprocessor Communication(3) 11 bits 11 bits pCLK(1) pCLK(1) pCLK(1) pCLK(1) (SMOD (SMOD (SMOD (SMOD = = = = 0) 1) 0) 1) Timer 1 Baud Rate Equation Timer 1 Baud Rate Equation NOTES: (1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE. (2) RI_0 will only be activated when a valid stop is received. (3) RI_0 will not be activated if bit 9 = 0. REN_0 bit 4 Receive Enable. This bit enables/disables the serial Port 0 received shift register. 0: Serial Port 0 reception disabled. 1: Serial Port 0 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0). TB8_0 bit 3 9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 0 modes 2 and 3. RB8_0 bit 2 9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 0 modes 2 and 3. In serial port mode 1, when SM2_0 = 0, RB8_0 is the state of the stop bit. RB8_0 is not used in mode 0. TI_0 bit 1 Transmitter Interrupt Flag. This bit indicates that data in the serial Port 0 buffer has been completely shifted out. In serial port mode 0, TI_0 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last data bit. This bit must be manually cleared by software. RI_0 bit 0 Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 0 buffer. In serial port mode 0, RI_0 is set at the end of the 8th bit. In serial port mode 1, RI_0 is set after the last sample of the incoming stop bit subject to the state of SM2_0. In modes 2 and 3, RI_0 is set after the last sample of RB8_0. This bit must be manually cleared by software. Serial Data Buffer 0 (SBUF0) 7 6 5 4 3 SFR 99H SBUF0 bits 7-0 1 0 Reset Value 00H Serial Data Buffer 0. Data for Serial Port 0 is read from or written to this location. The serial transmit and receive buffers are separate registers, but both are addressed at this location. MSC1200 SBAS289E 2 www.ti.com 37 SPI Control (SPICON) (SERSEL bit determines SPICON control) SFR 9AH SBIT3-0 bits 7-4 7 6 5 4 3 2 1 0 Reset Value SBIT3 SBIT2 SBIT1 SBIT0 ORDER CPHA ESS CPOL 00H Serial Bit Count. Number of bits transferred (read only). SBIT3:0 COUNT 0x00 0x01 0x03 0x02 0x06 0x07 0x05 0x04 0x0C 0 1 2 3 4 5 6 7 8 ORDER bit 3 Set Bit Order for Transmit and Receive. 0: Most Significant Bits First 1: Least Significant Bits First CPHA bit 2 Serial Clock Phase Control. 0: Valid data starting from half SCK period before the first edge of SCK 1: Valid data starting from the first edge of SCK ESS bit 1 Enable Slave Select. 0: SS (P1.4) is configured as a general-purpose I/O (default). 1: SS (P1.4) is configured as SS for SPI mode. DOUT (P1.2) drives when SS is low, and DOUT (P1.2) is highimpedance when SS is high. CPOL bit 0 Serial Clock Polarity. 0: SCK idle at logic LOW 1: SCK idle at logic HIGH I2C Control (I2CCON) (SERSEL bit determines I2CCON control) SFR 9AH SBIT3-0 bits 7-4 7 6 5 4 3 2 1 0 Reset Value SBIT3 SBIT2 SBIT1 SBIT0 STOP START DCS CNTSEL 00H Serial Bit Count. Number of bits transferred (read only). SBIT3:0 COUNT 0x00 0x01 0x03 0x02 0x06 0x07 0x05 0x04 0x0C 0 1 2 3 4 5 6 7 8 STOP bit 3 Stop-Bit Status. 0: No Stop 1: Stop Condition Received and I2CCNT set (cleared on write to I2CDATA) START bit 2 Start-Bit Status. 0: No Stop 1: Start or Repeated Start Condition Received and I2CCNT set (cleared on write to I2CDATA) 38 MSC1200 www.ti.com SBAS289E DCS bit 1 Disable Serial Clock Stretch. 0: Enable SCL Stretch (cleared by firmware or START condition) 1: Disable SCL Stretch CNTSEL bit 0 Counter Select. 0: Counter IRQ Set for Bit Counter = 8 (default) 1: Counter IRQ Set for Bit Counter = 1 SPI Data Register (SPIDATA) / I2C Data Register (I2CDATA) 7 6 5 4 3 2 1 0 SFR 9BH Reset Value 00H SPIDATA bits 7-0 SPI Data Register. Data for SPI is read from or written to this location. The SPI transmit and receive buffers are separate registers, but both are addressed at this location. I2CDATA bits 7-0 I2C Data Register. Data for I2C is read from or written to this location. The I2C transmit and receive buffers are separate registers, but both are addressed at this location. Auxilliary Interrupt Poll (AIPOL) SFR A4H 7 6 5 4 3 2 1 0 Reset Value SECIP SUMIP ADCIP MSECIP I2CIP CNTIP ALVDIP Unused 00H SECIP bit 7 Second System Timer Interrupt Poll (before IRQ masking). 0 = Seconds System Timer Interrupt Poll Inactive 1 = Seconds System Timer Interrupt Poll Active SUMIP bits 6 Accumulator Interrupt Poll (before IRQ masking). 0 = Accumulator Interrupt Poll Inactive 1 = Accumulator Interrupt Poll Active ADCIP bits 5 ADC Interrupt Poll (before IRQ masking). 0 = ADC Interrupt Poll Inactive 1 = ADC Interrupt Poll Active MSECIP bits 4 Millisecond System Timer Interrupt Poll (before IRQ masking). 0 = Millisecond System Timer Interrupt Poll Inactive 1 = Millisecond System Timer Interrupt Poll Active I2CIP bits 3 I2C Interrupt Poll (before IRQ masking). 0 = I2C Interrupt Poll Inactive 1 = I2C Interrupt Poll Active CNTIP bits 2 Serial Bit Count Interrupt Poll (before IRQ masking). 0 = Serial Bit Count Interrupt Poll Inactive 1 = Serial Bit Count Interrupt Poll Active ALVDIP bits 1 Analog Low Voltage Detect Interrupt Poll (before IRQ masking). 0 = Analog Low Voltage Detect Interrupt Poll Inactive 1 = Analog Low Voltage Detect Interrupt Poll Active MSC1200 SBAS289E www.ti.com 39 Pending Auxiliary Interrupt (PAI) SFR A5H PAI bits 3-0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 PAI3 PAI2 PAI1 PAI0 00H Pending Auxiliary Interrupt Register. The results of this register can be used as an index to vector to the appropriate interrupt routine. All of these interrupts vector through address 0033H. PAI3 PAI2 PAI1 PAI0 0 0 0 0 No Pending Auxiliary IRQ AUXILIARY INTERRUPT STATUS 0 0 0 1 Reserved 0 0 1 0 Analog Low Voltage Detect IRQ and Possible Lower Priority Pending 0 0 1 1 I2C IRQ and Possible Lower Priority Pending 0 1 0 0 Serial Bit Count Interrupt and Possible Lower Priority Pending 0 1 0 1 Millisecond System Timer IRQ and Possible Lower Priority Pending 0 1 1 0 ADC IRQ and Possible Lower Priority Pending 0 1 1 1 Accumulator IRQ and Possible Lower Priority Pending 1 0 0 0 Second System Timer IRQ and Possible Lower Priority Pending Auxiliary Interrupt Enable (AIE) SFR A6H 7 6 5 4 3 2 1 0 Reset Value ESEC ESUM EADC EMSEC EI2C ECNT EALV 0 00H Interrupts are enabled by EICON.4 (SFR D8H). The other interrupts are controlled by the IE and EIE registers. ESEC bit 7 Enable Second System Timer Interrupt (lowest priority auxiliary interrupt). Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Second Timer Interrupt mask. ESUM bit 6 Enable Summation Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Summation Interrupt mask. EADC bit 5 Enable ADC Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: ADC Interrupt mask. EMSEC bit 4 Enable Millisecond System Timer Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Millisecond System Timer Interrupt mask. EI2C bit 3 Enable I2C Start/Stop Bit. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: I2C Start/Stop Bit mask. ECNT bit 2 Enable Serial Bit Count Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Serial Bit Count Interrupt mask. EALV bit 1 Enable Analog Low Voltage Interrupt. Write: Set mask bit for this interrupt; 0 = masked, 1 = enabled. Read: Analog Low Voltage Detect Interrupt mask. 40 MSC1200 www.ti.com SBAS289E Auxiliary Interrupt Status Register (AISTAT) SFR A7H 7 6 5 4 3 2 1 0 Reset Value SEC SUM ADC MSEC I2C CNT ALVD 0 00H SEC bit 7 Second System Timer Interrupt Status Flag (lowest priority AI). 0: SEC Interrupt cleared or masked. 1: SEC Interrupt active (it is cleared by reading SECINT, SFR F9H). SUM bit 6 Summation Register Interrupt Status Flag. 0: SUM Interrupt cleared or masked. 1: SUM Interrupt active (it is cleared by reading the lowest byte of SUMR0, SFR E2H). ADC bit 5 ADC Interrupt Status Flag. 0: ADC Interrupt cleared or masked. 1: ADC Interrupt active (it is cleared by reading the lowest byte of ADRESL, SFR D9H; if active, no new data will be written to the ADC Results registers). MSEC bit 4 Millisecond System Timer Interrupt Status Flag. 0: MSEC Interrupt cleared or masked. 1: MSEC Interrupt active (it is cleared by reading MSINT, SFR FAH). I2C bit 3 I2C Start/Stop Interrupt Status Flag. 0: I2C Start/stop Interrupt cleared or masked. 1: I2C Start/stop Interrupt active (it is cleared by writing to I2CDATA, SFR 9BH). CNT bit 2 CNT Interrupt Status Flag. 0: CNT Interrupt cleared or masked. 1: CNT Interrupt active (it is cleared by reading from or writing to SPIDATA/I2CDATA, SFR 9BH). ALVD bit 1 Analog Low Voltage Detect Interrupt Status Flag. 0: ALVD Interrupt cleared or masked. 1: ALVD Interrupt active (cleared in HW if AVDD exceeds ALVD threshold). NOTE: If an interrupt is masked, the status can be read in AIPOL, SFR A4H. SFR A8H 7 6 5 4 3 2 1 0 Reset Value EA 0 0 ES0 ET1 EX1 ET0 EX0 00H Interrupt Enable (IE) EA bit 7 Global Interrupt Enable. This bit controls the global masking of all interrupts except those in AIE (SFR A6H). 0: Disable interrupt sources. This bit overrides individual interrupt mask settings for this register. 1: Enable all individual interrupt masks. Individual interrupts in this register will occur if enabled. ES0 bit 4 Enable Serial port 0 interrupt. This bit controls the masking of the serial Port 0 interrupt. 0: Disable all serial Port 0 interrupts. 1: Enable interrupt requests generated by the RI_0 (SCON0.0, SFR 98H) or TI_0 (SCON0.1, SFR 98H) flags. ET1 bit 3 Enable Timer 1 Interrupt. This bit controls the masking of the Timer 1 interrupt. 0: Disable Timer 1 interrupt. 1: Enable interrupt requests generated by the TF1 flag (TCON.7, SFR 88H). EX1 bit 2 Enable External Interrupt 1. This bit controls the masking of external interrupt 1. 0: Disable external interrupt 1. 1: Enable interrupt requests generated by the INT1 pin. ET0 bit 1 Enable Timer 0 Interrupt. This bit controls the masking of the Timer 0 interrupt. 0: Disable all Timer 0 interrupts. 1: Enable interrupt requests generated by the TF0 flag (TCON.5, SFR 88H). EX0 bit 0 Enable External Interrupt 0. This bit controls the masking of external interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the INT0 pin. MSC1200 SBAS289E www.ti.com 41 Port 1 Data Direction Low Register (P1DDRL) SFR AEH P1.3 bits 7-6 P1.2 bits 5-4 P1.1 bits 3-2 P1.0 bits 1-0 7 6 5 4 3 2 1 0 Reset Value P13H P13L P12H P12L P11H P11L P10H P10L 00H Port 1 bit 3 control. P13H P13L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 1 bit 2 control. P12H P12L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 1 bit 1 control. P11H P11L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 1 bit 0 control. P10H P10L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 1 Data Direction High Register (P1DDRH) SFR AFH P1.7 bits 7-6 P1.6 bits 5-4 P1.5 bits 3-2 P1.4 bits 1-0 42 7 6 5 4 3 2 1 0 Reset Value P17H P17L P16H P16L P15H P15L P14H P14L 00H Port 1 bit 7 control. P17H P17L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 1 bit 6 control. P16H P16L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 1 bit 5 control. P15H P15L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 1 bit 4 control. P14H P14L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input MSC1200 www.ti.com SBAS289E Port 3 (P3) SFR B0H P3.7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value P3.7 P3.6 SCK/SCL/CLKS P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFH General-Purpose I/O Port 3. This register functions as a general-purpose I/O port. In addition, all the pins have an alternative function listed below. Each of the functions is controlled by several other SFRs. The associated Port 3 latch bit must contain a logic ‘1’ before the pin can be used in its alternate function capacity. SCK/SCL/CLKS bit 6 Clock Source Select. Refer to PASEL (SFR F2H). T1 bit 5 Timer/Counter 1 External Input. A 1 to 0 transition on this pin will increment Timer 1. T0 bit 4 Timer/Counter 0 External Input. A 1 to 0 transition on this pin will increment Timer 0. INT1 bit 3 External Interrupt 1. A falling edge/low level on this pin will cause an external interrupt 1 if enabled. INT0 bit 2 External Interrupt 0. A falling edge/low level on this pin will cause an external interrupt 0 if enabled. TXD0 bit 1 Serial Port 0 Transmit. This pin transmits the serial Port 0 data in serial port modes 1, 2, 3, and emits the synchronizing clock in serial port mode 0. RXD0 bit 0 Serial Port 0 Receive. This pin receives the serial Port 0 data in serial port modes 1, 2, 3, and is a bidirectional data transfer pin in serial port mode 0. Port 3 Data Direction Low Register (P3DDRL) SFR B3H P3.3 bits 7-6 P3.2 bits 5-4 P3.1 bits 3-2 P3.0 bits 1-0 7 6 5 4 3 2 1 0 Reset Value P33H P33L P32H P32L P31H P31L P30H P30L 00H Port 3 bit 3 control. P33H P33L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 3 bit 2 control. P32H P32L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 3 bit 1 control. P31H P31L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 3 bit 0 control. P30H P30L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input MSC1200 SBAS289E www.ti.com 43 Port 3 Data Direction High Register (P3DDRH) SFR B4H P3.7 bits 7-6 7 6 5 4 3 2 1 0 Reset Value P37H P37L P36H P36L P35H P35L P34H P34L 00H 3 2 1 0 Reset Value Port 3 bit 7 control. P37H P37L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input NOTE: Port 3.7 also controlled by EA and Memory Access Control HCR1.1. P3.6 bits 5-4 Port 3 bit 6 control. P36H P36L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input NOTE: Port 3.6 also controlled by EA and Memory Access Control HCR1.1. P3.5 bits 3-2 P3.4 bits 1-0 Port 3 bit 5 control. P35H P35L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input Port 3 bit 4 control. P34H P34L 0 0 1 1 0 1 0 1 Standard 8051 CMOS Output Open Drain Output Input IDAC Register 7 6 5 4 00H SFR B5H IDAC bits 7-0 IDAC Register. IDACOUT = IDAC • 3.8µA (~1mA full-scale). Setting (PDCON.PDIDAC) will shut down IDAC and float the IDAC pin. Interrupt Priority (IP) SFR B8H 7 6 5 4 3 2 1 0 Reset Value 1 0 0 PS0 PT1 PX1 PT0 PX0 80H PS0 bit 4 Serial Port 0 Interrupt. This bit controls the priority of the serial Port 0 interrupt. 0 = Serial Port 0 priority is determined by the natural priority order. 1 = Serial Port 0 is a high priority interrupt. PT1 bit 3 Timer 1 Interrupt. This bit controls the priority of the Timer 1 interrupt. 0 = Timer 1 priority is determined by the natural priority order. 1 = Timer 1 priority is a high priority interrupt. PX1 bit 2 External Interrupt 1. This bit controls the priority of external interrupt 1. 0 = External interrupt 1 priority is determined by the natural priority order. 1 = External interrupt 1 is a high priority interrupt. PT0 bit 1 Timer 0 Interrupt. This bit controls the priority of the Timer 0 interrupt. 0 = Timer 0 priority is determined by the natural priority order. 1 = Timer 0 priority is a high priority interrupt. PX0 bit 0 External Interrupt 0. This bit controls the priority of external interrupt 0. 0 = External interrupt 0 priority is determined by the natural priority order. 1 = External interrupt 0 is a high priority interrupt. 44 MSC1200 www.ti.com SBAS289E Enable Wake Up (EWU) Waking Up from IDLE Mode SFR C6H 7 6 5 4 3 2 1 0 Reset Value — — — — — EWUWDT EWUEX1 EWUEX0 00H Auxiliary interrupts will wake up from IDLE. They are enabled with EAI (EICON.5). EWUWDT bit 2 Enable Wake Up Watchdog Timer. Wake up using watchdog timer interrupt. 0 = Don’t wake up on watchdog timer interrupt. 1 = Wake up on watchdog timer interrupt. EWUEX1 bit 1 Enable Wake Up External 1. Wake up using external interrupt source 1. 0 = Don’t wake up on external interrupt source 1. 1 = Wake up on external interrupt source 1. EWUEX0 bit 0 Enable Wake Up External 0. Wake up using external interrupt source 0. 0 = Don’t wake up on external interrupt source 0. 1 = Wake up on external interrupt source 0. System Clock Divider Register (SYSCLK) SFR C7H 7 6 5 4 3 2 1 0 Reset Value 0 0 DIVMOD1 DIVMOD0 0 DIV2 DIV1 DIV0 00H DIVMOD1-0 Clock Divide Mode bits 5-4 Write: DIVMOD DIVIDE MODE 00 Normal mode (default, no divide) 01 Immediate mode: start divide immediately, return to Normal mode on IDLE wakeup condition or Normal mode write. 10 Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the MSINT counter overflows, which follows a wakeup condition. Can exit on Normal mode write. 11 Manual mode: start divide immediately; exit mode only on write to DIVMOD. Read: DIVMOD 00 01 10 11 DIV2-0 bit 2-0 DIVISION MODE STATUS No divide Divider is in Immediate mode Divider is in Delay mode Reserved Divide Mode DIV DIVISOR 000 001 010 011 100 101 110 111 Divide Divide Divide Divide Divide Divide Divide Divide by by by by by by by by 2 (default) 4 8 16 32 1024 2048 4096 fCLK fCLK fCLK fCLK fCLK fCLK fCLK fCLK = = = = = = = = fSYS/2 fSYS/4 fSYS/8 fSYS/16 fSYS/32 fSYS/1024 fSYS/2048 fSYS/4096 MSC1200 SBAS289E www.ti.com 45 Program Status Word (PSW) SFR D0H 7 6 5 4 3 2 1 0 Reset Value CY AC F0 RS1 RS0 OV F1 P 00H CY bit 7 Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (during addition) or a borrow (during subtraction). Otherwise it is cleared to 0 by all arithmetic operations. AC bit 6 Auxiliary Carry Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry into (during addition), or a borrow (during substraction) from the high order nibble. Otherwise it is cleared to 0 by all arithmetic operations. F0 bit 5 User Flag 0. This is a bit-addressable, general-purpose flag for software control. RS1, RS0 bits 4-3 Register Bank Select 1-0. These bits select which register bank is addressed during register accesses. RS1 RS0 REGISTER BANK 0 0 1 1 0 1 0 1 0 1 2 3 ADDRESS 00H-07H 08H-0FH 10H-17H 18H-1FH OV bit 2 Overflow Flag. This bit is set to 1 if the last arithmetic operation resulted in a carry (addition), borrow (subtraction), or overflow (multiply or divide). Otherwise it is cleared to 0 by all arithmetic operations. F1 bit 1 User Flag 1. This is a bit-addressable, general-purpose flag for software control. P bit 0 Parity Flag. This bit is set to 1 if the modulo-2 sum of the 8 bits of the accumulator is 1 (odd parity); and cleared to 0 on even parity. ADC Offset Calibration Register Low Byte (OCL) 7 6 5 4 3 2 1 SFR D1H OCL bits 7-0 0 Reset Value LSB 00H ADC Offset Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC offset calibration. A value which is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register Middle Byte (OCM) 7 6 5 4 3 2 1 0 OCM bits 7-0 Reset Value 00H SFR D2H ADC Offset Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC offset calibration. A value which is written to this location will set the ADC offset calibration value. ADC Offset Calibration Register High Byte (OCH) 7 SFR D3H OCH bits 7-0 46 6 5 4 3 MSB 2 1 0 Reset Value 00H ADC Offset Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC offset calibration. A value which is written to this location will set the ADC offset calibration value. MSC1200 www.ti.com SBAS289E ADC Gain Calibration Register Low Byte (GCL) 7 6 5 4 3 2 1 SFR D4H GCL bits 7-0 0 Reset Value LSB 5AH ADC Gain Calibration Register Low Byte. This is the low byte of the 24-bit word that contains the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register Middle Byte (GCM) 7 6 5 4 3 2 1 0 SFR D5H GCM bits 7-0 Reset Value ECH ADC Gain Calibration Register Middle Byte. This is the middle byte of the 24-bit word that contains the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value. ADC Gain Calibration Register High Byte (GCH) 7 SFR D6H GCH bits 7-0 6 5 4 3 2 1 0 MSB Reset Value 5FH ADC Gain Calibration Register High Byte. This is the high byte of the 24-bit word that contains the ADC gain calibration. A value which is written to this location will set the ADC gain calibration value. ADC Multiplexer Register (ADMUX) SFR D7H INP3-0 bits 7-4 INN3-0 bits 3-0 7 6 5 4 3 2 1 0 Reset Value INP3 INP2 INP1 INP0 INN3 INN2 INN1 INN0 01H Input Multiplexer Positive Channel. This selects the positive signal input. INP3 INP2 INP1 INP0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 POSITIVE INPUT AIN0 (default) AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (Requires ADMUX = FFH) Input Multiplexer Negative Channel. This selects the negative signal input. INN3 INN2 INN1 INN0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 NEGATIVE INPUT AIN0 AIN1 (default) AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Temperature Sensor (Requires ADMUX = FFH) MSC1200 SBAS289E www.ti.com 47 Enable Interrupt Control (EICON) SFR D8H 7 6 5 4 3 2 1 0 Reset Value 0 1 EAI AI WDTI 0 0 0 40H EAI bit 5 Enable Auxiliary Interrupt. The Auxiliary Interrupt accesses nine different interrupts which are masked and identified by SFR registers PAI (SFR A5H), AIE (SFR A6H), and AISTAT (SFR A7H). 0 = Auxiliary Interrupt disabled (default). 1 = Auxiliary Interrupt enabled. AI bit 4 Auxiliary Interrupt Flag. AI must be cleared by software before exiting the interrupt service routine, after the source of the interrupt is cleared. Otherwise, the interrupt occurs again. Setting AI in software generates an Auxiliary Interrupt, if enabled. 0 = No Auxiliary Interrupt detected (default). 1 = Auxiliary Interrupt detected. WDTI bit 3 Watchdog Timer Interrupt Flag. WDTI must be cleared by software before exiting the interrupt service routine. Otherwise, the interrupt occurs again. Setting WDTI in software generates a watchdog time interrupt, if enabled. The Watchdog timer can generate an interrupt or reset. The interrupt is available only if the reset action is disabledin HCR0. 0 = No Watchdog Timer Interrupt Detected (default). 1 = Watchdog Timer Interrupt Detected. ADC Results Register Low Byte (ADRESL) 7 6 5 4 3 2 1 SFR D9H ADRESL bits 7-0 0 Reset Value LSB 00H The ADC Results Low Byte. This is the low byte of the 24-bit word that contains the ADC Results. Reading from this register clears the ADC interrupt; however, AI in EICON (SFR D8) must also be cleared. ADC Results Register Middle Byte (ADRESM) 7 6 5 4 3 2 1 0 SFR DAH ADRESM bits 7-0 Reset Value 00H The ADC Results Middle Byte. This is the middle byte of the 24-bit word that contains the ADC Results. ADC Results Register High Byte (ADRESH) 7 SFR DBH ADRESH bits 7-0 48 6 5 4 3 MSB 2 1 0 Reset Value 00H The ADC Results High Byte. This is the high byte of the 24-bit word that contains the ADC Results. MSC1200 www.ti.com SBAS289E ADC Control Register 0 (ADCON0) SFR DCH 7 6 5 4 3 2 1 0 Reset Value — BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 30H BOD bit 6 Burnout Detect. When enabled this connects a positive current source to the positive channel and a negative current source to the negative channel. If the channel is open circuit then the ADC results will be full-scale (buffer must be enabled). 0 = Burnout Current Sources Off (default). 1 = Burnout Current Sources On. EVREF bit 5 Enable Internal Voltage Reference. If an external voltage reference is used, the internal voltage reference should be disabled. 0 = Internal Voltage Reference Off. 1 = Internal Voltage Reference On (default). VREFH bit 4 Voltage Reference High Select. The internal voltage reference can be selected to be 2.5V or 1.25V. 0 = REFOUT/REFIN+ is 1.25V. 1 = REFOUT/REFIN+ is 2.5V (default). EBUF bit 3 Enable Buffer. Enable the input buffer to provide higher input impedance but limits the input voltage range and dissipates more power. 0 = Buffer disabled (default). 1 = Buffer enabled. PGA2-0 bits 2-0 Programmable Gain Amplifier. Sets the gain for the PGA from 1 to 128. PGA2 PGA1 PGA0 GAIN 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 (default) 2 4 8 16 32 64 128 MSC1200 SBAS289E www.ti.com 49 ADC Control Register 1 (ADCON1) SFR DDH 7 6 5 4 3 2 1 0 Reset Value OF_UF POL SM1 SM0 — CAL2 CAL1 CAL0 x000 0000B OF_UF bit 7 Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or an underflow occurred. The bit is cleared by writing a 0 to it. POL bit 6 Polarity. Polarity of the ADC result and Summation register. 0 = Bipolar. 1 = Unipolar. SM1-0 bits 5-4 CAL2-0 bits 2-0 POL ANALOG INPUT DIGITAL OUTPUT 0 +FSR ZERO –FSR 0x7FFFFF 0x000000 0x800000 1 +FSR ZERO –FSR 0xFFFFFF 0x000000 0x000000 Settling Mode. Selects the type of filter or auto select which defines the digital filter settling characteristics. SM1 SM0 SETTLING MODE 0 0 1 1 0 1 0 1 Auto Fast Settling Filter Sinc2 Filter Sinc3 Filter Calibration Mode Control Bits. Writing to this register initiates calibration. CAL2 CAL1 CAL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 CALIBRATION MODE No Calibration (default) Self Calibration, Offset and Gain Self Calibration, Offset Only Self Calibration, Gain Only System Calibration, Offset Only System Calibration, Gain Only Reserved Reserved Read Value—000B. ADC Control Register 2 (ADCON2) SFR DEH DR7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 1BH Decimation Ratio LSB (refer to ADCON3, SFR DFH). ADC Control Register 3 (ADCON3) SFR DFH DR10-8 bits 2-0 7 6 5 4 3 2 1 0 Reset Value — — — — — DR10 DR9 DR8 06H Decimation Ratio Most Significant 3 Bits. The output data rate = fMOD fCLK where fMOD = . Decimation Ratio (ACLK + 1) • 64 Accumulator (A or ACC) SFR E0H ACC.7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 00H Accumulator. This register serves as the accumulator for arithmetic and logic operations. Summation/Shifter Control (SSCON) SFR E1H 7 6 5 4 3 2 1 0 Reset Value SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 00H The Summation register is powered down when the ADC is powered down. If all zeroes are written to this register the 32-bit SUMR3-0 registers will be cleared. The Summation registers will do sign extend if Bipolar is selected in ADCON1. 50 MSC1200 www.ti.com SBAS289E SSCON1-0 Summation/Shift Control. bits 7-6 SSCON1 SSCON0 0 0 0 1 0 1 0 0 0 0 1 1 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 0 0 1 x Note (1) Note (1) 0 1 0 x Note (1) Note (1) 0 0 0 x Note (1) Note (1) 0 0 0 Note (1) x Note (1) 0 0 0 Note (1) x Note (1) 0 0 0 Note (1) x Note (1) DESCRIPTION Clear Summation Register CPU Summation on Write to SUMR0 CPU Subtraction on Write to SUMR0 CPU Shift Only ADC Summation Only ADC Summation Completes then Shift Completes NOTES: (1) Refer to register bit definition. SCNT2-0 bits 5-3 Summation Count. When the summation is complete an interrupt will be generated unless masked. Reading the SUMR0 register clears the interrupt. SCNT2 0 0 0 0 1 1 1 1 SHF2-0 bits 2-0 SCNT1 SCNT0 0 0 1 1 0 0 1 1 SUMMATION COUNT 0 1 0 1 0 1 0 1 2 4 8 16 32 64 128 256 Shift Count. SHF2 SHF1 SHF0 SHIFT DIVIDE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 2 4 8 16 32 64 128 256 5 4 Summation Register 0 (SUMR0) 7 6 3 2 1 SFR E2H SUMR0 bits 7-0 0 Reset Value LSB 00H Summation Register 0. This is the least significant byte of the 32-bit summation register or bits 0 to 7. Write: will cause values in SUMR3-0 to be added to or subtracted from the summation register. Read: will clear the Summation Interrupt. Summation Register 1 (SUMR1) 7 6 5 4 3 2 1 0 SFR E3H SUMR1 bits 7-0 Reset Value 00H Summation Register 1. This is the most significant byte of the lowest 16 bits of the summation register or bits 8-15. Summation Register 2 (SUMR2) 7 6 5 4 3 2 1 0 SUMR2 bits 7-0 Reset Value 00H SFR E4H Summation Register 2. This is the most significant byte of the lowest 24 bits of the summation register or bits 16-23. Summation Register 3 (SUMR3) 7 SFR E5H SUMR3 bits 7-0 6 5 4 3 MSB 1 0 Reset Value 00H Summation Register 3. This is the most significant byte of the 32-bit summation register or bits 24-31. MSC1200 SBAS289E 2 www.ti.com 51 Offset DAC Register (ODAC) 7 6 5 4 3 2 1 0 SFR E6H Reset Value 00H ODAC bit7-0 Offset DAC Register. This register will shift the input by up to half of the ADC full-scale input range. The offset DAC value is summed with the ADC input prior to conversion. Writing 00H or 80H to ODAC turns off the Offset DAC. bit 7 Offset DAC Sign bit. 0 = Positive 1 = Negative bit 6-0 Offset = − VREF ODAC[6 : 0] bit 7 • • (−1) 2 • PGA 127 NOTE: ODAC cannot be used to offset the input so that the buffer can be used for AGND signals. Low Voltage Detect Control (LVDCON) SFR E7H ALVDIS bit 7 7 6 5 4 3 2 1 0 Reset Value ALVDIS 0 0 0 1 1 1 1 8FH Analog Low Voltage Detect Disable. 0 = Enable Detection of Low Analog Supply Voltage (ALVD interrupt set when AVDD < 2.8V). 1 = Disable Detection of Low Analog Supply Voltage. Extended Interrupt Enable (EIE) SFR E8H EWDI bit 4 7 6 5 4 3 2 1 0 Reset Value 1 1 1 EWDI EX5 EX4 EX3 EX2 E0H Enable Watchdog Interrupt. This bit enables/disables the watchdog interrupt. The Watchdog timer is enabled by the WDTCON (SFR FFH) and PDCON (SFR F1H) registers. 0 = Disable the Watchdog Interrupt 1 = Enable Interrupt Request Generated by the Watchdog Timer EX5 bit 3 External Interrupt 5 Enable. This bit enables/disables external interrupt 5. 0 = Disable External Interrupt 5 1 = Enable External Interrupt 5 EX4 bit 2 External Interrupt 4 Enable. This bit enables/disables external interrupt 4. 0 = Disable External Interrupt 4 1 = Enable External Interrupt 4 EX3 bit 1 External Interrupt 3 Enable. This bit enables/disables external interrupt 3. 0 = Disable External Interrupt 3 1 = Enable External Interrupt 3 EX2 bit 0 External Interrupt 2 Enable. This bit enables/disables external interrupt 2. 0 = Disable External Interrupt 2 1 = Enable External Interrupt 2 52 MSC1200 www.ti.com SBAS289E Hardware Product Code Register 0 (HWPC0) SFR E9H 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 MEMORY 0000_000xB HWPC0.7-0 bits 7-0 Hardware Product Code LSB. Read only. MEMORY SIZE MODEL FLASH MEMORY 0 1 MSC1200Y2 MSC1200Y3 4kB 8kB Hardware Product Code Register 1 (HWPC1) SFR EAH 7 6 5 4 3 2 1 0 Reset Value 0 0 1 0 0 0 0 0 20H HWPC1.7-0 bits 7-0 Hardware Product Code MSB. Read only. Hardware Version Register (HWVER) 7 6 5 4 3 2 1 0 Reset Value SFR EBH Flash Memory Control (FMCON) SFR EEH 7 6 5 4 3 2 1 0 Reset Value 0 PGERA 0 FRCM 0 BUSY 1 0 02H PGERA bit 6 Page Erase. Available in both user and program modes. 0 = Disable Page Erase Mode 1 = Enable Page Erase Mode FRCM bit 4 Frequency Control Mode. The bypass is only used for slow clocks to save power. 0 = Bypass (default) 1 = Use Delay Line. Saves power (Recommended). BUSY bit 2 Write/Erase BUSY Signal. 0 = Idle or Available 1 = Busy Flash Memory Timing Control Register (FTCON) SFR EFH 7 6 5 4 3 2 1 0 Reset Value FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 A5H 1 0 Reset Value Refer to Flash Timing Characteristics FER3-0 bits 7-4 Set Erase. Flash Erase Time = (1 + FER) • (MSEC + 1) • tCLK. 11ms industrial temperature range. 5ms commercial temperature range. FWR3-0 bits 3-0 Set Write. Flash Write Time = (1 + FWR) • (USEC + 1) • 5 • tCLK. 30µs to 40µs. B Register (B) 7 6 5 4 3 2 SFR F0H B bits 7-0 00H B Register. This register serves as a second accumulator for certain arithmetic operations. MSC1200 SBAS289E www.ti.com 53 Power-Down Control Register (PDCON) SFR F1H 7 6 5 4 3 2 1 0 Reset Value PDICLK PDIDAC PDI2C 0 PDADC PDWDT PDSPI PDSPI 6FH Turning peripheral modules off puts the MSC1200 in the lowest power mode. PDICLK bit 7 Internal Clock Control. 0 = Internal Oscillator and PLL On (Internal Oscillator or PLL mode) 1 = Internal Oscillator and PLL Power Down (External Clock mode) PDIDAC bit 6 IDAC Control. 0 = IDAC On 1 = IDAC Power Down (default) PDI2C bit 5 I2C Control. 0 = I2C On (only when PDSPI = 1) 1 = I2C Power Down (default) PDADC bit 3 ADC Control. 0 = ADC On 1 = ADC, VREF, and Summation registers are powered down (default). PDWDT bit 2 Watchdog Timer Control. 0 = Watchdog Timer On 1 = Watchdog Timer Power Down (default) PDST bit 1 System Timer Control. 0 = System Timer On 1 = System Timer Power Down (default) PDSPI bit 0 SPI Control. 0 = SPI System On 1 = SPI System Power Down (default) PSEN/ALE Select (PASEL) SFR F2H PSEN4-0 bits 7-3 7 6 5 4 3 2 1 0 Reset Value PSEN4 PSEN3 PSEN2 PSEN1 PSEN0 0 0 0 00H PSEN Mode Select. Defines the output on P3.6 in User Application mode or Serial Flash Programming mode. 00000: General-Purpose I/O (default) 00001: SYSCLK 00011: Internal PSEN (refer to Figure 3 for timing) 00101: Internal ALE (refer to Figure 3 for timing) 00111: fOSC(buffered XIN oscillator clock) 01001: Memory WR (MOVX write) 01011: T0 Out (overflow)(1) 01101: T1 Out (overflow)(1) 01111: fMOD(2) 10001: SYSCLK/2 (toggles on rising edge)(2) 10011: Internal PSEN/2(2) 10101: Internal ALE/2(2) 10111: fOSC/2(2) 11001: Memory WR/2 (MOVX write)(2) 11011: T0 Out/2 (overflow)(2) 11101: T1 Out/2 (overflow)(2) 11111: fMOD/2(2) NOTES: (1) On period of these signals equal to tCLK. (2) Duty cycle is 50%. 54 MSC1200 www.ti.com SBAS289E Phase Lock Loop Low Register (PLLL) SFR F4H PLL7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value PLL7 PLL6 PLL5 PLL4 PLL3 PLL2 PLL1 PLL0 C1H PLL Counter Value Least Significant Bit. PLL Frequency = External Crystal Frequency • PLL9:0 Phase Lock Loop High Register (PLLH) SFR F5H 7 6 5 4 3 2 1 0 Reset Value CLKSTAT2 CLKSTAT1 CLKSTAT0 PLLLOCK 0 0 PLL9 PLL8 x1H CLKSTAT2-0 Active Clock Status (read only). Derived from HCR2 setting; refer to Table II. bits 7-5 000: Reserved 001: Reserved 010: Reserved 011: External Clock Mode 100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status) 101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status) 110: Internal Oscillator High-Frequency (HF) Mode 111: Internal Oscillator Low-Frequency (LF) Mode PLLLOCK bit 4 PLL Lock Status and Status Enable. For Write (PLL Lock Status Enable): 0 = No Effect 1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid). For Read (PLL Lock Status): 0 = PLL Not Locked (PLL may be inactive; refer to Table II for active clock mode) 1 = PLL Locked (PLL is active clock) PLL9-8 bits 1-0 PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4H) Analog Clock (ACLK) SFR F6H FREQ6-0 bits 6-0 7 6 5 4 3 2 1 0 Reset Value 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03H Clock Frequency – 1. This value + 1 divides the system clock to create the ADC clock. fCLK fOSC fACLK = , where fCLK = . SYSCLK Divider (ACLK + 1) f ACLK fMOD = 64 fMOD ADC Data Rate = fDATA = Decimation Ratio System Reset Register (SRST) SFR F7H RSTREQ bit 0 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 RSTREQ 00H Reset Request. Setting this bit to 1 and then clearing to 0 will generate a system reset. MSC1200 SBAS289E www.ti.com 55 Extended Interrupt Priority (EIP) SFR F8H 7 6 5 4 3 2 1 0 Reset Value 1 1 1 PWDI PX5 PX4 PX3 PX2 E0H PWDI bit 4 Watchdog Interrupt Priority. This bit controls the priority of the watchdog interrupt. 0 = The watchdog interrupt is low priority. 1 = The watchdog interrupt is high priority. PX5 bit 3 External Interrupt 5 Priority. This bit controls the priority of external interrupt 5. 0 = External interrupt 5 is low priority. 1 = External interrupt 5 is high priority. PX4 bit 2 External Interrupt 4 Priority. This bit controls the priority of external interrupt 4. 0 = External interrupt 4 is low priority. 1 = External interrupt 4 is high priority. PX3 bit 1 External Interrupt 3 Priority. This bit controls the priority of external interrupt 3. 0 = External interrupt 3 is low priority. 1 = External interrupt 3 is high priority. PX2 bit 0 External Interrupt 2 Priority. This bit controls the priority of external interrupt 2. 0 = External interrupt 2 is low priority. 1 = External interrupt 2 is high priority. Seconds Timer Interrupt (SECINT) SFR F9H 7 6 5 4 3 2 1 0 Reset Value WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 7FH This system clock is divided by the value of the 16-bit register MSECH:MSECL. Then that 1ms timer tick is divided by the register HMSEC which provides the 100ms signal used by this seconds timer. Therefore, this seconds timer can generate an interrupt which occurs from 100ms to 12.8 seconds. Reading this register will clear the Seconds Interrupt. This Interrupt can be monitored in the AIE register. WRT bit 7 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The SEC value is loaded when the current count expires. 1 = Write Immediately. The counter is loaded once the CPU completes the write operation. SECINT6-0 Seconds Count. Normal operation would use 100ms as the clock interval. bits 6-0 Seconds Interrupt = (1 + SEC) • (HMSEC + 1) • (MSEC + 1) • tCLK. Milliseconds Interrupt (MSINT) SFR FAH 7 6 5 4 3 2 1 0 Reset Value WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 7FH The clock used for this timer is the 1ms clock which results from dividing the system clock by the values in registers MSECH:MSECL. Reading this register will clear MSINT. WRT bit 7 Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0. 0 = Delay Write Operation. The MSINT value is loaded when the current count expires. 1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation. MSINT6-0 bits 6-0 Seconds Count. Normal operation would use 1ms as the clock interval. MS Interrupt Interval = (1 + MSINT) • (MSEC + 1) • tCLK 56 MSC1200 www.ti.com SBAS289E One Microsecond Register (USEC) SFR FBH FREQ5-0 bits 5-0 7 6 5 4 3 2 1 0 Reset Value 0 0 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 03H Clock Frequency – 1. This value + 1 divides the system clock to create a 1µs Clock. USEC = CLK/(FREQ + 1). This clock is used to set Flash write time. See FTCON (SFR EFH). One Millisecond Low Register (MSECL) SFR FCH MSECL7-0 bits 7-0 7 6 5 4 3 2 1 0 Reset Value MSECL7 MSECL6 MSECL5 MSECL4 MSECL3 MSECL2 MSECL1 MSECL0 9FH One Millisecond Low. This value in combination with the next register is used to create a 1ms Clock. 1ms Clock = (MSECH • 256 + MSECL + 1) • tCLK. This clock is used to set Flash erase time. See FTCON (SFR EFH). One Millisecond High Register (MSECH) SFR FDH 7 6 5 4 3 2 1 0 Reset Value MSECH7 MSECH6 MSECH5 MSECH4 MSECH3 MSECH2 MSECH1 MSECH0 0FH MSECH7-0 One Millisecond High. This value in combination with the previous register is used to create a 1ms clock. bits 7-0 1ms = (MSECH • 256 + MSECL + 1) • tCLK. One Hundred Millisecond Register (HMSEC) SFR FEH 7 6 5 4 3 2 1 0 Reset Value HMSEC7 HMSEC6 HMSEC5 HMSEC4 HMSEC3 HMSEC2 HMSEC1 HMSEC0 63H HMSEC7-0 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock. bits 7-0 100ms = (MSECH • 256 + MSECL + 1) • (HMSEC + 1) • tCLK. Watchdog Timer Register (WDTCON) SFR FFH 7 6 5 4 3 2 1 0 Reset Value EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 00H EWDT bit 7 Enable Watchdog (R/W). Write 1/Write 0 sequence sets the Watchdog Enable Counting bit. DWDT bit 6 Disable Watchdog (R/W). Write 1/Write 0 sequence clears the Watchdog Enable Counting bit. RWDT bit 5 Reset Watchdog (R/W). Write 1/Write 0 sequence restarts the Watchdog Counter. WDCNT4-0 bits 4-0 Watchdog Count (R/W). Watchdog expires in (WDCNT + 1) • HMSEC to (WDCNT + 2) • HMSEC, if the sequence is not asserted. There is an uncertainty of 1 count. NOTE: If HCR0.3 (EWDR) is set and the watchdog timer expires, a system reset is generated. If HCR0.3 (EWDR) is cleared and the watchdog timer expires, an interrupt is generated (see Table VII). MSC1200 SBAS289E www.ti.com 57 PACKAGE OPTION ADDENDUM www.ti.com 25-Nov-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY MSC1200Y2PFBR ACTIVE TQFP PFB 48 2000 MSC1200Y2PFBT ACTIVE TQFP PFB 48 250 MSC1200Y3PFBR ACTIVE TQFP PFB 48 2000 MSC1200Y3PFBT ACTIVE TQFP PFB 48 250 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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