ICST ICS843AG-106 106.25mhz, lvcmos, lvpecl dual output oscillator Datasheet

ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
GENERAL DESCRIPTION
FEATURES
The ICS843-106 is a Fibre Channel Dual
Output Oscillator and a member of the
HiPerClockS™
HiPerClocks TM family of high perfor mance
devices from ICS. The ICS843-106 uses a
25MHz crystal to synthesize 106.25MHz.
The ICS843-106 has excellent jitter performance. The
ICS843-106 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
• One LVCMOS/LVTTL output, 15Ω output impedance
One LVPECL output pair
ICS
• Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
• Output frequency: 106.25MHz
• Random jitter: 3ps (typical)
• Deterministic jitter: 0.24ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
LVCMOS
106.25MHz
Q0
25MHz
XTAL_IN
Clock
Synthesizer
XTAL_OUT
LVPECL
106.25MHz
VCC
XTAL_IN
XTAL_OUT
VEE
1
2
3
4
8
7
6
5
Q1
nQ1
VCCO
Q0
ICS843-106
Q1
nQ1
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
ICS843-106
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
843AG-106
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1
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
Power
4
VCC
XTAL_IN,
XTAL_OUT
VEE
5
Q0
Output
Description
6
VCCO
Power
Positive supply pin.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Negative supply pin.
Single-ended clock output. LVCMOS/LVTTL interface levels.
15Ω output impedance.
Output supply pin.
7, 8
nQ1, Q1
Output
Differential LVPECL output pair.
2, 3
Input
Power
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
ROUT
Output Impedance
843AG-106
Test Conditions
Minimum
Q0
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2
Typical
Maximum
Units
4
pF
15
Ω
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO (LVPECL)
Continuous Current
50mA
Surge Current
100mA
Package Thermal Impedance, θJA
8 Lead TSSOP
101.7°C/W (0 mps)
8 Lead SOIC
112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Positive Supply Voltage
3.0
3.3
3.6
V
VCCO
Output Supply Voltage
3.0
3.3
3.6
V
IEE
Power Supply Current
116
mA
ICC
Power Supply Current
96
mA
ICCO
Output Supply Current
24
mA
Maximum
Units
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
Test Conditions
Minimum
Typical
2.6
V
Output Low Voltage; NOTE 1
VOL
NOTE 1: Outputs terminated with 50Ω to VCCO/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
0.5
V
Maximum
Units
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCCO - 2.0
VCCO - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
843AG-106
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3
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TABLE 4. CRYSTAL CHARACTERISTICS (NOTE 1)
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
Frequency
25
MHz
Frequency Tolerance
Frequency Stability Over Operating
Temperature Range
Load Capacitance (CL); NOTE 2
±30
ppm
±30
ppm
18
pF
Aging for 10 Years
±15
ppm
Drive Level
NOTE 1: Using an HC49/US SMD package, the parameters shown above target ±100ppm accuracy.
NOTE 2: See Cr ystal Input Interface in the Application Information Section.
1
mW
Maximum
Units
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±0.3V, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
Test Conditions
Minimum
Typical
106.25
MH z
tDJ
Deterministic Jitter ; NOTE 1
0.24
ps
tRJ
3
ps
3.12
ps
tp-p
Random Jitter ; NOTE 1
RMS of Total Distribution (σ);
NOTE 2
Peak-to-Peak Jitter ; NOTE 1
24
ps
tOSC
Oscillation Star t Up Time
t R / tF
Output
Rise/Fall Time
tRMS
10
ms
100
500
ps
250
800
ps
odc
Output Duty Cycle
48
NOTE 1: Measured using Wavecrest SIA-3000.
NOTE 2: Measured using Wavecrest SIA-3000, Tj @ 10e-12BER result divided by 14.
52
%
843AG-106
Q0
Q1/nQ1
20% to 80%
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REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
PARAMETER MEASUREMENT INFORMATION
1.65V ± 0.15V
2V
SCOPE
VCC,
VCCO
VCC,
VCCO
Qx
SCOPE
Qx
LVCMOS
LVPECL
nQx
GND
VEE
-1.65V ± 0.15V
-1.3V ± 0.3V
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
V
nQ1
CC
2
Q0
Q1
t PW
t
odc =
t PW
t
PERIOD
t PW
odc =
x 100%
t PW
x 100%
t PERIOD
t PERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
PERIOD
80%
80%
80%
VSW I N G
Clock
Outputs
20%
20%
tR
Clock
Outputs
tF
LVCMOS OUTPUT RISE/FALL TIME
843AG-106
20%
20%
tR
tF
LVPECL OUTPUT RISE/FALL TIME
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5
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
LVCMOS OUTPUT:
An unused LVCMOS output should be terminated with 100Ω
to ground as close as possible to the device.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
CRYSTAL INPUT INTERFACE
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
The ICS843-106 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
XTAL_OUT
C1
12p
X1
18pF Parallel Cry stal
XTAL_IN
C2
12p
Figure 1. CRYSTAL INPUt INTERFACE
843AG-106
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6
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
FREQUENCY STABILITY
The table shown provides a basic guideline in selecting
the proper quartz crystal that meets a timing budget of
±100ppm. For more information on selecting the proper
Parameter
Typical
Units
Frequency Tolerance
±30
ppm
Frequency Stability
±30
ppm
Aging for 10 Years
±15
ppm
Accuracy of ICS Oscillator
±10
ppm
Load Capacitance Accuracy
±3
ppm
Total Overall Timing Error
±88
ppm
crystal, see the application note, Crystal Timing Budget
and Accuracy for FemtoClock™ .
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
drive 50Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
FOUT
125Ω
FIN
125Ω
Zo = 50Ω
Zo = 50Ω
50Ω
RTT =
1
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FOUT
50Ω
VCC - 2V
FIN
Zo = 50Ω
RTT
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
843AG-106
84Ω
FIGURE 2B. LVPECL OUTPUT TERMINATION
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7
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843-106.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843-106 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 0.3V = 3.6V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.6V * 116mA = 417.6mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 417.6mW + 30mW = 447.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6A
below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.448W * 90.5°C/W = 110.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 6B. THERMAL RESISTANCE θJA FOR 8 LEAD SOIC FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843AG-106
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REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CCO_MAX
•
-V
OH_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
CC_MAX
– 0.9V
) = 0.9V
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.7V
) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (V _MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) =
L
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
))/R ] * (V
OL_MAX
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
843AG-106
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9
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 7B. θJAVS. AIR FLOW TABLE 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843-106 is: 2376
843AG-106
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10
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Minimum
N
A
SYMBOL
Maximum
8
Millimeters
MINIMUM
N
--
1.20
A
MAXIMUM
8
1.35
1.75
A1
0.05
0.15
A1
0.10
0.25
A2
0.80
1.05
B
0.33
0.51
b
0.19
0.30
C
0.19
0.25
c
0.09
0.20
D
4.80
5.00
D
2.90
3.10
E
3.80
4.00
4.50
H
5.80
6.20
E
E1
6.40 BASIC
4.30
e
e
0.65 BASIC
1.27 BASIC
h
0.25
0.50
L
0.45
0.75
L
0.40
1.27
α
0°
8°
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
843AG-106
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11
REV. A JANUARY 10, 2006
ICS843-106
Integrated
Circuit
Systems, Inc.
106.25MHZ, LVCMOS, LVPECL
DUAL OUTPUT OSCILLATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS843AG-106
3A106
8 lead TSSOP
tube
0°C to 70°C
ICS843AG-106T
3A106
8 lead TSSOP
2500 tape & reel
0°C to 70°C
ICS843AG-106LF
TBD
8 lead "Lead-Free" TSSOP
tube
0°C to 70°C
ICS843AG-106LFT
TBD
8 lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
ICS843AM-106
TBD
8 lead SOIC
tube
0°C to 70°C
ICS843AM-106T
TBD
8 lead SOIC
2500 tape & reel
0°C to 70°C
ICS843AM-106LF
TBD
8 lead "Lead-Free" SOIC
tube
0°C to 70°C
ICS843AM-106LFT
TBD
8 lead "Lead-Free" SOIC
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
843AG-106
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REV. A JANUARY 10, 2006