bq4285 Real-Time Clock (RTC) With NVRAM Control Features ➤ Direct clock/calendar replacement for IBM ® AT-compatible computers and other applications ➤ Functionally compatible with the DS1285 - Closely matches MC146818A pin configuration ➤ Calendar in day of the week, day of the month, months, and years, with automatic leap-year adjustment ➤ Time of day in seconds, minutes, and hours - 12- or 24-hour format Optional daylight saving adjustment ➤ 114 bytes of general nonvolatile storage ➤ BCD or binary format for clock and calendar data ➤ Automatic backup and writeprotect control to external SRAM ➤ Programmable square wave output ➤ 160 ns cycle time allows fast bus operation ➤ Three individually maskable interrupt event flags: ➤ Less than 0.5 µA load under battery operation ➤ 14 bytes for clock/calendar and control - Periodic rates from 122 µs to 500 ms - Time-of-day alarm once per second to once per day - End-of-clock update cycle ➤ 24-pin plastic DIP or SOIC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 The CMOS bq4285 is a low-power microprocessor peripheral providing a time-of-day clock and 100-year calendar with alarm features and battery operation. Other features include three maskable interrupt sources, square wave output, and 114 bytes of general nonvolatile storage. The bq4285 write-protects the clock, calendar, and storage registers during power failure. A backup battery then maintains data and operates the clock and calendar. The bq4285 is a fully compatible realtime clock for IBM AT-compatible computers and other applications. The only external components are a 32.768kHz crystal and a backup battery. The bq4285 integrates a batterybackup controller to make a standard CMOS SRAM nonvolatile during power-fail conditions. During powerfail, the bq4285 automatically writeprotects the external SRAM and provides a VCC output sourced from the clock backup battery. Pin Names Pin Connections VOUT X1 X2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS General Description VCC SQW CEOUT CEIN BC INT RST DS VSS R/W AS CS 24-Pin DIP or SOIC 28-Pin PLCC No longer available PN428501.eps SLUS002A JUNE 1991 - REVISED MAY 2004 1 AD0–AD7 Multiplexed address/data input/output MOT Bus type select input CS AS DS R/W INT RST SQW BC X1–X2 NC CEIN CEOUT VOUT VCC VSS Chip select input Address strobe input Data strobe input Read/write input Interrupt request output Reset input Square wave output 3V backup cell input Crystal inputs No connect RAM chip enable input RAM chip enable output Supply output +5V supply Ground bq4285 Block Diagram CS Pin Descriptions AD0–AD7 Chip select input CS should be driven low and held stable during the data-transfer phase of a bus cycle accessing the bq4285. Multiplexed address/data input/ output The bq4285 bus cycle consists of two phases: the address phase and the datatransfer phase. The address phase precedes the data-transfer phase. During the address phase, an address placed on AD0–AD7 is latched into the bq4285 on the falling edge of the AS signal. During the data-transfer phase of the bus cycle, the AD0–AD7 pins serve as a bidirectional data bus. MOT Table 1. Bus Setup Connect to VSS for correct operation Bus Type Intel 2 MOT DS R/W AS Level Equivalent Equivalent Equivalent VSS RD, MEMR, or I/OR WR, MEMW, or I/OW ALE bq4285 AS Reset may be disabled by connecting RST to VCC. This allows the control bits to retain their states through powerdown/power-up cycles. Address strobe input AS serves to demultiplex the address/data bus. The falling edge of AS latches the address on AD0–AD7. This demultiplexing process is independent of the CS signal. DS SQW SQW may output a programmable frequency square-wave signal during normal (VCC valid) system operation. Any one of the 13 specific frequencies may be selected through register A. This pin is held low when the square-wave enable bit (SQWE) in register B is 0 (see the Control/Status Registers section). Data strobe input With MOT = VSS, the DS input is provided a signal similar to RD, MEMR, or I/OR in an BC Intel-based system. The falling edge on DS is used to enable the outputs during a read cycle. R/W 3V backup cell input BC should be connected to a 3V backup cell for RTC operation and storage register nonvolatility in the absence of power. When VCC slews down past VBC (3V typical), the integral control circuitry switches the power source to BC. When VCC returns above VBC, the power source is switched to VCC. Upon power-up, a voltage within the VBC range must be present on the BC pin for the oscillator to start up. Read/write input With MOT = VSS, R/W is provided a signal similar to WR, MEMW, or I/OW in an Intelbased system. The rising edge on R/W latches data into the bq4285. X1–X2 CEIN INT Crystal inputs The X1–X2 inputs are provided for an external 32.768Khz quartz crystal, Daiwa DT-26 or equivalent, with 6pF load capacitance. A trimming capacitor may be necessary for extremely precise time-base generation. External RAM chip enable input, active low Interrupt request output CEIN should be driven low to enable the controlled external RAM. CEIN is internally pulled up with a 50KΩ resistor. INT is an open-drain output. INT is asserted low when any event flag is set and the corresponding event enable bit is also set. INT becomes high-impedance whenever register C is read (see the Control/Status Registers section). RST Square-wave output CEOUT External RAM chip enable output, active low When power is valid, CEOUT reflects CEIN. Reset input VOUT The bq4285 is reset when RST is pulled low. When reset, INT becomes highimpedance, and the bq4285 is not accessible. Table 4 in the Control/Status Registers section lists the register bits that are cleared by a reset. Supply output VOUT provides the higher of VCC or VBC, switched internally, to supply external RAM. 3 VCC +5V supply VSS Ground bq4285 Functional Description date period (see Figure 2). The alarm flag bit may also be set during the update cycle. Address Map The bq4285 copies the local register updates into the user buffer accessed by the host processor. When a 1 is written to the update transfer inhibit bit (UTI) in register B, the user copy of the clock and calendar bytes remains unchanged, while the local copy of the same bytes continues to be updated every second. The bq4285 provides 14 bytes of clock and control/status registers and 114 bytes of general nonvolatile storage. Figure 1 illustrates the address map for the bq4285. Update Period The update-in-progress bit (UIP) in register A is set tBUC time before the beginning of an update cycle (see Figure 2). This bit is cleared and the update-complete flag (UF) is set at the end of the update cycle. The update period for the bq4285 is one second. The bq4285 updates the contents of the clock and calendar locations during the update cycle at the end of each up- Figure 1. Address Map Figure 2. Update Period Timing and UIP 4 bq4285 c. Programming the RTC Write the appropriate value to the hour format (HF) bit. The time-of-day, alarm, and calendar bytes can be written in either the BCD or binary format (see Table 2). 2. Write new values to all the time, alarm, and calendar locations. These steps may be followed to program the time, alarm, and calendar: 3. Clear the UTI bit to allow update transfers. 1. On the next update cycle, the RTC updates all 10 bytes in the selected format. Modify the contents of register B: a. Write a 1 to the UTI bit to prevent transfers between RTC bytes and user buffer. b. Write the appropriate value to the data format (DF) bit to select BCD or binary format for all time, alarm, and calendar bytes. Table 2. Time, Alarm, and Calendar Formats Range Address RTC Bytes Decimal Binary Binary-Coded Decimal 0 Seconds 0–59 00H–3BH 00H–59H 1 Seconds alarm 0–59 00H–3BH 00H–59H 2 Minutes 0–59 00H–3BH 00H–59H 3 Minutes alarm 0–59 00H–3BH 00H–59H 4 Hours, 12-hour format 1–12 01H–OCH AM; 81H–8CH PM 01H–12H AM; 81H–92H PM Hours, 24-hour format 0–23 00H–17H 00H–23H Hours alarm, 12-hour format 1–12 01H–OCH AM; 81H–8CH PM 01H–12H AM; 81H–92H PM Hours alarm, 24-hour format 0–23 00H–17H 00H–23H 6 Day of week (1=Sunday) 1–7 01H–07H 01H–07H 7 Day of month 1–31 01H–1FH 01H–31H 8 Month 1–12 01H–0CH 01H–12H 9 Year 0–99 00H–63H 00H–99H 5 5 bq4285 The update-ended interrupt, which occurs at the end of each update cycle Square-Wave Output ■ The bq4285 divides the 32.768kHz oscillator frequency to produce the 1 Hz update frequency for the clock and calendar. Thirteen taps from the frequency divider are fed to a 16:1 multiplexer circuit. The output of this mux is fed to the SQW output and periodic interrupt generation circuitry. The four least-significant bits of register A, RS0–RS3, select among the 13 taps (see Table 3). The square-wave output is enabled by writing a 1 to the square-wave enable bit (SQWE) in register B. Each of the three interrupt events is enabled by an individual interrupt-enable bit in register B. When an event occurs, its event flag bit in register C is set. If the corresponding event enable bit is also set, then an interrupt request is generated. The interrupt request flag bit (INTF) of register C is set with every interrupt request. Reading register C clears all flag bits, including INTF, and makes INT high-impedance. Interrupts Two methods can be used to process bq4285 interrupt events: The bq4285 allows three individually selected interrupt events to generate an interrupt request. These three interrupt events are: ■ Enable interrupt events and use the interrupt request output to invoke an interrupt service routine. ■ The periodic interrupt, programmable to occur once every 122 µs to 500 ms ■ ■ The alarm interrupt, programmable to occur once per second to once per day Do not enable the interrupts and use a polling routine to periodically check the status of the flag bits. The individual interrupt sources are described in detail in the following sections. Table 3. Square-Wave Frequency/Periodic Interrupt Rate Register A Bits Square Wave RS3 RS2 RS1 RS0 Frequency 0 0 0 0 None 0 0 0 1 256 0 0 1 0 128 Hz 0 0 1 1 8.192 kHz 122.070 µs 0 1 0 0 4.096 kHz 244.141 µs 0 1 0 1 2.048 kHz 488.281 µs 0 1 1 0 1.024 kHz 976.5625 0 1 1 1 512 Hz 1.95315 ms 1 0 0 0 256 Hz 3.90625 ms 1 0 0 1 128 Hz 7.8125 ms 1 0 1 0 64 Hz 15.625 ms 1 0 1 1 32 Hz 31.25 ms 1 1 0 0 16 Hz 62.5 ms 1 1 0 1 8 Hz 125 ms 1 1 1 0 4 Hz 250 ms 1 1 1 1 2 Hz 500 ms 6 Units Periodic Interrupt Period Units None Hz 3.90625 ms 7.8125 ms µs bq4285 Periodic Interrupt Update Cycle Interrupt The mux output used to drive the SQW output also drives the interrupt-generation circuitry. If the periodic interrupt event is enabled by writing a 1 to the periodic interrupt enable bit (PIE) in register C, an interrupt request is generated once every 122µs to 500ms. The period between interrupts is selected by the same bits in register A that select the square wave frequency (see Table 3). The update cycle ended flag bit (UF) in register C is set to a 1 at the end of an update cycle. If the update interrupt enable bit (UIE) of register B is 1, and the update transfer inhibit bit (UTI) in register B is 0, then an interrupt request is generated at the end of each update cycle. Accessing RTC bytes Alarm Interrupt Time and calendar bytes read during an update cycle may be in error. Three methods to access the time and calendar bytes without ambiguity are: During each update cycle, the RTC compares the hours, minutes, and seconds bytes with the three corresponding alarm bytes. If a match of all bytes is found, the alarm interrupt event flag bit, AF in register C, is set to 1. If the alarm event is enabled, an interrupt request is generated. An alarm byte may be removed from the comparison by setting it to a “don’t care” state. An alarm byte is set to a “don’t care” state by writing a 1 to each of its two mostsignificant bits. A “don’t care” state may be used to select the frequency of alarm interrupt events as follows: ■ If none of the three alarm bytes is “don’t care,” the frequency is once per day, when hours, minutes, and seconds match. ■ If only the hour alarm byte is “don’t care,” the frequency is once per hour, when minutes and seconds match. ■ If only the hour and minute alarm bytes are “don’t care,” the frequency is once per minute, when seconds match. ■ If the hour, minute, and second alarm bytes are “don’t care,” the frequency is once per second. ■ Enable the update interrupt event to generate interrupt requests at the end of the update cycle. The interrupt handler has a maximum of 999ms to access the clock bytes before the next update cycle begins (see Figure 3). ■ Poll the update-in-progress bit (UIP) in register A. If UIP = 0, the polling routine has a minimum of tBUC time to access the clock bytes (see Figure 3). ■ Use the periodic interrupt event to generate interrupt requests every tPI time, such that UIP = 1 always occurs between the periodic interrupts. The interrupt handler will have a minimum of tPI/2 + tBUC time to access the clock bytes (see Figure 3). Oscillator Control When power is first applied to the bq4285 and VCC is above VPFD, the internal oscillator and frequency divider are turned on by writing a 010 pattern to bits 4 through 6 of register A. A pattern of 11X turns the oscillator on but keeps the frequency divider disabled. Any other pattern to these bits keeps the oscillator off. Figure 3. Update-Ended/Periodic Interrupt Relationship 7 bq4285 As the supply continues to fall past VPFD, an internal switching device forces VOUT to the external backup energy source. CEOUT is held high by the VOUT energy source. Power-Down/Power-Up Cycle The bq4285 continuously monitors V CC for out-oftolerance. During a power failure, when VCC falls below VPFD (4.17V typical), the bq4285 write-protects the clock and storage registers. When VCC is below VBC (3V typical), the power source is switched to BC. RTC operation and storage data are sustained by a valid backup energy source. When VCC is above VBC, the power source is VCC. Write-protection continues for tCSR time after VCC rises above VPFD. During power-up, VOUT is switched back to the 5V supply as VCC rises above the backup cell input voltage sourcing VOUT. CEOUT is held inactive for time tCER (200ms maximum) after the power supply has reached VPFD, independent of the CEIN input, to allow for processor stabilization. An external CMOS static RAM is battery-backed using the VOUT and chip enable output pins from the bq4285. As the voltage input VCC slows down during a power failure, the chip enable output, CEOUT, is forced inactive independent of the chip enable input CEIN. During power-valid operation, the CEIN input is passed through to the CEOUT output with a propagation delay of less than 10ns. This activity unconditionally write-protects the external SRAM as VCC falls below VPFD. If a memory access is in process to the external SRAM during power-fail detection, that memory cycle continues to completion before the memory is write-protected. If the memory cycle is not terminated within time tWPT (30µs maximum), the chip enable output is unconditionally driven high, write-protecting the controlled SRAM. A primary backup energy source input is provided on the bq4285. The BC input accepts a 3V primary battery, typically some type of lithium chemistry. To prevent battery drain when there is no valid data to retain, VOUT and CEOUT are internally isolated from BC by the initial connection of a battery. Following the first application of VCC above VPFD, this isolation is broken, and the backup cell provides power to VOUT and CEOUT for the external SRAM. Figure 4 shows the hardware hookup for the external RAM. Figure 4. External RAM Hookup to the bq4285 RTC 8 bq4285 Control/Status Registers the frequency divider disabled. When 010 is written, the RTC begins its first update after 500ms. The four control/status registers of the bq4285 are accessible regardless of the status of the update cycle (see Table 4). UIP - Update Cycle Status 7 UIP Register A 7 UIP 6 OS2 5 OS1 Register A Bits 4 3 2 OS0 RS3 RS2 1 RS1 Register A programs: The frequency of the square-wave and the periodic event rate. ■ Oscillator operation. 7 UTI Status of the update cycle. 6 - 5 - 4 - 3 RS3 2 RS2 1 RS1 0 RS0 These bits select one of the 13 frequencies for the SQW output and the periodic interrupt rate, as shown in Table 3. 6 OS2 5 OS1 4 OS0 2 - 1 - 0 - 6 PIE 5 AIE Register B Bits 4 3 2 UIE SQWE DF 1 HF 0 DSE ■ Update cycle transfer operation ■ Square-wave output ■ Interrupt events ■ Daylight saving adjustment Register B selects: OS0–OS2 - Oscillator Control 7 - 3 - Register B enables: RS0–RS3 - Frequency Select 7 - 4 - Register B Register A provides: ■ 5 - This read-only bit is set prior to the update cycle. When UIP equals 1, an RTC update cycle may be in progress. UIP is cleared at the end of each update cycle. This bit is also cleared when the update transfer inhibit (UTI) bit in register B is 1. 0 RS0 ■ 6 - ■ 3 - 2 - 1 - Clock and calendar data formats All bits of register B are read/write. 0 - These three bits control the state of the oscillator and divider stages. A pattern of 010 enables RTC operation by turning on the oscillator and enabling the frequency divider. A pattern of 11X turns the oscillator on, but keeps Table 4. Control/Status Registers Bit Name and State on Reset Reg. Loc. (Hex) Read Write 1 7 (MSB) 6 5 4 3 2 1 0 (LSB) A 0A Yes Yes UIP na OS2 na OS1 na OS0 na B 0B Yes Yes UTI na PIE 0 AIE 0 UIE 0 SQWE 0 DF na HF na C 0C Yes No INTF 0 PF 0 AF 0 UF 0 - 0 - 0 - 0 - 0 D 0D Yes No VRT na - 0 - 0 - 0 - 0 - 0 - 0 - 0 Notes: na = not affected. 1. Except bit 7. 9 RS3 na RS2 na RS1 na RS0 na DSE na bq4285 UIE - Update Cycle Interrupt Enable DSE - Daylight Saving Enable 7 - 6 - 5 - 4 - 3 - 2 - 1 - 7 - 0 DSE This bit enables daylight-saving time adjustments when written to 1: ■ ■ 4 - 3 - 2 - 1 HF 7 - 0 - 5 AIE 4 - 3 - 2 - 1 - 0 - 0 = Disabled PIE - Periodic Interrupt Enable 4 - 3 - 2 DF 1 - 0 - 7 - This bit selects the numeric format in which the time, alarm, and calendar bytes are represented: 1 = Binary 6 PIE 5 - 4 - 3 - 2 - 1 - 0 - This bit enables an interrupt request due to a periodic interrupt event: 1 = Enabled 0 = BCD 0 = Disabled SQWE - Square-Wave Enable 6 - 6 - 1 = Enabled DF - Data Format 7 - 0 - This bit enables an interrupt request due to an alarm interrupt event: 0 = 12-hour format 5 - 1 - AIE - Alarm Interrupt Enable 1 = 24-hour format 6 - 2 - The UIE bit is automatically cleared when the UTI bit equals 1. This bit selects the time-of-day and alarm hour format: 7 - 3 - 0 = Disabled HF - Hour Format 5 - 4 UIE 1 = Enabled On the first Sunday in April, the time springs forward from 2:00:00 AM to 3:00:00 AM. 6 - 5 - This bit enables an interrupt request due to an update ended interrupt event: On the last Sunday in October, the first time the bq4285 increments past 1:59:59 AM, the time falls back to 1:00:00 AM. 7 - 6 - 5 - 4 - 3 SQWE UTI - Update Transfer Inhibit 2 - 1 - 0 - 7 UTI This bit enables the square-wave output: 6 - 5 - 4 - 3 - 2 - 1 - 0 - This bit inhibits the transfer of RTC bytes to the user buffer: 1 = Enabled 1 = Inhibits transfer and clears UIE 0 = Disabled and held low 0 = Allows transfer 10 bq4285 INTF - Interrupt Request Flag Register C 7 INTF 6 PF Register C Bits 5 4 3 AF UF 0 7 INTF 2 0 1 0 6 - 5 - 4 - 3 - 2 - 1 - 0 - 0 0 This flag is set to a 1 when any of the following is true: Register C is the read-only event status register. AIE = 1 and AF = 1 Bits 0–3 - Unused Bits 7 - 6 - PIE = 1 and PF = 1 5 - 4 - 3 0 2 0 1 0 0 0 UIE = 1 and UF = 1 Reading register C clears this bit. These bits are always set to 0. Register D UF - Update-Event Flag 7 - 6 - 5 - 4 UF 3 - 2 - 1 - 0 - 7 VRT 6 0 5 0 Register D Bits 4 3 0 0 2 0 1 0 0 0 This bit is set to a 1 at the end of the update cycle. Reading register C clears this bit. Register D is the read-only data integrity status register. AF - Alarm Event Flag Bits 0–6 - Unused Bits 7 - 6 - 5 AF 4 - 3 - 2 - 1 - 0 - 7 - This bit is set to a 1 when an alarm event occurs. Reading register C clears this bit. 6 0 5 0 4 0 3 0 2 0 1 0 0 0 3 - 2 - 1 - 0 - These bits are always set to 0. VRT - Valid RAM and Time 7 - 6 PF 5 - 4 - 3 - 2 - 1 - 0 - 7 VRT 6 - 5 - 4 - PF - Periodic Event Flag 1 = Valid backup energy source This bit is set to a 1 every tPI time, where tPI is the time period selected by the settings of RS0–RS3 in register A. Reading register C clears this bit. 0 = Backup energy source is depleted When the backup energy source is depleted (VRT = 0), data integrity of the RTC and storage registers is not guaranteed. 11 bq4285 Absolute Maximum Ratings Symbol Parameter Value Unit Conditions VCC DC voltage applied on VCC relative to VSS -0.3 to 7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 to 7.0 V VT ≤ VCC + 0.3 TOPR Operating temperature 0 to +70 °C Commercial TSTG Storage temperature -55 to +125 °C TBIAS Temperature under bias -40 to +85 °C TSOLDER Soldering temperature 260 °C Note: For 10 seconds Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. Recommended DC Operating Conditions (TA = TOPR) Minimum Typical Maximum Unit VCC Symbol Supply voltage 4.5 5.0 5.5 V VSS Supply voltage 0 0 0 V VIL Input low voltage -0.3 - 0.8 V VIH Input high voltage 2.2 - VCC + 0.3 V VBC Backup cell voltage 2.5 - 4.0 V Note: Parameter Typical values indicate operation at TA = 25°C. 12 bq4285 DC Electrical Characteristics (TA = TOPR, VCC = 5V ± 10%) Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes ILI Input leakage current - - ±1 µA VIN = VSS to VCC ILO Output leakage current - - ±1 µA AD0–AD7, INT, and SQW in high impedance, VOUT = VSS to VCC VOH Output high voltage 2.4 - - V IOH = -2.0 mA VOL Output low voltage - - 0.4 V IOL = 4.0 mA ICC Operating supply current - 7 15 mA VSO Supply switch-over voltage - VBC - V ICCB Battery operation current - 0.3 0.5 µA VPFD Power-fail-detect voltage 4.0 4.17 4.35 V - - V VOUT1 VOUT voltage VCC - 0.3V VOUT2 VOUT voltage VBC - 0.3V ICE Chip enable input current Note: Min. cycle, duty = 100%, IOH = 0mA, IOL = 0mA VBC = 3V, TA = 25°C, no load on VOUT or CEOUT IOUT = 100mA, VCC >VBC IOUT = 100µA, VCC < VBC - - µA 100 Internal 50K pull-up Typical values indicate operation at TA = 25°C, VCC = 5V or VBC = 3V. Crystal Specifications (DT-26 or Equivalent) Symbol Parameter Minimum Typical Maximum Unit fO Oscillation frequency - 32.768 - kHz CL Load capacitance - 6 - pF TP Temperature turnover point 20 25 30 °C k Parabolic curvature constant - - -0.042 ppm/°C Q Quality factor 40,000 70,000 - R1 Series resistance - - 45 KΩ C0 Shunt capacitance - 1.1 1.8 pF C0/C1 Capacitance ratio - 430 600 DL Drive level - - 1 µW ∆f/fO Aging (first year at 25°C) - 1 - ppm 13 bq4285 Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V) Parameter Minimum Typical Maximum Unit CI/O Symbol Input/output capacitance - - 7 pF VOUT = 0V CIN Input capacitance - - 5 pF VIN = 0V Note: Conditions This parameter is sampled and not 100% tested. AC Test Conditions Parameter Test Conditions Input pulse levels 0 to 3.0 V Input rise and fall times 5 ns Input and output timing reference levels 1.5 V (unless otherwise specified) Output load (including scope and jig) See Figures 5 and 6 Figure 5. Output Load A Figure 6. Output Load B 14 bq4285 Read/Write Timing (TA = TOPR, VCC = 5V ± 10%) Symbol Parameter Minimum Typical Maximum Unit tCYC Cycle time 160 - - ns tDSL DS low or RD/WR high time 80 - - ns tDSH DS high or RD/WR low time 55 - - ns tRWH R/W hold time 0 - - ns tRWS R/W setup time 10 - - ns tCS Chip select setup time 5 - - ns tCH Chip select hold time 0 - - ns tDHR Read data hold time 0 - 25 ns tDHW Write data hold time 0 - - ns tAS Address setup time 20 - - ns tAH Address hold time 5 - - ns tDAS Delay time, DS to AS rise 10 - - ns tASW Pulse width, AS high 30 - - ns tASD Delay time, AS to DS rise (RD/WR fall) 35 - - ns tOD Output data delay time from DS rise (RD fall) - - 50 ns tDW Write data setup time 30 - - ns tBUC Delay time before update - 244 - µs tPI Periodic interrupt time interval - - - - tUC Time of update cycle - 1 - µs 15 Notes See Table 3 bq4285 Motorola Bus Read/Write Timing (PLCC Package Only) Note: OBSOLETE 16 bq4285 Intel Bus Read Timing Intel Bus Write Timing 17 bq4285 Power-Down/Power-Up Timing (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit Conditions tF VCC slew from 4.5V to 0V 300 - - µs tR VCC slew from 0V to 4.5V 100 - - µs tCSR CS at VIH after power-up 20 - 200 ms Internal write-protection period after VCC passes VPFD on power-up. tWPT Write-protect time for external RAM 10 6 30 µs Delay after VCC slews down past VPFD before SRAM is write-protected. tCER Chip enable recovery time tCSR - tCSR ms Time during which external SRAM is write-protected after VCC passes VPFD on power-up. tCED Chip enable propagation delay to external SRAM - 7 10 ns Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode may affect data integrity. Power-Down/Power-Up Timing 18 bq4285 Interrupt Delay Timing (TA = TOPR) Symbol Parameter Minimum Typical Maximum Unit tRSW Reset pulse width 5 - - µs tIRR INT release from RST - - 2 µs tIRD INT release from DS (RD) - - 2 µs Interrupt Delay Timing (PLCC Package Only) Note: Package OBSOLETE Interrupt Delay Timing 19 bq4285 24-Pin DIP (P) 24-Pin DIP (P) Dimension A A1 B B1 C D E E1 e G L S Minimum 0.160 0.015 0.015 0.045 0.008 1.240 0.600 0.530 0.600 0.090 0.115 0.070 Maximum 0.190 0.040 0.022 0.065 0.013 1.280 0.625 0.570 0.670 0.110 0.150 0.090 All dimensions are in inches. 24-Pin SOIC (S) 24-Pin SOIC (S) Dimension A A1 B C D E e H L Minimum 0.095 0.004 0.013 0.008 0.600 0.290 0.045 0.395 0.020 All dimensions are in inches. 20 Maximum 0.105 0.012 0.020 0.013 0.615 0.305 0.055 0.415 0.040 bq4285 Data Sheet Revision History Change No. Page No. Description Natur of Change 1 3 Address strobe input Clarification 1 12 Was 2.0 min; is 2.5 min 1 13 Backup cell voltage VBC Power-fail detect voltage VPFD 1 13 Chip enable input current Additional specifiction 2 3, 13 Crystal type Daiwas DT-26 (not DT-26S) Clarification Was 4.1 min, 4.25 max; is 4.0 min, 4.35 max 3 1, 20, 22 Package option change PLCC last time buy 4 1, 2, 3, 13, 16, 19, 21, 23 Package option removal PLCC Last Time Buy Complete Note: Change 1 = Nov. 1992 B changes from June 1991 A. Change 2 = Nov. 1993 C changes from Nov. 1992 B Change 3 = Jan. 1999 D changes from Nov. 1993 C Change 4 = May 2004 (SLUS002A) changes from Jan. 1999 D 23 bq4285 Ordering Information bq4285 Temperature: blank = Commercial (0 to +70°C) Package Option: P = 24-pin plastic DIP (0.600) S = 24-pin SOIC (0.300) Device: bq4285 Real-Time Clock With NVRAM Control 24 PACKAGE OPTION ADDENDUM www.ti.com 14-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) BQ4285P-SB2 ACTIVE PDIP N 24 15 TBD Call TI BQ4285S-SB2 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ4285S-SB2TR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) Level-NA-NA-NA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002 N (R–PDIP–T24) PLASTIC DUAL–IN–LINE 1.222 (31,04) MAX 24 13 0.360 (9,14) MAX 1 12 0.070 (1,78) MAX 0.200 (5,08) MAX 0.425 (10,80) MAX 0.020 (0,51) MIN Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0’–15’ 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25) NOM 4040051–3/D 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS–010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.610 (40,89) 2.040 (51,82) 2.390 (60,71) 2.590 (65,79) DIM 4040053 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. 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