STMicroelectronics HCF4536B Programmable timer Datasheet

HCC/HCF4536B
PROGRAMMABLE TIMER
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24 FLIP-FLOP STAGES - COUNTS FROM
20 TO 224
LAST 16 STAGES SELECTABLE BY BCD SELECT CODE
BYPASS INPUT ALLOWS BYPASSING FIRST
8 STAGES
ON-CHIP RC OSCILLATOR PROVISION
CLOCK INHIBIT INPUT
SCHMITT-TRIGGER IN CLOCK LINE PERMITS OPERATION WITH VERY LONG RISE
AND FALL TIMES
ON-CHIP MONOSTABLE OUTPUT PROVISION
TYPICAL fCL = 3MHz AT VDD = 10V
TEST MODE ALLOWS FAST TEST SEQUENCE
SET AND RESET INPUTS
CAPABLE OF DRIVING TWO LOW POWER
TTL
LOADS,
ONE
LOWER-POWER
SCHOTTKY LOAD, OR TWO HTL LOADS
OVER THE RATED TEMPERATURE RANGE
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT AT 20V FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100 nA AT 18V AND 25°C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TENo
TATIVE STANDARD N . 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
HCC4536BF
ORDER CODES :
HCF4536BEY
HCF4536BC1
PIN CONNECTIONS
DESCRIPTION
The HCC4536B (extended temperature range) and
HCF4536B (intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package. The
HCC/HCF4536B is a programmable timer consisting of 24 ripple-binary counter stages. The salient
feature of this device is its flexibility. The device can
count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It can
be driven by an external clock or an RC oscillator
that can be constructed using on-chip components.
November 1996
1/17
HCC/HCF4536B
Input IN1 serves as either the external clock input or
the input to the on-chip RC oscillator. OUT1 and
OUT2 are connection terminals for the external RC
components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing functions can be achieved using
combinations of these capabilities. A logic 1 on the
8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the
last 16 stages. Selection of 1 of 16 outputs is accomplished by the decoder and the BCD inputs A, B, C
and D. MONO IN is the timing input for the on-chip
monostable oscillator. Grounding of the MONO IN
terminal through a resistor of 10KΩ or higher, disables the one-shot circuit and connects the decoder
directly to the DECODE OUT terminal. A resistor to
VDD and a capacitor to ground from the MONO IN
terminal enables the one-shot circuit and controls its
pulse width. A fast test mode is enabled by a logic
1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence.
FUNCTIONAL DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V DD*
Parameter
Supply Voltage : H CC Types
H C F Types
Vi
Input Voltage
II
Value
Unit
– 0.5 to + 20
– 0.5 to + 18
V
V
– 0.5 to V DD + 0.5
V
DC Input Current (any one input)
± 10
mA
Pt ot
Total Power Dissipation (per package)
Dissipation per Output Transistor
for T o p = Full Package-temperature Range
200
mW
100
mW
Top
Operating Temperature : H CC Types
H C F Types
– 55 to + 125
– 40 to + 85
°C
°C
Tstg
Storage Temperature
– 65 to + 150
°C
Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltages are with respect to VSS (GND).
2/17
HCC/HCF4536B
BLOCK DIAGRAM
DECODE OUT SELECTION TABLE
TRUTH TABLE
In 1 Set Reset Clock Osc Out1 Out2 Decode
Inh Inh
Out
–
–/
0
0
0
0
–
–/
–\
–
No
Change
–\
–
0
0
0
0
–\
–
– Advance
to Next
–/
State
X
1
0
0
0
0
1
X
0
1
0
0
0
1
1
0
No
Change
X
0
0
1
0
0
0
0
0
X
0
1
1
0
0
0
–
–/
–\
–
– Advance
to Next
–/
State
0 = Low Level
No
Change
Number or Stages
I n Divider Chain
D
C
B
A
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
9
10
11
12
1
2
3
4
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
13
14
15
16
5
6
7
8
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
17
18
19
20
9
10
11
12
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
21
22
23
24
13
14
15
16
8-BYPASS = 0 8-BYPASS = 1
0 = Low Level
3/17
HCC/HCF4536B
LOGIC DIAGRAMS (continued on next page)
4/17
HCC/HCF4536B
LOGIC DIAGRAMS (continued)
5/17
HCC/HCF4536B
STATIC ELECTRICAL CHARACTERISTICS (over recommended operating conditions)
Test Conditions
Symbol
IL
V OH
V OL
Parameter
Quiescent
Current
VI
(V)
VO
(V)
V IL
I OH
0/ 5
5
5
0.04
5
150
HCC
Types 0/15
10
10
0.04
10
300
15
20
0.04
20
600
0/20
20
100
0.08
100
3000
0/ 5
HCF
0/10
Types
0/15
5
20
0.04
20
150
10
40
0.04
40
300
15
80
0.04
80
600
Output High
Voltage
Output Low
Voltage
0/ 5
<1
5
4.95
4.95
4.95
0/10
<1
10
9.95
9.95
9.95
0/15
<1
15
14.95
5/0
<1
5
0.05
0.05
0.05
10/0
<1
10
0.05
0.05
0.05
I OL
Input High
Voltage
Input Low
Voltage
Output
Drive
Current
Output
Sink
Current
CI
15
<1
5
1/9
0.05
3.5
0.05
3.5
<1
10
7
7
7
1.5/13.5 < 1
15
11
11
11
4.5/0.5
<1
5
1.5
1.5
1.5
9/1
<1
10
3
3
3
13.5/1.5 < 1
15
4
4
4
5
– 2
– 1.6 – 3.2
– 1.15
HCC
Types 0/10
5
– 0.64
– 0.51 – 1
– 0.36
9.5
10
– 1.6
– 1.3 – 2.6
– 0.9
0/15
13.5
15
– 4.2
– 3.4 – 6.8
– 2.4
0/ 5
2.5
5
– 1.53
– 1.36 – 3.2
– 1.1
0/ 5
HCF
Types 0/10
4.6
5
– 0.52
– 0.44 – 1
– 0.36
9.5
10
– 1.3
– 1.1 – 2.6
– 0.9
0/15
13.5
15
– 3.6
– 3.0 – 6.8
– 2.4
0/ 5
0.4
5
0.64
0.51
1
0.36
0.5
10
1.6
1.3
2.6
0.9
1.5
15
4.2
3.4
6.8
2.4
0.4
5
0.52
0.44
1
0.36
0.5
10
1.3
1.1
2.6
0.9
1.5
15
3.6
3.0
6.8
2.4
Any Input
18
± 0.1
±10 – 5 ± 0.1
15
± 0.3
±10
V
mA
mA
± 1
µA
5
–5
± 0.3
7.5
* TLow = – 55°C for HCC device : – 40°C for HCF device.
* THigh= + 125°C for HCC device : + 85°C for HCF device.
The Noise Margin for both ”1” and ”0” level is : 1V min. with VDD = 5V , 2V min. with VDD = 10V, 2.5 V min. with VDD = 15V.
6/17
V
V
Any Input
HCF 0/15
Types
Input Capacitance
V
0.05
4.6
HCC 0/18
Types
µA
3.5
2.5
HCC
0/10
Types
0/15
Unit
14.95
0/ 5
HCF
0/10
Types
0/15
Input
Leakage
Current
<1
0.5/4.5
14.95
0/ 5
0/ 5
I IH , I IL
|I O | V D D
T L o w*
25 °C
T Hi g h *
(µA) (V) Min. Max. Min. Typ. Max. Min. Max.
0/10
15/0
V IH
Value
± 1
pF
HCC/HCF4536B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25 o C, C L = 50 pF, RL = 200 KΩ,
o
typical temperature coefficent for all VDD values is 03 %/ C, all input rise and fall times= 20 ns)
Symbol
tPLH
tPHL
Parameter
Propagation Delay Time
Clock to Q1, 8-bypass High
Clock to Q1, 8-bypass Low
Clock to Q16
Qn to Qn + 1
tPLH
Propagation Delay Time
tPHL
Reset to Qn
tTLH
tTHL
Transition Time
tW
Pulse Width
Clock
Set
Reset
Recovery Time
Set
Reset
tr, tf
fCL
Clock Input Rise or Fall Time
Test Conditions
VDD (V)
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
Maximum Clock Input Frequency
10
15
Min.
0.5
1.5
2.5
Value
Typ.
1
0.5
0.35
2.5
0.8
0.6
4
1.5
1
150
75
50
300
125
80
3
1
0.75
100
50
40
200
75
50
200
100
60
3
1
0.75
2.5
1
0.6
3.5
1.5
1
Max.
2
1
0.7
5
1.6
1.2
8
3
2
300
150
100
600
250
160
6
2
1.5
200
100
80
400
150
100
400
200
120
6
2
1.5
5
2
1.6
7
3
2
Unit
µs
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
Unlimted
µs
1
3
5
MHz
7/17
HCC/HCF4536B
Output Low (sink) Current Characteristics.
Output High (source) Current Characteristics.
Typical Transition Time vs. Load Capacitance.
Typical Propagation Delay Time vs. Load Capacitance (clock to Q1, 8 Bypass high).
Typical Propagation Delay Time vs. Load Capacitance (Clock to Q1, 8 Bypass low).
Typical Propagation Delay Time vs. Load Capacitance (Clock to Q16, 8 Bypass high).
8/17
HCC/HCF4536B
Typical Propagation Delay Time vs. Load Capacitance (QN to QN+1).
Typical RC Oscillator Frequency Deviation vs.
Supply Voltage.
Typical RC Oscillator Frequency Deviation vs.
Time Constant Resistance and Capacitance.
Typical RC Oscillator Frequency Deviation vs. Ambient Temperature (RS = 0).
Typical RC Oscillator Frequency Deviation vs. Ambient Temperature (RS = 120KΩ).
Typical Pulse Width vs. External Capacitance
(VDD = 5V).
9/17
HCC/HCF4536B
Typical Pulse Width vs. External Capacitance
(VDD = 10V).
Typical Pulse Width vs. External
(VDD = 15V).
Capacitance
Typical Dynamic Power Dissipation vs. Input
Pulse Frequency.
TYPICAL APPLICATIONS
Time Internal Configuration Using External Clock
; Set and Clock Inhibit Functions.
10/17
Time Internal Configuration Using External Clock
; Reset and Output Monostable to Achieve a
Pulse Output.
HCC/HCF4536B
TYPICAL APPLICATIONS (Continued)
Time Internal Configuration Using Onchip RC Oscillator and Reset Input to Initiate Time Interval.
Application Showing Use of 4098B and 4536B to
get Decode Pulse 8 Clock Pulses after Reset
TIMING DIAGRAM
11/17
HCC/HCF4536B
Functional Test Sequence
Inputs
Outputs
Comments
All 2 4 steps a r e in reset mode.
I n1
Set
Reset
8-Bypass
Decade Out
Q 1 Thru Q 2 4
1
0
1
1
0
1
1
1
1
0
Counter is in three 8-stage section in parallel
mode.
0
1
1
1
0
First ”1” to ”0” Transition of Clock
1
0
–
–
1
1
1
0
1
1
1
1
The 255 ”1” to ”0” Transition
0
0
0
0
1
Counter converted back to 24 stages in series
mode.
Set and Reset must be connected together and
simultaneoulsy go from ”1” to ”0”.
1
0
0
0
1
In 1 switches to a ”1”.
0
0
0
0
0
Counter Ripples from an all ”1” state to an all ”0”
state.
255 ”1” to ”0” transitions are clocked in the
counter.
FUNCTIONAL TEST SEQUENCE
Test Function has been included for the reduction of
test time required to exercise all 24 counter stages.
This test function divides the counter into three 8stage section and 255 counts are loaded in each of
the 8-stage sections in parallel. All flip-flops are now
at a ”1”. The counter is now returned to the normal
24-steps in series configuration. One more pulse is
entered into In1 which will cause the counter to ripple
from an all ”1” state to an all ”0” state.
TEST CIRCUITS
Quiescent Device Current.
12/17
Input Voltage.
HCC/HCF4536B
TEST CIRCUITS (continued)
Input Leakage Current.
Dynamic Power Dissipation.
Switching Time.
Input Waveforms for Switching-Time.
Functional.
13/17
HCC/HCF4536B
Plastic DIP16 (0.25) MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
0.77
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.020
1.65
0.030
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
17.78
0.700
F
7.1
0.280
I
5.1
0.201
L
Z
3.3
0.130
1.27
0.050
P001C
14/17
HCC/HCF4536B
Ceramic DIP16/1 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
20
0.787
B
7
0.276
D
E
3.3
0.130
0.38
e3
0.015
17.78
0.700
F
2.29
2.79
0.090
0.110
G
0.4
0.55
0.016
0.022
H
1.17
1.52
0.046
0.060
L
0.22
0.31
0.009
0.012
M
0.51
1.27
0.020
0.050
N
P
Q
10.3
7.8
8.05
5.08
0.406
0.307
0.317
0.200
P053D
15/17
HCC/HCF4536B
PLCC20 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
9.78
10.03
0.385
0.395
B
8.89
9.04
0.350
0.356
D
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
E
7.37
8.38
0.290
0.330
e
1.27
0.050
e3
5.08
0.200
F
0.38
0.015
G
0.101
0.004
M
1.27
0.050
M1
1.14
0.045
P027A
16/17
HCC/HCF4536B
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1996 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
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