STMicroelectronics L6562A 0708 Transition-mode pfc controller Datasheet

L6562A
Transition-mode PFC controller
Features
■
Proprietary multiplier design for minimum THD
■
Very accurate adjustable output overvoltage
protection
DIP-8
■
Ultra-low (30µA) Start-up current
■
Low (2.5mA) quiescent current
■
Digital leading-edge blanking on current sense
■
Disable function on E/A input
■
1% (@ TJ = 25 °C) internal reference voltage
■
■
SO-8
Applications
PFC pre-regulators for:
■
-600/+800mA totem pole gate driver with active
pull-down during UVLO and voltage clamp
IEC61000-3-2 compliant SMPS (Flat TV,
monitors, desktop PC, games)
■
HI-END AC-DC adapter/charger up to 400W
DIP-8/SO-8 packages
■
Electronic ballast
■
Entry level server & web server
Figure 1.
Block diagram
Table 1. Device summary
Order codes
Package
Packaging
L6562AN
DIP-8
Tube
L6562AD
SO-8
Tube
L6562ADTR
SO-8
Tape & Reel
August 2007
Rev 3
1/26
www.st.com
26
Contents
L6562A
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Typical electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.2
Disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.3
THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4
Operating with no auxiliary winding on the boost inductor . . . . . . . . . . . . 16
7.5
Comparison between the L6562A and the L6562 . . . . . . . . . . . . . . . . . . 17
8
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
L6562A
1
Description
Description
The L6562A is a current-mode PFC controller operating in Transition Mode (TM). Coming
with the same pin-out as its predecessors L6561 and L6562, it offers improved performance.
The highly linear multiplier includes a special circuit, able to reduce AC input current
distortion, that allows wide-range-mains operation with an extremely low THD, even over a
large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and an accurate
(1% @TJ = 25°C) internal voltage reference.
The device features extremely low consumption (60µA max. before start-up and <5 mA
operating) and includes a disable function suitable for IC remote ON/OFF, which makes it
easier to comply with energy saving requirements (Blue Angel, EnergyStar, Energy2000,
etc.).
An effective two-step OVP enables to safely handle overvoltages either occurring at start-up
or resulting from load disconnection.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable
to drive high current MOSFETs or IGBTs. This, combined with the other features and the
possibility to operate with the proprietary Fixed-Off-Time control, makes the device an
excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.
3/26
Pin settings
L6562A
2
Pin settings
2.1
Pin connection
Figure 2.
2.2
Pin connection (top view)
INV
1
8
Vcc
COMP
2
7
GD
MULT
3
6
GND
CS
4
5
ZCD
Pin description
Table 2. Pin description
4/26
Pin N°
Name
Description
1
INV
Inverting input of the error amplifier. The information on the output voltage of
the PFC pre-regulator is fed into this pin through a resistor divider. The pin
doubles as an ON/OFF control input.
2
COMP
Output of the error amplifier. A compensation network is placed between this
pin and INV to achieve stability of the voltage control loop and ensure high
power factor and low THD.
3
MULT
Main input to the multiplier. This pin is connected to the rectified mains
voltage via a resistor divider and provides the sinusoidal reference to the
current loop.
Input to the PWM comparator. The current flowing in the MOSFET is sensed
through a resistor, the resulting voltage is applied to this pin and compared
with an internal sinusoidal-shaped reference, generated by the multiplier, to
determine MOSFET’s turn-off. The pin is equipped with 200 ns leading-edge
blanking for improved noise immunity.
4
CS
5
ZCD
Boost inductor’s demagnetization sensing input for transition-mode
operation. A negative-going edge triggers MOSFET’s turn-on.
6
GND
Ground. Current return for both the signal part of the IC and the gate driver.
7
GD
Gate driver output. The totem pole output stage is able to drive power
MOSFET’s and IGBT’s with a peak current of 600 mA source and 800 mA
sink. The high-level voltage of this pin is clamped at about 12V to avoid
excessive gate voltages in case the pin is supplied with a high Vcc.
8
Vcc
Supply Voltage of both the signal part of the IC and the gate driver. The
supply voltage upper limit is extended to 22V min. to provide more headroom
for supply voltage changes.
L6562A
3
Maximum ratings
Maximum ratings
Table 3. Absolute maximum ratings
4
Symbol
Pin
VCC
8
IGD
7
---
1 to 4
IZCD
5
Parameter
Value
Unit
IC supply voltage (ICC ≤ 20mA)
Self-limited
V
Output totem pole peak current
Self-limited
A
-0.3 to 8
V
±10
mA
Analog inputs & outputs
Zero current detector max. current
Thermal data
Table 4. Thermal data
Value
Symbol
Parameter
Unit
SO8
DIP8
RthJA
Max. Thermal Resistance, Junction-toambient
150
100
°C/W
PTOT
Power Dissipation @TA = 50°C
0.65
1
W
TJ
TSTG
Junction Temperature Operating range
-40 to 150
°C
Storage Temperature
-55 to 150
°C
5/26
Electrical characteristics
5
L6562A
Electrical characteristics
Table 5. Electrical characteristics
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
22.5
V
Supply voltage
VCC
Operating range
After turn-on
10.5
VccOn
Turn-on threshold
(1)
11.7
12.5
13.3
V
VccOff
Turn-off threshold
(1)
9.5
10
10.5
V
2.8
V
25
28
V
Hys
Hysteresis
VZ
Zener Voltage
2.2
ICC = 20mA
22.5
Supply current
Istart-up
Iq
ICC
Iq
Start-up current
Before turn-on, VCC = 11V
30
60
µA
Quiescent current
After turn-on
2.5
3.75
mA
3.5
5
mA
1.7
2.2
mA
-1
µA
Operating supply current @ 70kHz
Quiescent current
During OVP (either static or dynamic)
or VINV ≤150mV
Multiplier input
IMULT
Input bias current
VMULT
Linear operation range
∆V cs
-------------------∆V MULT
K
VMULT = 0 to 4V
0 to 3
Output max. slope
VMULT = 0 to 1V,
VCOMP = Upper clamp
Gain (2)
V
1
1.1
V/V
VMULT = 1V, VCOMP= 4V,
0.32
0.38
0.44
TJ = 25 °C
2.475
2.5
2.525
10.5V < VCC < 22.5V (1)
2.455
V
Error amplifier
VINV
Line regulation
VCC = 10.5V to 22.5V
IINV
Input bias current
VINV = 0 to 3V
Gv
Voltage gain
Open loop
GB
Gain-bandwidth product
ICOMP
6/26
Voltage feedback input
threshold
V
2.545
2
60
5
mV
-1
µA
80
dB
1
MHz
Source current
VCOMP = 4V, VINV = 2.4V
-2
-3.5
Sink current
VCOMP = 4V, VINV = 2.6V
2.5
4.5
-5
mA
mA
L6562A
Electrical characteristics
Table 5. Electrical characteristics (continued)
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol
VCOMP
Parameter
Test condition
Min
Typ
Max
Unit
Upper clamp voltage
ISOURCE = 0.5mA
5.3
5.7
6
V
Lower clamp voltage
ISINK = 0.5mA (1)
2.1
2.25
2.4
V
VINVdis
Disable threshold
150
200
250
mV
VINVen
Restart threshold
380
450
520
mV
23.5
27
30.5
µA
Output overvoltage
IOVP
Dynamic OVP triggering
current
Hys
Hysteresis
(3)
Static OVP threshold
(1)
20
2.1
2.25
µA
2.4
V
-1
µA
300
ns
Current sense comparator
ICS
Input bias current
tLEB
Leading edge blanking
td(H-L)
VCS = 0
100
Delay to output
VCS
Current sense clamp
Vcsoffset
Current sense offset
200
175
VCOMP = Upper clamp, Vmult = 1.5V
1.0
1.08
VMULT = 0
25
VMULT = 2.5V
5
ns
1.16
V
mV
Zero current detector
VZCDH
Upper clamp voltage
IZCD = 2.5mA
5.0
5.7
6.5
V
VZCDL
Lower clamp voltage
IZCD = - 2.5mA
-0.3
0
0.3
V
VZCDA
Arming voltage
(positive-going edge)
(3)
1.4
V
VZCDT
Triggering voltage
(negative-going edge)
(3)
0.7
V
IZCDb
Input bias current
VZCD = 1 to 4.5V
2
µA
IZCDsrc
Source current capability
-2.5
mA
IZCDsnk
Sink current capability
2.5
mA
Start timer period
75
Starter
tSTART
190
300
µs
7/26
Electrical characteristics
L6562A
Table 5. Electrical characteristics (continued)
( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
0.6
1.2
V
Gate driver
VOL
Output low voltage
Isink = 100mA
VOH
Output high voltage
Isource = 5mA
Isrcpk
Peak source current
-0.6
A
Isnkpk
Peak sink current
0.8
A
10.3
V
tf
Voltage fall time
30
70
ns
tr
Voltage rise time
60
110
ns
12
15
V
1.1
V
VOclamp
Output clamp voltage
Isource = 5mA; Vcc = 20 V
UVLO saturation
Vcc = 0 to VCCon, Isink = 2 mA
1. All the parameters are in tracking
2. The multiplier output is given by:
Vcs = K ⋅ VMULT ⋅ (VCOMP − 2.5 )
3. Parameters guaranteed by design, functionality tested in production.
8/26
9.8
10
L6562A
Typical electrical characteristic
Figure 3.
Supply current vs supply
voltage
Figure 4.
Start-up & UVLO vs TJ
p
10.00
j
13
Vcc-ON
12
0.10
(V)
Icc (mA)
1.00
11
10
0.01
Co = 1 nF
f = 70 kHz
Tj = 25°C
0.00
0.00
Vcc-OFF
9
5.00
10.00
15.00
20.00
-50
25.00
0
Vcc (V)
Figure 5.
IC consumption vs TJ
p
50
100
150
Tj (°C)
Figure 6.
j
Vcc Zener voltage vs TJ
28
10
Operating
27
Quiescent
Disabled or during OVP
26
VccZ (V)
1
Icc (mA)
6
Typical electrical characteristic
24
Vcc = 12 V
Co= 1 nF
f = 70 kHz
0.1
25
23
Before start-up
22
-50
0.01
-50
0
50
100
150
0
50
100
150
Tj (°C)
Tj (°C)
9/26
Typical electrical characteristic
Figure 7.
L6562A
Feedback reference vs TJ
Figure 8.
OVP current vs TJ
j
35
2.6
34
Vcc = 12V
Vcc = 12V
33
32
2.55
Iovp (uA)
VREF (V)
31
2.5
30
29
28
27
26
2.45
25
24
2.4
23
-50
0
50
100
150
-50
0
Tj (°C)
Figure 9.
50
Tj (°C)
100
150
E/A output clamp levels vs TJ Figure 10. Delay-to-output vsTJ
300
6
Upper clamp
5
tD (H-L) (ns)
V COMP pin2 (V)
200
4
Vcc = 12V
3
Vcc = 12V
100
Lower clamp
2
0
1
-50
-50
0
50
Tj (°C)
10/26
100
150
0
50
Tj (°C)
100
150
L6562A
Typical electrical characteristic
Figure 11. Multiplier characteristic
Figure 12. Vcs clamp vs TJ
p
1.3
1.2
V COMP (pin2) (V)
Upper Volt. Clamp
1.1
Vcc = 12V
5.75 V
1.0
VCOMP = Upper clamp
4V
0.9
3.5V
5V
1.2
4.5V
0.7
Vcsx (V)
Vcs (pin4) (V)
0.8
0.6
0.5
3V
0.4
1.1
0.3
0.2
0.1
2.5 V
0.0
1
-0.1
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8 2
VMULT (pin3) (V)
2.2 2.4 2.6 2.8
0
50
100
150
Tj (°C)
Figure 13. ZCD clamp levels vs TJ
p
-50
3
Figure 14. Start-up timer vs TJ
p
j
j
200
7
Upper clamp
6
190
5
Vzcd (V)
Tstart (us)
Vcc = 12V
4
IZCD = ±2.5 mA
3
2
180
170
Vcc = 12V
1
160
Lower clamp
0
-1
-50
0
50
Tj (°C)
100
150
150
-50
0
50
Tj (°C)
100
150
11/26
Typical electrical characteristic
L6562A
Figure 15. Gate-driver output low
saturation
Figure 16. Gate-drive output high
saturation
5.00
12.00
Tj = 25 °C
11.00
4.00
Vcc = 12V
SOURCE
10.00
Vpin7 (V)
Vpin7 (V)
3.00
2.00
9.00
8.00
Tj = 25 °C
1.00
7.00
Vcc = 12V
SINK
0.00
6.00
0
200
400
600
800
1000
0
200
400
600
I GD (mA)
I GD (m A)
Figure 17. Gate-drive clamp vs TJ
Figure 18. Output gate drive low
saturation vs TJ during UVLO
13.5
1.1
Vcc = 20V
Isink = 2 mA
1
Vcc = 11V
0.9
Vpin7 (V)
Vpin7 clamp (V)
13.25
13
Vcc = 0V
0.8
0.7
12.75
0.6
0.5
12.5
-50
12/26
0
50
Tj (°C)
100
150
-50
0
50
Tj (°C)
100
150
L6562A
Application information
7
Application information
7.1
Overvoltage protection
Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a
PFC pre-regulator close to its nominal value, set by the resistors R1 and R2 of the output
divider. Neglecting ripple components, the current through R1, IR1, equals that through R2,
IR2. Considering that the non-inverting input of the error amplifier is internally referenced at
2.5V, also the voltage at pin INV will be 2.5V, then:
Equation 1
V O – 2.5
I R2 = I R1 = 2.5
-------- = --------------------R1
R2
If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage
at pin INV will be kept at 2.5V by the local feedback of the error amplifier, a network
connected between pins INV and COMP that introduces a long time constant to achieve
high PF (this is why ∆Vo can be large). As a result, the current through R2 will remain equal
to 2.5/R2 but that through R1 will become:
Equation 2
V O – 2.5 + ∆V O
I' R1 = --------------------------------------R1
The difference current ∆IR1=I'R1-IR2=I'R1-IR1= ∆Vo/R1 will flow through the compensation
network and enter the error amplifier output (pin COMP). This current is monitored inside
the device and if it reaches about 24µA the output voltage of the multiplier is forced to
decrease, thus smoothly reducing the energy delivered to the output. As the current
exceeds 27µA, the OVP is triggered (Dynamic OVP): the gate-drive is forced low to switch
off the external power transistor and the IC put in an idle state. This condition is maintained
until the current falls below approximately 7µA, which re-enables the internal starter and
allows switching to restart. The output ∆Vo that is able to trigger the Dynamic OVP function
is then:
Equation 3
∆VO = R1 · 20 · 10 - 6
An important advantage of this technique is that the OV level can be set independently of
the regulated output voltage: the latter depends on the ratio of R1 to R2, the former on the
individual value of R1. Another advantage is the precision: the tolerance of the detection
current is 13%, i.e. 13% tolerance on ∆Vo. Since ∆Vo << Vo, the tolerance on the absolute
value will be proportionally reduced.
Example: Vo = 400V, ∆Vo = 40V. Then: R1 = 40V/27µA ≈ 1.5MΩ ;
R2 = 1.5 MΩ ·2.5/(400-2.5) = 9.43kΩ. The tolerance on the OVP level due to the L6562A will
be 40·0.13 = 5.3V, that is ± 1.2%.
13/26
Application information
L6562A
When the load of a PFC pre-regulator is very low, the output voltage tends to stay steadily
above the nominal value, which cannot be handled by the Dynamic OVP. If this occurs,
however, the error amplifier output will saturate low; hence, when this is detected the
external power transistor is switched off and the IC put in an idle state (Static OVP). Normal
operation is resumed as the error amplifier goes back into its linear region. As a result, the
device will work in burst-mode, with a repetition rate that can be very low.
When either OVP is activated the quiescent consumption of the IC is reduced to minimize
the discharge of the Vcc capacitor and increase the hold-up capability of the IC supply
system.
7.2
Disable function
The INV pin doubles its function as a not-latched IC disable: a voltage below 0.2V shuts
down the IC and reduces its consumption at a lower value. To restart the IC, the voltage on
the pin must exceed 0.45 V. The main usage of this function is a remote ON/OFF control
input that can be driven by a PWM controller for power management purposes. However it
also offers a certain degree of additional safety since it will cause the IC to shutdown in case
the lower resistor of the output divider is shorted to ground or if the upper resistor is missing
or fails open.
7.3
THD optimizer circuit
The device is equipped with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
14/26
L6562A
Application information
Figure 19. THD optimization: standard TM PFC controller (left side) and L6562A
(right side)
Input current
Input current
Rectified mains voltage
Imains
Input current
Rectified mains voltage
Imains
Input current
MOSFET's drainVdrain
voltage
MOSFET's drainVdrain
voltage
To overcome this issue the circuit embedded in the device forces the PFC pre-regulator to
process more energy near the line voltage zero-crossings as compared to that commanded
by the control loop. This will result in both minimizing the time interval where energy transfer
is lacking and fully discharging the high-frequency filter capacitor after the bridge. The effect
of the circuit is shown in figure 2, where the key waveforms of a standard TM PFC controller
are compared to those of the L6562A.
Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid.
To maximally benefit from the THD optimizer circuit, the high-frequency filter capacitor after
the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - thus making the action of the
optimizer circuit little effective.
15/26
Application information
7.4
L6562A
Operating with no auxiliary winding on the boost inductor
To generate the synchronization signal on the ZCD pin, the typical approach requires the
connection between the pin and an auxiliary winding of the boost inductor through a limiting
resistor. When the device is supplied by the cascaded DC-DC converter, it is necessary to
introduce a supplementary winding to the PFC choke just to operate the ZCD pin.
Another solution could be implemented by simply connecting the ZCD pin to the drain of the
power MOSFET through an R-C network as shown in figure 3: in this way the highfrequency edges experienced by the drain will be transferred to the ZCD pin, hence arming
and triggering the ZCD comparator.
Also in this case the resistance value must be properly chosen to limit the current
sourced/sunk by the ZCD pin. In typical applications with output voltages around 400V,
recommended values for these components are 22pF (or 33pF) for CZCD and 330k for
RZCD. With these values proper operation is guaranteed even with few volts difference
between the regulated output voltage and the peak input voltage
Figure 20. ZCD pin synchronization without auxiliary winding
RZCD
ZCD
5
L6562A
16/26
CZCD
L6562A
7.5
Application information
Comparison between the L6562A and the L6562
The L6562A is not a direct drop-in replacement of the L6562, even if both have the same
pin-out. One function (Disable) has been relocated.
Table 2 compares the two devices, i.e. those parameters that may result in different values
of the external components. The parameters that have the most significant impact on the
design, i.e. that definitely require external component changes when converting an L6562based design to the L6562A, are highlighted in bold.
Table 6. L6562A vs. L6562
Parameter
L6562
L6562A
12/9.5 V
12.5/10 V
Turn-off threshold spread (max.)
±0.8 V
±0.5 V
IC consumption before start-up (max.)
70 uA
60 uA
0.6
0.38
1.7 V
1.08 V
Current sense propagation delay (delay-to-output) (typ.)
200 ns
175 ns
Dynamic OVP triggering current (typ.)
40 uA
27 uA
ZCD arm/trigger/clamp thresholds (typ.)
2.1/1.4/0.7 V
1.4/0.7/0 V
0.3 V (1)
0.45 V (2)
2.6 V
2.2 V
Leading-edge blanking on current sense
No
Yes
Reference voltage accuracy ( overall)
2.4%
1.8%
IC turn-on & turn-off thresholds (typ.)
Multiplier gain (typ.)
Current sense reference clamp (typ.)
Enable threshold (typ.)
Gate-driver internal drop (max.)
1. Function located on pin 5 (ZCD)
2. Function located on pin 1 (INV)
The lower value (-36%) for the clamp level of the current sense reference voltage allows the
use of a lower sense resistor for the same peak current, with a proportional reduction of the
associated power dissipation. Essentially, the advantage is the reduction of the power
dissipated in a single point (hotspot), which is a considerable benefit in applications where
heat removal is critical, e.g. in adapters enclosed in a sealed plastic case. The lower value
for the Dynamic OVP triggering current allows the use of a higher resistance value (+48%)
for the upper resistor of the divider sensing the output voltage of the PFC stage (keeping the
same overvoltage level) with no significant increase of noise sensitivity. This reduction goes
in favor of standby consumption in applications required to comply with energy saving
regulations.
17/26
Application examples and ideas
8
L6562A
Application examples and ideas
Figure 21. Demo board EVL6562A-TM-80W, wide-range mains : electrical schematic
Vo=400V
Po=80W
D1
NTC
STTH1L06 2.5 Ω
R4
R5
270 kΩ 270 kΩ
Vac
88V
to
264V
+
P1
W08
C1
0.22 µF
630V
T1
R14
100 Ω
R11
1M Ω
R50 - 22 kΩ
R6
47 kΩ
R2
1 MΩ
COMP
VCC
8
5
MULT
3
L6562A
C23
150 nF
2
GND
C29
22 µF
25V
Boost Inductor Spec (ITACOIL E2543/E)
E25x13x7 core, N67 ferrite
1.5 mm gap for 0.7 mH primary inductance
Primary: 102 turns 20x0.1 mm
Secondary: 10 turns 0.1 mm
C4
100 nF
INV
1
7
6
C2
10nF
R12
1M Ω
C3 - 2200 nF
ZCD
-
R3
15 kΩ
18/26
C5
10 nF
D2
1N5248B
R1
1 MΩ
F1
4A/250V
D8
1N4148
4
CS
GD
R7
33 Ω
C6
47 µF
450V
Q1
STP8NM50FP
R8
47k Ω
R15
SHORTED
R9
0.68 Ω
0.25W
R10
0.68 Ω
0.25W
R13
15 kΩ
R13B
82 kΩ
L6562A
Application examples and ideas
Figure 22. L6562A 80W TM PFC evaluation
Figure 23. L6562A 80W TM PFC evaluation
board: compliance to EN61000-3-2
board: compliance to JEIDA-MITI
standard
standard
Measurements @ 230Vac Full load
EN61000-3-2 class D limits
Measurements @ 100Vac Full load
1
Harmonic current (A)
Harmonic current (A)
1
JEIDA-MITI class D limits
0.1
0.01
0.001
0.0001
0.1
0.01
0.001
0.0001
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Harmonic Order (n)
Harmonic Order (n)
Vin = 230 Vac - 50 Hz, Pout = 80 W
THD = 10.48 %, PF = 0.973
Figure 24. Figure 3 - L6562A 80W TM PFC
Evaluation board: Input Current
waveform @230V-50Hz – 80W load
Vin = 100 Vac - 50 Hz, Pout = 80 W
THD = 3.18 %, PF = 0.997
Figure 25. Figure 4- L6562A 80W TM PFC
Evaluation board: Input Current
waveform @100V-50Hz – 80W load
19/26
Application examples and ideas
L6562A
Figure 26. L6562A 80W TM PFC evaluation
board: Power Factor vs Vin
Figure 27. L6562A 80W TM PFC evaluation
board: THD vs Vin
1.00
12
10
0.95
0.90
THD (%)
PF
8
Pout = 80W
6
4
0.85
Pout = 80W
2
0
0.80
80
100
120
140
160
180
200
220
240
80
260
100
120
140
160
180
200
220
240
260
Vin (Vac)
Vin (Va c)
Figure 28. L6562A 80W TM PFC evaluation
board: efficiency vs Vin
Figure 29. L6562A 80W TM PFC Evaluation
board: Static Vout regulation vs
Vin
100
404
403.5
95
Pout = 80W
402.5
90
Vout (Vdc)
EFFICIENCY (%)
403
Pout = 80W
85
402
401.5
401
80
400.5
75
80
100
120
140
160
180
Vin (Vac)
20/26
200
220
240
260
400
80
100
120
140
160
180
Vin (Vac)
200
220
240
260
90 - 265Vac
2
1
J1
R3 3
620k
620k
C1 4
3.3uF
1M5
R1
R3 2
8A/250V
F1
C1 3
470nF-X2
C1
220nF
C2 1
10nF
10k
4
3
2
1
CS
750k
R1 0
JP1 02
JUMPER
L2
RES
L6562A
MULT
COMP
INV
1
470nF-X2
C2
+40 0Vdc
R3 4
R14
39k
L1
CM-1.5mH-5A
1
JP1 01
JUMPER
9.1k
R1 2
680k
R1 1
ZCD
GND
GD
VCC
2
2
5
6
7
8
Q3
BC85 7C
R3 1
1K5
680nF-X2
C3
C1 6
220pF
47uF/50 V
R1 6
15K
C1 5
100pF
C1 2
470nF/5 0V
-
+
C1 1
~
~
D2
D1 5XB6 0
R1 5
820
LL4148
D6
470nF-630V
C4
L3
DM-51uH-6A
470nF-630V
C5
D4
LL4148
R4
180K
R3
180K
8
5-6
330pF
C2 0
R1 8
6R8
R3 5
3R9
R1 7
6R8
R3 6
3R9
D5
BZX8 5-C15
C1 0
33N
R5
47R
1K0
R1 9
11
L4
PQ40-500u H
1-2
D8
LL4148
D7
LL4148
R2 0
0R39-1W
R2 1
0R39-1W
R2 2
0R39-1W
+40 0Vdc
R2 3
0R68W
Q2
STP12NM5 0FP
C7
330uF-450V
NTC 2R5-S237
R2
470nF-630V
C6
Q1
STP12NM5 0FP
STTH8R06
D3
1N5406
D1
+
1
2
3
4
5
L6562A
Application examples and ideas
Figure 30. Demo board EVL6562A-400W, wide-range mains, FOT: electrical schematic
21/26
Package mechanical data
9
L6562A
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
22/26
L6562A
Package mechanical data
Table 7. DIP-8 mechanical data
mm
Inch
Dim.
Min
A
Typ
Max
Min
3.32
Typ
Max
0.131
a1
0.51
0.020
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
D
E
10.92
7.95
9.75
0.430
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
3.18
Z
3.81
1.52
0.125
0.150
0.060
Figure 31. Package dimensions
23/26
Package mechanical data
L6562A
Table 8. SO-8 mechanical data
mm.
inch
Dim.
Min
Typ
Max
Min
Typ
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
(1)
4.80
5.00
0.189
0.197
E
3.80
4.00
0.15
0.157
D
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
ddd
0° (min.), 8° (max.)
0.10
0.004
1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs
shall not exceed 0.15mm (.006inch) in total (both side).
Figure 32. Package dimensions
24/26
L6562A
10
Revision history
Revision history
Table 9. Revision history
Date
Revision
Changes
03-Mar-2007
1
First release
28-Jun-2007
2
Updated electrical characteristics
07-Aug-2007
3
Added Chapter 6: Typical electrical characteristic on page 9
25/26
L6562A
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