IS65C256AL IS62C256AL 32K x 8 LOW POWER CMOS STATIC RAM MAY 2012 FEATURES • Access time: 25 ns, 45 ns • Low active power: 200 mW (typical) • Low standby power — 150 µW (typical) CMOS standby — 15 mW (typical) operating • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 5V power supply • Lead-free available • Industrial and Automotive temperatures available DESCRIPTION The ISSI IS62C256AL/IS65C256AL is a low power, 32,768 word by 8-bit CMOS static RAM. It is fabricated using ISSI's high-performance, low power CMOS technology. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 150 µW (typical) at CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Select (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62C256AL/IS65C256AL is pin compatible with other 32Kx8 SRAMs in plastic SOP or TSOP (Type I) package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K X 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CE OE WE CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. D 05/09/12 1 IS65C256AL IS62C256AL PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOP 28-Pin TSOP A14 1 28 VDD A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE A0-A14 Address Inputs Mode CE Chip Select Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Not Selected (Power-down) Output Disabled Read Write VDD Power GND Ground WE CE OE I/O Operation VDD Current X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +7.0 –65 to +150 0.5 20 Unit V °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. Rev. D 05/09/12 IS65C256AL IS62C256AL OPERATING RANGE Part No. IS62C256AL IS62C256AL Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD 5V ± 10% 5V ± 10% IS65C256AL Automotive –40°C to +125°C 5V ± 10% DC ELECTRICAL CHARACTERISTICS Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Test Conditions VDD = Min., IOH = –1.0 mA VDD = Min., IOL = 2.1 mA Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled GND ≤ VIN ≤ VDD Com. Ind. Auto. Com. Ind. Auto. Min. 2.4 — 2.2 –0.3 –1 –2 –10 –1 –2 –10 Max. — 0.4 VDD + 0.5 0.8 1 2 10 1 2 10 Unit V V V V µA µA Note: 1. VIL = –3.0V for pulse width less than 10 ns. Integrated Silicon Solution, Inc. Rev. D 05/09/12 3 IS65C256AL IS62C256AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol ICC1 Parameter VDD Operating Supply Current Test Conditions VDD = Max., CE = VIL IOUT = 0 mA, f = 0 ICC2 VDD Dynamic Operating Supply Current VDD = Max., CE = VIL IOUT = 0 mA, f = fMAX ISB1 TTL Standby Current (TTL Inputs) ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. Com. Ind. Auto. typ. (2) Com. Ind. Auto. Com. Ind. Auto. typ. (2) -25 ns Min. Max. — 15 — 20 — 25 — 25 — 30 — 35 15 — 100 — 120 — 150 — 15 — 20 — 50 5 -45 ns Min. Max. — 15 — 20 — 25 — 20 — 25 — 30 12 — 100 — 120 — 150 — 15 — 20 — 50 5 Unit mA mA µA µA Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 5.0V, TA = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V. 4 Integrated Silicon Solution, Inc. Rev. D 05/09/12 IS65C256AL IS62C256AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -25 ns Min. Max. Parameter -45 ns Min. Max. Unit tRC Read Cycle Time 25 — 45 — ns tAA Address Access Time — 25 — 45 ns tOHA Output Hold Time 2 — 2 — ns tACS CE Access Time — 25 — 45 ns OE Access Time — 13 — 25 ns tLZOE OE to Low-Z Output 0 — 0 — ns tHZOE(2) OE to High-Z Output 0 12 0 20 ns tLZCS(2) CE to Low-Z Output 3 — 3 — ns tHZCS CE to High-Z Output 0 12 0 20 ns tPU CE to Power-Up 0 — 0 — ns tPD(3) CE to Power-Down — 20 — 30 ns tDOE (2) (2) (3) Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 1838 Ω 5V OUTPUT OUTPUT 100 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. Rev. D 05/09/12 480 Ω 5V 993 Ω 5 pF Including jig and scope 255 Ω Figure 2. 5 IS65C256AL IS62C256AL AC WAVEFORMS READ CYCLE NO. 1(1,2) t RC ADDRESS t AA t OHA t OHA DOUT DATA VALID PREVIOUS DATA VALID READ1.eps READ CYCLE NO. 2(1,3) t RC ADDRESS t AA t OHA OE t HZOE t DOE t LZOE CE t ACS t HZCS t LZCS DOUT HIGH-Z DATA VALID CS_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. Rev. D 05/09/12 IS65C256AL IS62C256AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -25 ns Min. Max. Parameter -45 ns Min. Max. Unit tWC Write Cycle Time 25 — 45 — ns tSCS CE to Write End 15 — 35 — ns tAW Address Setup Time to Write End 15 — 25 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWE1, tPWE2(4) WE Pulse Width 15 — 25 — ns tSD Data Setup to Write End 12 — 20 — ns tHD Data Hold from Write End 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCS t HA CE t AW t PWE1 t PWE2 WE t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CS_WR1.eps Integrated Silicon Solution, Inc. Rev. D 05/09/12 7 IS65C256AL IS62C256AL AC WAVEFORMS WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA DOUT t HZWE t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN CS_WR2.eps WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1) t WC ADDRESS OE CE VALID ADDRESS t HA LOW LOW t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CS_WR3.eps Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. I/O will assume the High-Z state if OE = VIH. 8 Integrated Silicon Solution, Inc. Rev. D 05/09/12 IS65C256AL IS62C256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. 2.0 VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V VIN ≥ VDD – 0.2V, or VIN ≤ VSS + 0.2V tSDR Data Retention Setup Time See Data Retention Waveform tRDR Recovery Time Com. Ind. Auto. See Data Retention Waveform Max. Unit 5.5 V 15 20 50 µA 0 — ns tRC — ns — — — Typ. — — — Note: 1. Typical Values are measured at VDD = 5V, TA = 25oC and not 100% tested. CE Controlled) DATA RETENTION WAVEFORM (CE tSDR Data Retention Mode tRDR VDD 4.5V 2.2V VDR CE1 GND Integrated Silicon Solution, Inc. Rev. D 05/09/12 CE1 ≥ VDD - 0.2V 9 IS65C256AL IS62C256AL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 45 Order Part No. Package IS62C256AL-45T IS62C256AL-45TL IS62C256AL-45UL TSOP TSOP, Lead-free Plastic SOP, Lead-free ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package 25 IS62C256AL-25TI IS62C256AL-25ULI TSOP Plastic SOP, Lead-free 45 IS62C256AL-45TI IS62C256AL-45TLI IS62C256AL-45ULI TSOP TSOP, Lead-free Plastic SOP, Lead-free ORDERING INFORMATION Automotive Range: –40°C to +125°C Speed (ns) 10 Order Part No. Package 25 IS65C256AL-25TA3 IS65C256AL-25TLA3 IS65C256AL-25ULA3 TSOP TSOP, Lead-free Plastic SOP, Lead-free 45 IS65C256AL-45TA3 IS65C256AL-45TLA3 IS65C256AL-45ULA3 TSOP TSOP, Lead-free Plastic SOP, Lead-free Integrated Silicon Solution, Inc. Rev. D 05/09/12 IS65C256AL IS62C256AL Integrated Silicon Solution, Inc. Rev. D 05/09/12 11 IS65C256AL IS62C256AL 12 Integrated Silicon Solution, Inc. Rev. D 05/09/12