Freescale MK61FN1M0VMJ12 K61 sub-family data sheet Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: K61P256M120SF3
Rev. 3, 2/2012
K61P256M120SF3
K61 Sub-Family Data Sheet
Supports the following:
MK61FX512VMJ12,
MK61FN1M0VMJ12
Features
• Operating Characteristics
– Voltage range: 1.71 to 3.6 V
– Flash write voltage range: 1.71 to 3.6 V
– Temperature range (ambient): -40 to 105°C
• Performance
– Up to 120 MHz ARM Cortex-M4 core with DSP
instructions delivering 1.25 Dhrystone MIPS per
MHz
• Memories and memory interfaces
– Up to 1024 KB program flash memory on nonFlexMemory devices
– Up to 512 KB program flash memory on
FlexMemory devices
– Up to 512 KB FlexNVM on FlexMemory devices
– 16 KB FlexRAM on FlexMemory devices
– Up to 128 KB RAM
– Serial programming interface (EzPort)
– FlexBus external bus interface
– DDR controller interface
– NAND flash controller interface
• Clocks
– 3 to 32 MHz crystal oscillator
– 32 kHz crystal oscillator
– Multi-purpose clock generator
• System peripherals
– 10 low-power modes to provide power optimization
based on application requirements
– Memory protection unit with multi-master
protection
– 32-channel DMA controller, supporting up to 128
request sources
– External watchdog monitor
– Software watchdog
– Low-leakage wakeup unit
• Security and integrity modules
– Hardware CRC module to support fast cyclic
redundancy checks
– Tamper detect and secure storage
– Hardware random-number generator
– Hardware encryption supporting DES, 3DES, AES,
MD5, SHA-1, and SHA-256 algorithms
– 128-bit unique identification (ID) number per chip
• Human-machine interface
– Low-power hardware touch sensor interface (TSI)
– General-purpose input/output
• Analog modules
– Four 16-bit SAR ADCs
– Programmable gain amplifier (PGA) (up to x64)
integrated into each ADC
– Two 12-bit DACs
– Four analog comparators (CMP) containing a 6-bit
DAC and programmable reference input
– Voltage reference
• Timers
– Programmable delay block
– Two 8-channel motor control/general purpose/PWM
timers
– Two 2-channel quadrature decoder/general purpose
timers
– IEEE 1588 timers
– Periodic interrupt timers
– 16-bit low-power timer
– Carrier modulator transmitter
– Real-time clock
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
© 2012 Freescale Semiconductor, Inc.
Preliminary
• Communication interfaces
– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability
– USB high-/full-/low-speed On-the-Go controller with ULPI interface
– USB full-/low-speed On-the-Go controller with on-chip transceiver
– Two Controller Area Network (CAN) modules
– Three SPI modules
– Two I2C modules
– Six UART modules
– Secure Digital host controller (SDHC)
– Two I2S modules
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
2
Preliminary
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................5
5.4.2
Thermal attributes...............................................26
1.1 Determining valid orderable parts......................................5
6 Peripheral operating requirements and behaviors....................26
2 Part identification......................................................................5
6.1 Core modules....................................................................26
2.1 Description.........................................................................5
6.1.1
Debug trace timing specifications.......................27
2.2 Format...............................................................................5
6.1.2
JTAG electricals..................................................27
2.3 Fields.................................................................................5
6.2 System modules................................................................30
2.4 Example............................................................................6
6.3 Clock modules...................................................................30
3 Terminology and guidelines......................................................6
6.3.1
MCG specifications.............................................30
3.1 Definition: Operating requirement......................................6
6.3.2
Oscillator electrical specifications.......................32
3.2 Definition: Operating behavior...........................................6
6.3.3
32kHz Oscillator Electrical Characteristics.........34
3.3 Definition: Attribute............................................................7
6.4 Memories and memory interfaces.....................................35
3.4 Definition: Rating...............................................................7
6.4.1
Flash (FTFE) electrical specifications.................35
3.5 Result of exceeding a rating..............................................8
6.4.2
EzPort Switching Specifications.........................38
3.6 Relationship between ratings and operating
6.4.3
NFC specifications..............................................39
requirements......................................................................8
6.4.4
DDR controller specifications..............................42
3.7 Guidelines for ratings and operating requirements............8
6.4.5
Flexbus Switching Specifications........................45
3.8 Definition: Typical value.....................................................9
6.5 Security and integrity modules..........................................48
3.9 Typical value conditions....................................................10
4 Ratings......................................................................................10
6.5.1
DryIce Tamper Electrical Specifications.............48
6.6 Analog...............................................................................49
4.1 Thermal handling ratings...................................................10
6.6.1
ADC electrical specifications..............................50
4.2 Moisture handling ratings..................................................11
6.6.2
CMP and 6-bit DAC electrical specifications......58
4.3 ESD handling ratings.........................................................11
6.6.3
12-bit DAC electrical characteristics...................60
4.4 Voltage and current operating ratings...............................11
6.6.4
Voltage reference electrical specifications..........63
5 General.....................................................................................12
6.7 Timers................................................................................64
5.1 AC electrical characteristics..............................................12
6.8 Communication interfaces.................................................64
5.2 Nonswitching electrical specifications...............................13
6.8.1
Ethernet switching specifications........................64
5.2.1
Voltage and current operating requirements......13
6.8.2
USB electrical specifications...............................66
5.2.2
LVD and POR operating requirements...............15
6.8.3
USB DCD electrical specifications......................66
5.2.3
Voltage and current operating behaviors............16
6.8.4
USB VREG electrical specifications...................67
5.2.4
Power mode transition operating behaviors.......18
6.8.5
ULPI timing specifications...................................67
5.2.5
Power consumption operating behaviors............19
6.8.6
CAN switching specifications..............................68
5.2.6
EMC radiated emissions operating behaviors....22
6.8.7
DSPI switching specifications (limited voltage
5.2.7
Designing with radiated emissions in mind.........23
5.2.8
Capacitance attributes........................................23
range).................................................................69
6.8.8
5.3 Switching specifications.....................................................23
DSPI switching specifications (full voltage
range).................................................................70
5.3.1
Device clock specifications.................................23
6.8.9
I2C switching specifications................................72
5.3.2
General switching specifications.........................24
6.8.10
UART switching specifications............................72
5.4 Thermal specifications.......................................................25
6.8.11
SDHC specifications...........................................72
6.8.12
I2S/SAI Switching Specifications........................73
5.4.1
Thermal operating requirements.........................25
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
3
6.9 Human-machine interfaces (HMI)......................................75
6.9.1
8 Pinout........................................................................................77
TSI electrical specifications................................75
8.1 K61 Signal Multiplexing and Pin Assignments..................77
7 Dimensions...............................................................................76
8.2 K61 Pinouts.......................................................................87
7.1 Obtaining package dimensions.........................................77
9 Revision History........................................................................88
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
4
Preliminary
Freescale Semiconductor, Inc.
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.freescale.com and perform a part number
search for the following device numbers: PK61 and MK61.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
Q K## A M FFF T PP CC N
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
Kinetis family
• K61
A
Key attribute
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
5
Terminology and guidelines
Field
Description
Values
FFF
Program flash memory size
•
•
•
•
•
•
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
T
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
• MJ = 256 MAPBGA (17 mm x 17 mm)
CC
Maximum CPU frequency (MHz)
• 12 = 120 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
2.4 Example
This is an example part number:
MK61FN1M0VMJ12
3 Terminology and guidelines
3.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
3.1.1 Example
This is an example of an operating requirement, which you must meet for the
accompanying operating behaviors to be guaranteed:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
6
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
3.2 Definition: Operating behavior
An operating behavior is a specified value or range of values for a technical
characteristic that are guaranteed during operation if you meet the operating requirements
and any other specified conditions.
3.2.1 Example
This is an example of an operating behavior, which is guaranteed if you meet the
accompanying operating requirements:
Symbol
IWP
Description
Min.
Digital I/O weak pullup/ 10
pulldown current
Max.
130
Unit
µA
3.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
—
Max.
7
Unit
pF
3.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
7
Terminology and guidelines
3.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
Min.
1.0 V core supply
voltage
Max.
–0.3
Unit
1.2
V
3.5 Result of exceeding a rating
Failures in time (ppm)
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
3.6 Relationship between ratings and operating requirements
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- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- Probable permanent failure
Handling range
- No permanent failure
∞
–∞
3.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
8
Preliminary
Freescale Semiconductor, Inc.
Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
3.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
µA
3.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
9
Ratings
5000
4500
4000
TJ
IDD_STOP (μA)
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.05
1.00
1.10
VDD (V)
3.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
°C
VDD
3.3 V supply voltage
3.3
V
4 Ratings
4.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
–55
150
°C
1
TSDR
Solder temperature, lead-free
—
260
°C
2
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
10
Preliminary
Freescale Semiconductor, Inc.
Ratings
4.2 Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
VHBM
Electrostatic discharge voltage, human body model
-2000
+2000
V
1
VCDM
Electrostatic discharge voltage, charged-device model
-500
+500
V
2
Latch-up current at ambient temperature of 105°C
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
4.4 Voltage and current operating ratings
Symbol
Description
Min.
Max.
Unit
Digital supply voltage1
–0.3
3.8
V
VDD_INT
Core supply voltage
–0.3
3.8
V
VDD_DDR
DDR I/O supply voltage
–0.3
3.8
V
Digital supply current
—
300
mA
IDD_INT
Core supply current
—
185
mA
IDD_DDR
DDR supply current
—
220
mA
Digital input voltage (except RESET, EXTAL0/XTAL0, and
EXTAL1/XTAL1) 2
–0.3
5.5
V
Tamper input voltage
–0.3
VBAT + 0.3
V
DDR input voltage
–0.3
VDD_DDR +
0.3
V
Analog3, RESET, EXTAL0/XTAL0, and EXTAL1/XTAL1 input
voltage
–0.3
VDD + 0.3
V
VDD
IDD
VDIO
VDTamper
VDDDR
VAIO
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
11
General
Symbol
Description
Min.
Max.
Unit
Instantaneous maximum current single pin limit (applies to all
digital pins except Tamper and DDR pins)
–25
25
mA
ID_DDR
Instananeous maximum current single pin limit (applies to
DDR pins)
TBD
TBD
mA
ID_Tamper
Instananeous maximum current single pin limit (applies to
Tamper pins)
TBD
TBD
mA
ID
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
VUSB_DP
USB_DP input voltage
–0.3
3.63
V
VUSB_DM
USB_DM input voltage
–0.3
3.63
V
VREGIN
USB regulator input
–0.3
6.0
V
RTC battery supply voltage
–0.3
3.8
V
VBAT
1. It applies for all port pins except Tamper pins.
2. It covers digital pins except Tamper pins and DDR pins.
3. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
5 General
5.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
Figure 1. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
• have CL=30pF loads,
• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and
• are configured for high drive strength (PORTx_PCRn[DSE]=1)
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
12
Preliminary
Freescale Semiconductor, Inc.
General
5.2 Nonswitching electrical specifications
5.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
Min.
Max.
Unit
max(VDD_DD
R,1.71)
3.6
V
1.71
VDD
V
• DDR1
2.3
2.7
V
• DDR2/LPDDR
1.7
1.9
V
0.49 ×
VDD_DDR
0.51 ×
VDD_DDR
V
1.71
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
–0.1
0.1
V
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
0.1
V
1.71
3.6
V
0.7 × VDD
—
V
0.75 × VDD
—
V
—
0.35 × VDD
V
—
0.3 × VDD
V
VREF_DDR +
0.15
—
V
—
V
VREF_DDR +
0.125
—
V
VDD
Description
Supply voltage
VDD_INT
Core supply voltage
VDD_DDR
DDR voltage — memory I/O buffers
VREF_DDR
VDDA
VBAT
VIH
Input reference voltage (DDR1/DDR2)
Analog supply voltage
RTC battery supply voltage
Input high voltage (digital pins except Tamper pins
and DDR pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VIL
Input low voltage (digital pins except Tamper pins and
DDR pins)
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VIH_DDR
Input high voltage (DDR pins)
• DDR1
• DDR2
• LPDDR
Notes
0.7 ×
VDD_DDR
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
13
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
VIL_DDR
Input low voltage (DDR pins)
• DDR1
• DDR2
• LPDDR
Min.
Max.
Unit
—
VREF_DDR –
0.15
V
VREF_DDR –
0.125
V
—
—
Notes
V
0.3 ×
VDD_DDR
VIH_Tamper
Tamper input high voltage
• 2.7 V ≤ VBAT ≤ 3.6 V
• 1.7 V ≤ VBAT ≤ 2.7 V
VIL_Tamper
Tamper input low voltage
• 2.7 V ≤ VBAT ≤ 3.6 V
0.7 × VBAT
—
V
0.75 × VBAT
—
V
—
0.35 × VBAT
V
—
0.3 × VBAT
V
0.06 × VDD
—
V
0.06 × VBAT
—
V
-5
—
mA
TBD
TBD
mA
-0.2
—
mA
—
2.0
mA
• 1.7 V ≤ VBAT ≤ 2.7 V
VHYS
Input hysteresis (digital pins except Tamper pins and
DDR pins)
VHYS_Tamper Input hysteresis (Tamper pins)
IICDIO
Digital pin (except Tamper pins and DDR pins)
negative DC injection current — single pin
1
• VIN < VSS-0.3V
IICDIO_DDR
DDR pin negative DC injection current -- single pin
• TBD
IICDIO_Tamper Tamper pin negative DC injection current — single pin
• VIN < VSS-0.3V
• VIN > VBAT
IICAIO
IICcont
-5
—
• VIN > VDD+0.3V (Positive current injection)
—
+5
-25
—
—
+25
1.2
—
V
VPOR_VBAT
—
V
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Positive current injection
VRFVBAT
mA
• VIN < VSS-0.3V (Negative current injection)
• Negative current injection
VRAM
3
Analog2, EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC
injection current — single pin
VDD (VDD_INT) voltage required to retain RAM
VBAT voltage required to retain the VBAT register file
mA
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection
to VDD. If VIN greater than VDIO_MIN (=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
14
Preliminary
Freescale Semiconductor, Inc.
General
the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current
limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IIC|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN
(=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting
resistors at the pads. If these limits cannot be observed then a current limiting resistor is required. The negative DC
injection current limiting resistor is calculated as R=(VAIO_MIN-VIN)/|IIC|. The positive injection current limiting resistor is
calcualted as R=(VIN-VAIO_MAX)/|IIC|. Select the larger of these two calculated resistances.
5.2.2 LVD and POR operating requirements
Table 2. LVD and POR operating requirements
Symbol
Description
Min.
Typ.
Max.
Unit
VPOR
Falling VDD POR detect voltage
0.8
1.1
1.5
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
1
VLVW1H
• Level 1 falling (LVWV=00)
2.62
2.70
2.78
V
VLVW2H
• Level 2 falling (LVWV=01)
2.72
2.80
2.88
V
VLVW3H
• Level 3 falling (LVWV=10)
2.82
2.90
2.98
V
VLVW4H
• Level 4 falling (LVWV=11)
2.92
3.00
3.08
V
—
±80
—
mV
1.54
1.60
1.66
V
VHYSH
Low-voltage inhibit reset/recover hysteresis —
high range
VLVDL
Falling low-voltage detect threshold — low range
(LVDV=00)
Low-voltage warning thresholds — low range
1
VLVW1L
• Level 1 falling (LVWV=00)
1.74
1.80
1.86
V
VLVW2L
• Level 2 falling (LVWV=01)
1.84
1.90
1.96
V
VLVW3L
• Level 3 falling (LVWV=10)
1.94
2.00
2.06
V
VLVW4L
• Level 4 falling (LVWV=11)
2.04
2.10
2.16
V
—
±60
—
mV
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
Notes
VBG
Bandgap voltage reference
0.97
1.00
1.03
V
tLPO
Internal low power oscillator period
900
1000
1100
μs
factory trimmed
1. Rising thresholds are falling threshold + hysteresis voltage
Table 3. VBAT power operating requirements
Symbol
Description
VPOR_VBAT Falling VBAT supply POR detect voltage
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
V
Notes
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
15
General
5.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA
VDD – 0.5
—
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA
VDD – 0.5
—
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA
VDD – 0.5
—
V
Output high current total for all ports
—
100
mA
IOHT_io60
Output high current total for fast digital ports
—
100
mA
VOH_DDR
Output high voltage for DDR pins
VDD_DDR 0.36
—
V
—
V
VDD_DDR 0.28
—
V
VDD_DDR 0.28
—
V
—
V
—
TBD
mA
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
VBAT – 0.5
—
V
—
TBD
mA
VOH
Description
Notes
Output high voltage — high drive strength
Output high voltage — low drive strength
IOHT
• DDR1 (IOH = -16.2 mA)
• DDR2 half strength (IOH = TBD mA)
• DDR2 full strength (IOH = -13.4 mA)
• LPDDR half strength (IOH = -0.1 mA)
• LPDDR full strength (IOH = -0.1 mA)
0.9 x
VDD_DDR
0.9 x
VDD_DDR
IOHT_DDR
Output high current total for DDR pins
• DDR1
• DDR2
• LPDDR
VOH_Tamper
Output high voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -3mA
Output high voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -0.6mA
IOH_Tamper
Output high current total for Tamper pins
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
16
Preliminary
Freescale Semiconductor, Inc.
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Min.
Max.
Unit
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA
—
0.5
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA
—
0.5
V
Output low current total for all ports
—
TBD
mA
IOLT_io60
Output low current total for fast digital ports
—
TBD
mA
VOL_DDR
Output low voltage for DDR pins
VOL
Description
Notes
Output low voltage — high drive strength
Output low voltage — low drive strength
IOLT
—
0.37
V
• DDR1 (IOL = 16.2 mA)
—
0.28
V
• DDR2 half strength (IOL = TBD mA)
—
0.28
V
• DDR2 full strength (IOL = 13.4 mA)
—
—
0.1 x
VDD_DDR
V
• LPDDR half strength (IOL = 0.1 mA)
• LPDDR full strength (IOL = 0.1 mA)
IOLT_DDR
V
0.1 x
VDD_DDR
Output low current total for DDR pins
—
TBD
mA
—
0.5
V
—
0.5
V
—
0.5
V
—
0.5
V
Output low current total for Tamper pins
—
TBD
mA
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
1
IIN
Input leakage current (per pin) at 25°C
—
0.025
μA
1
IIN_DDR
Input leakage current (per DDR pin) for full
temperature range
—
1
μA
IIN_DDR
Input leakage current (per DDR pin) at 25°C
—
0.025
μA
IIN_Tamper
Input leakage current (per Tamper pin) for full
temperature range
—
TBD
μA
IIN_Tamper
Input leakage current (per Tamper pin) at 25°C
—
0.025
μA
• DDR1
• DDR2
• LPDDR
VOL_Tamper
Output low voltage — high drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 10mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 3mA
Output low voltage — low drive strength
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = 2mA
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = 0.6mA
IOL_Tamper
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
17
General
Table 4. Voltage and current operating behaviors (continued)
Symbol
Min.
Max.
Unit
Hi-Z (off-state) leakage current (per pin)
—
1
μA
Hi-Z (off-state) leakage current (per DDR pin)
—
1
μA
Hi-Z (off-state) leakage current (per Tamper pin)
—
1
μA
RPU
Internal pullup resistors
20
50
kΩ
2
RPD
Internal pulldown resistors
20
50
kΩ
3
RPU_Tamper
Internal pullup resistors (per Tamper pin)
20
50
kΩ
RPD_Tamper
Internal pulldown resistors (per Tamper pin)
20
50
kΩ
60
90
Ω
120
180
Ω
IOZ
IOZ_DDR
IOZ_Tamper
RODT
Description
On-die termination (ODT) resistance for DDR2
• Rtt1(eff) - 75 Ω
• Rtt2(eff) - 150 Ω
Notes
1. Measured at VDD=3.6V
2. Measured at VDD supply voltage = VDD min and Vinput = VSS
3. Measured at VDD supply voltage = VDD min and Vinput = VDD
5.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
•
•
•
•
CPU and system clocks = FEI 100 MHz
Bus clock = 50 MHz
FlexBus clock = 50 MHz
Flash clock = 25 MHz
Table 5. Power mode transition operating behaviors
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
Min.
Max.
Unit
Notes
—
300
μs
1
—
126
μs
—
82
μs
—
82
μs
—
5.0
μs
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
18
Preliminary
Freescale Semiconductor, Inc.
General
Table 5. Power mode transition operating behaviors (continued)
Symbol
Description
• VLPS → RUN
• STOP → RUN
Min.
Max.
Unit
—
TBD
μs
—
TBD
μs
Notes
1. Normal boot (FTFE_FOPT[LPBOOT]=1)
5.2.5 Power consumption operating behaviors
Table 6. Power consumption operating behaviors
Symbol
IDDA
IDD_RUN
Description
Min.
Typ.
Max.
Unit
Notes
Analog supply current
—
—
See note
mA
1
Run mode current — all peripheral clocks
disabled, code executing from flash
—
65
TBD
mA
—
65
TBD
mA
—
95
TBD
mA
—
95
TBD
mA
2
• @ 1.8V
• @ 3.0V
IDD_RUN
Run mode current — all peripheral clocks
enabled, code executing from flash
3
• @ 1.8V
• @ 3.0V
IDD_WAIT
Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
37
TBD
mA
2
IDD_WAIT
Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
21
TBD
mA
4
IDD_STOP
Stop mode current at 3.0 V
—
TBD
TBD
mA
—
TBD
TBD
mA
—
TBD
TBD
mA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
—
2.3
TBD
mA
5
IDD_VLPR
Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
3.1
TBD
mA
6
IDD_VLPW
Very-low-power wait mode current at 3.0 V
—
1.8
TBD
mA
7
IDD_VLPS
Very-low-power stop mode current at 3.0 V
—
200
TBD
μA
—
TBD
TBD
μA
—
TBD
TBD
μA
• @ –40 to 25°C
• @ 70°C
• @ 105°C
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
19
General
Table 6. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_LLS
Low leakage stop mode current at 3.0 V
—
200
TBD
μA
—
TBD
TBD
μA
—
TBD
TBD
μA
—
6.5
TBD
μA
—
37.4
TBD
μA
—
148.3
TBD
μA
—
3.4
TBD
μA
—
13.4
TBD
μA
—
58.5
TBD
μA
—
2.9
TBD
μA
—
9.8
TBD
μA
—
44.7
TBD
μA
—
0.91
1.1
μA
• @ –40 to 25°C
—
1.5
1.85
μA
• @ 70°C
—
4.3
4.3
μA
• @ –40 to 25°C
• @ 70°C
Notes
8
• @ 105°C
IDD_VLLS3
Very low-leakage stop mode 3 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
#newreference/
llsramn
• @ 105°C
IDD_VLLS2
Very low-leakage stop mode 2 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VLLS1
Very low-leakage stop mode 1 current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
IDD_VBAT
Average current when CPU is not accessing
RTC registers at 3.0 V
9
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus, 50 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled, but peripherals are not in active operation.
4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
7. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
8. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.
9. Includes 32kHz oscillator current and RTC operation.
5.2.5.1
Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
20
Preliminary
Freescale Semiconductor, Inc.
General
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater
than 50 MHz frequencies. MCG in PEE mode is greater than 100 MHz frequencies.
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFL
Figure 2. Run mode supply current vs. core frequency
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
21
General
Figure 3. VLPR mode supply current vs. core frequency
5.2.6 EMC radiated emissions operating behaviors
Table 7. EMC radiated emissions operating behaviors for 256MAPBGA
Symbol
Description
Frequency
band (MHz)
Typ.
Unit
VRE1
Radiated emissions voltage, band 1
0.15–50
TBD
dBμV
VRE2
Radiated emissions voltage, band 2
50–150
TBD
dBμV
VRE3
Radiated emissions voltage, band 3
150–500
TBD
dBμV
VRE4
Radiated emissions voltage, band 4
500–1000
TBD
dBμV
IEC level
0.15–1000
K
—
VRE_IEC
Notes
1,
2
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported
emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the
measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48 MHz
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
22
Preliminary
Freescale Semiconductor, Inc.
General
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband
TEM Cell Method
5.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to http://www.freescale.com.
2. Perform a keyword search for “EMC design.”
5.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN_A
Input capacitance: analog pins
—
7
pF
CIN_D
Input capacitance: digital pins
—
7
pF
Input capacitance: fast digital pins
—
9
pF
CIN_D_io60
5.3 Switching specifications
5.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
Description
Min.
Max.
Unit
System and core clock
—
120
MHz
fSYS_USBFS
System and core clock when Full Speed USB in
operation
20
—
MHz
fSYS_USBHS
System and core clock when High Speed USB in
operation
60
—
MHz
fENET
System and core clock when ethernet in operation
Notes
Normal run mode
fSYS
• 10 Mbps
• 100 Mbps
fBUS
FB_CLK
fFLASH
MHz
5
—
50
—
Bus clock
—
60
MHz
FlexBus clock
—
50
MHz
Flash clock
—
25
MHz
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
23
General
Table 9. Device clock specifications (continued)
Symbol
fDDR
fLPTMR
Description
Min.
Max.
Unit
DDR clock
—
150
MHz
LPTMR clock
—
25
MHz
Notes
VLPR mode1
fSYS
System and core clock
—
4
MHz
fBUS
Bus clock
—
4
MHz
FlexBus clock
—
4
MHz
fFLASH
Flash clock
—
1
MHz
fLPTMR
LPTMR clock
—
4
MHz
FB_CLK
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, and I2C signals.
Table 10. General switching specifications
Symbol
tio50
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
16
—
ns
2
External reset pulse width (digital glitch filter disabled)
100
—
ns
2
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time (high drive strength)
—
TBD
ns
3
—
TBD
ns
4
—
TBD
ns
3
—
TBD
ns
4
—
TBD
ns
3
—
TBD
ns
4
• Slew disabled
• Slew enabled
tio50
Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled
tio60
Port rise and fall time (high drive strength)
• Slew disabled
• Slew enabled
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
24
Preliminary
Freescale Semiconductor, Inc.
General
Table 10. General switching specifications (continued)
Symbol
tio60
Description
Min.
Max.
Unit
Notes
—
TBD
ns
3
—
TBD
ns
4
—
TBD
ns
5
—
TBD
ns
6
—
TBD
ns
7
—
TBD
ns
8
—
TBD
ns
9
• DDR1
—
TBD
ns
10
• DDR2
—
TBD
ns
11
Port fall time
—
TBD
ns
9
• DDR1
—
TBD
ns
10
• DDR2
—
TBD
ns
11
Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled
ttamper
Port rise and fall time (high drive strength)
• Slew disabled
• Slew enabled
ttamper
Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled
tddr
Port rise time
• LPDDR
tddr
• LPDDR
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 25pF load
4. 15pF load
5. 75pF load
6. 15pF load
7. 75pF load
8. 15pF load
9. DDR —rise and fall times at 50 Ω transmission line impedance terminated to 0.5 × VDD_DDR + 5 pF load.
10. Rising slew rate measured between 0.5 × VDD_DDR and 0.5 × VDD_DDR + 250 mV for all modes.
11. Falling slew rate measured between 0.5 × VDD_DDR and 0.5 × VDD_DDR – 250 mV for all modes.
5.4 Thermal specifications
5.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
Description
Min.
Max.
Unit
TJ
Die junction temperature
–40
125
°C
TA
Ambient temperature
–40
105
°C
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
25
Peripheral operating requirements and behaviors
5.4.2 Thermal attributes
Board type
Symbol
Description
Unit
Notes
Single-layer (1s)
RθJA
Thermal
43
resistance, junction
to ambient (natural
convection)
°C/W
1, 2
Four-layer (2s2p)
RθJA
Thermal
28
resistance, junction
to ambient (natural
convection)
°C/W
1,2, 3
Single-layer (1s)
RθJMA
Thermal
36
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
Four-layer (2s2p)
RθJMA
Thermal
25
resistance, junction
to ambient (200 ft./
min. air speed)
°C/W
1,3
—
RθJB
Thermal
17
resistance, junction
to board
°C/W
4
—
RθJC
Thermal
8
resistance, junction
to case
°C/W
5
—
ΨJT
Thermal
2
characterization
parameter, junction
to package top
outside center
(natural
convection)
°C/W
6
1.
2.
3.
4.
5.
6.
256 MAPBGA
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.
Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.
Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
6 Peripheral operating requirements and behaviors
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
26
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.1 Core modules
6.1.1 Debug trace timing specifications
Table 12. Debug trace operating behaviors
Symbol
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
MHz
Twl
Low pulse width
2
—
ns
Twh
High pulse width
2
—
ns
Tr
Clock and data rise time
—
3
ns
Tf
Clock and data fall time
—
3
ns
Ts
Data setup
3
—
ns
Th
Data hold
2
—
ns
Figure 4. TRACE_CLKOUT specifications
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Figure 5. Trace data specifications
6.1.2 JTAG electricals
Table 13. JTAG voltage range electricals
Symbol
J1
Description
Min.
Max.
Unit
Operating voltage
2.7
5.5
V
TCLK frequency of operation
MHz
• JTAG
—
10
• CJTAG
—
5
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
27
Peripheral operating requirements and behaviors
Table 13. JTAG voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J2
TCLK cycle period
1/J1
—
ns
J3
TCLK clock pulse width
• JTAG
100
—
ns
• CJTAG
200
—
ns
—
ns
1
ns
—
ns
—
ns
—
ns
—
ns
J4
TCLK rise and fall times
—
J5
TMS input data setup time to TCLK rise
• JTAG
• CJTAG
112
J6
TDI input data setup time to TCLK rise
8
J7
TMS input data hold time after TCLK rise
• JTAG
• CJTAG
53
3.4
3.4
J8
TDI input data hold time after TCLK rise
3.4
J9
TCLK low to TMS data valid
• JTAG
• CJTAG
—
J10
J11
48
ns
85
TCLK low to TDO data valid
Output data hold/invalid time after clock
edge1
—
48
ns
—
3
ns
1. They are common for JTAG and CJTAG.
J2
J3
J3
TCLK (input)
J4
J4
Figure 6. Test clock input timing
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
28
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
TCLK
J5
Data inputs
J6
Input data valid
J7
Data outputs
Output data valid
J8
Data outputs
J7
Data outputs
Output data valid
Figure 7. Boundary scan (JTAG) timing
TCLK
J9
TDI/TMS
J10
Input data valid
J11
TDO
Output data valid
J12
TDO
J11
TDO
Output data valid
Figure 8. Test Access Port timing
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
29
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 9. TRST timing
6.2 System modules
There are no specifications necessary for the device's system modules.
6.3 Clock modules
6.3.1 MCG specifications
Table 14. MCG specifications
Symbol
Description
Min.
Typ.
Max.
Unit
—
32.768
—
kHz
31.25
—
39.0625
kHz
Internal reference (slow clock) current
—
TBD
—
µA
Δfdco_res_t
Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
—
± 0.3
± 0.6
%fdco
1
Δfdco_res_t
Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
± 0.2
± 0.5
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
± 10
—
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
—
± 4.5
—
%fdco
1
4
MHz
fints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) — user
trimmed
Iints
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
5
MHz
Internal reference (fast clock) current
—
TBD
—
µA
Iintf
Notes
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
30
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
kHz
floc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
31.25
—
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
—
23.99
—
MHz
—
47.97
—
MHz
—
71.99
—
MHz
—
95.98
—
MHz
—
180
—
—
150
—
FLL accumulated jitter of DCO output over a 1µs
time window
—
TBD
—
ps
FLL target frequency acquisition time
—
—
1
ms
8
—
16
MHz
Notes
FLL
ffll_ref
fdco
FLL reference frequency range
DCO output
frequency range
Low range (DRS=00)
2, 3
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
frequency
2
Low range (DRS=00)
4, 5
732 × ffll_ref
Mid range (DRS=01)
1464 × ffll_ref
Mid-high range (DRS=10)
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
• fVCO = 98 MHz
Jacc_fll
tfll_acquire
ps
6
PLL0,1
fpll_ref
PLL reference frequency range
fvcoclk_2x
VCO output frequency
fvcoclk
PLL output frequency
fvcoclk_90
Ipll
—
90
PLL quadrature output frequency
PLL operating current (fast)
—
180
—
90
—
TBD
360
180
180
—
MHz
MHz
MHz
µA
7
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
31
Peripheral operating requirements and behaviors
Table 14. MCG specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
—
TBD
—
µA
Ipll
PLL operating current (fast)
tpll_lock
Lock detector detection time
—
—
100 × 10-6
+ 1075(1/
fpll_ref)
s
Jcyc_pll
Jitter (cycle to cycle)
—
50
TBD
ps
Jacc_pll
Jitter (accumulated)
—
500
TBD
ps
Notes
7
8
9
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
9. Accumulated jitter will depend on VCO frequency and VDIV.
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1
Symbol
VDD
IDDOSC
Oscillator DC electrical specifications
Table 15. Oscillator DC electrical specifications
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
Supply current — low-power mode (HGO=0)
Notes
1
• 32 kHz
—
500
—
nA
• 4 MHz
—
200
—
μA
• 8 MHz (RANGE=01)
—
300
—
μA
• 16 MHz
—
950
—
μA
• 24 MHz
—
1.2
—
mA
• 32 MHz
—
1.5
—
mA
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
32
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
IDDOSC
Supply current — high gain mode (HGO=1)
Typ.
Max.
Unit
Notes
1
• 32 kHz
—
25
—
μA
• 4 MHz
—
400
—
μA
• 8 MHz (RANGE=01)
—
500
—
μA
• 16 MHz
—
2.5
—
mA
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
EXTAL load capacitance
—
—
—
2, 3
Cy
XTAL load capacitance
—
—
—
2, 3
RF
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
10
—
MΩ
Feedback resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
—
1
—
MΩ
Series resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
Series resistor — low-frequency, high-gain mode
(HGO=1)
—
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
—
—
—
kΩ
—
0
—
kΩ
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
0.6
—
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
—
VDD
—
V
RS
2, 4
Series resistor — high-frequency, high-gain
mode (HGO=1)
Vpp5
1.
2.
3.
4.
VDD=3.3 V, Temperature =25 °C
See crystal or resonator manufacturer's recommendation
Cx,Cy can be provided by using either the integrated capacitors or by using external components.
When low power mode is selected, RF is integrated and must not be attached externally.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
33
Peripheral operating requirements and behaviors
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2
Symbol
Oscillator frequency specifications
Table 16. Oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
fosc_lo
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
—
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal
Input clock frequency (external clock mode)
—
—
60
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
—
1000
—
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
500
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
—
0.6
—
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
tcst
Notes
1
2, 3
4, 5
1. Frequencies less than 8 MHz are not in the PLL range.
2. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
3. When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it
remains within the limits of the DCO input clock frequency.
4. Proper PC board layout procedures must be followed to achieve specifications.
5. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register
being set.
6.3.3 32kHz Oscillator Electrical Characteristics
This section describes the module electrical characteristics.
6.3.3.1
Symbol
VBAT
RF
32kHz oscillator DC electrical specifications
Table 17. 32kHz oscillator DC electrical specifications
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
—
100
—
MΩ
Internal feedback resistor
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
34
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 17. 32kHz oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Cpara
Parasitical capacitance of EXTAL32 and XTAL32
—
5
7
pF
Vpp1
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be connected to
any other devices.
6.3.3.2
Symbol
fosc_lo
tstart
32kHz oscillator frequency specifications
Table 18. 32kHz oscillator frequency specifications
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
—
32.768
—
kHz
Crystal start-up time
—
1000
—
ms
Notes
1
1. Proper PC board layout procedures must be followed to achieve specifications.
6.4 Memories and memory interfaces
6.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
6.4.1.1
Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 19. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm4
Notes
Program Phrase high-voltage time
—
7.5
TBD
μs
thversscr
Erase Flash Sector high-voltage time
—
13
TBD
ms
1
thversblk
Erase Flash Block high-voltage time
—
425
TBD
ms
1
1. Maximum time based on expectations at cycling end-of-life.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
35
Peripheral operating requirements and behaviors
6.4.1.2
Symbol
Flash timing specifications — commands
Table 20. Flash command timing specifications
Min.
Typ.
Max.
Unit
Read 1s Block execution time
—
1.5
TBD
ms
trd1sec4k
Read 1s Section execution time (4KB flash)
—
50
TBD
μs
1
tpgmchk
Program Check execution time
—
35
TBD
μs
1
trdrsrc
Read Resource execution time
—
35
TBD
μs
1
tpgm8
Program Phrase execution time
—
65
TBD
μs
tersblk
Erase Flash Block execution time
—
450
TBD
ms
2
tersscr
Erase Flash Sector execution time
—
15
TBD
ms
2
Program Section execution time (4KB flash)
—
20
TBD
ms
trd1all
Read 1s All Blocks execution time
—
1.5
TBD
ms
trdonce
Read Once execution time
—
17
TBD
μs
Program Once execution time
—
65
TBD
μs
tersall
Erase All Blocks execution time
—
900
TBD
ms
2
tvfykey
Verify Backdoor Access Key execution time
—
25
TBD
μs
1
trd1blk
tpgmsec4k
tpgmonce
Description
Notes
1
Swap Control execution time
tswapx01
• control code 0x01
—
185
TBD
μs
tswapx02
• control code 0x02
—
65
TBD
μs
tswapx04
• control code 0x04
—
65
TBD
μs
tswapx08
• control code 0x08
—
25
TBD
μs
—
TBD
TBD
ms
tpgmpart
Program Partition for EEPROM execution time
Set FlexRAM Function execution time:
tsetram64k
• 64 KB EEPROM backup
—
TBD
TBD
ms
tsetram128k
• 128 KB EEPROM backup
—
TBD
TBD
ms
tsetram256k
• 256 KB EEPROM backup
—
TBD
TBD
ms
tsetram512k
• 512 KB EEPROM backup
—
TBD
TBD
ms
—
100
TBD
μs
teewr8bers
Byte-write to erased FlexRAM location execution
time
3
Byte-write to FlexRAM execution time:
teewr8b64k
• 64 KB EEPROM backup
—
TBD
TBD
ms
teewr8b128k
• 128 KB EEPROM backup
—
TBD
TBD
ms
teewr8b256k
• 256 KB EEPROM backup
—
TBD
TBD
ms
teewr8b512k
• 512 KB EEPROM backup
—
TBD
TBD
ms
—
100
TBD
μs
teewr16bers
16-bit write to erased FlexRAM location
execution time
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
36
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 20. Flash command timing specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
16-bit write to FlexRAM execution time:
teewr16b64k
• 64 KB EEPROM backup
—
TBD
TBD
ms
teewr16b128k
• 128 KB EEPROM backup
—
TBD
TBD
ms
teewr16b256k
• 256 KB EEPROM backup
—
TBD
TBD
ms
teewr16b512k
• 512 KB EEPROM backup
—
TBD
TBD
ms
—
200
TBD
μs
teewr32bers
32-bit write to erased FlexRAM location
execution time
teewr32b64k 32-bit-write to FlexRAM execution time:
teewr32b128k
• 64 KB EEPROM backup
—
TBD
TBD
ms
teewr32b256k
• 128 KB EEPROM backup
—
TBD
TBD
ms
teewr32b512k
• 256 KB EEPROM backup
—
TBD
TBD
ms
• 512 KB EEPROM backup
—
TBD
TBD
ms
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3
Flash (FTFE) current and power specfications
Table 21. Flash (FTFE) current and power specfications
Symbol
Description
IDD_PGM
Worst case programming current in program flash
6.4.1.4
Symbol
Typ.
Unit
10
mA
Reliability specifications
Table 22. NVM reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k
Data retention after up to 10 K cycles
5
50
—
years
2
tnvmretp1k
Data retention after up to 1 K cycles
10
100
—
years
2
tnvmretp100
Data retention after up to 100 cycles
15
100
—
years
2
10 K
35 K
—
cycles
3
nnvmcycp
Cycling endurance
Data Flash
tnvmretd10k
Data retention after up to 10 K cycles
5
50
—
years
2
tnvmretd1k
Data retention after up to 1 K cycles
10
100
—
years
2
tnvmretd100
Data retention after up to 100 cycles
15
100
—
years
2
10 K
35 K
—
cycles
3
nnvmcycd
Cycling endurance
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
37
Peripheral operating requirements and behaviors
Table 22. NVM reliability specifications (continued)
Symbol
Description
Min.
Typ.1
Max.
Unit
Notes
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
5
50
—
years
2
tnvmretee10
Data retention up to 10% of write endurance
10
100
—
years
2
tnvmretee1
Data retention up to 1% of write endurance
15
100
—
years
2
Write endurance
4
nnvmwree16
• EEPROM backup to FlexRAM ratio = 16
TBD
TBD
—
writes
nnvmwree128
• EEPROM backup to FlexRAM ratio = 128
TBD
TBD
—
writes
nnvmwree512
• EEPROM backup to FlexRAM ratio = 512
TBD
TBD
—
writes
nnvmwree4k
• EEPROM backup to FlexRAM ratio = 4096
TBD
TBD
—
writes
nnvmwree32k
• EEPROM backup to FlexRAM ratio =
32,768
TBD
TBD
—
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
25°C profile. Engineering Bulletin EB618 does not apply to this technology.
2. Data retention is based on Tjavg = 55°C (temperature profile over the lifetime of the application).
3. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
4. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling
endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and
typical values assume all byte-writes to FlexRAM.
6.4.1.5
Write endurance to FlexRAM for EEPROM
TBD
6.4.2 EzPort Switching Specifications
Table 23. EzPort switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
EP1
EZP_CK frequency of operation (all commands except
READ)
—
fSYS/2
MHz
EP1a
EZP_CK frequency of operation (READ command)
—
fSYS/8
MHz
EP2
EZP_CS negation to next EZP_CS assertion
2 x tEZP_CK
—
ns
EP3
EZP_CS input valid to EZP_CK high (setup)
5
—
ns
EP4
EZP_CK high to EZP_CS input invalid (hold)
5
—
ns
EP5
EZP_D input valid to EZP_CK high (setup)
2
—
ns
EP6
EZP_CK high to EZP_D input invalid (hold)
5
—
ns
EP7
EZP_CK low to EZP_Q output valid
—
16
ns
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
38
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 23. EzPort switching specifications (continued)
Num
Description
Min.
Max.
Unit
EP8
EZP_CK low to EZP_Q output invalid (hold)
0
—
ns
EP9
EZP_CS negation to EZP_Q tri-state
—
12
ns
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EP5
EP6
EZP_D (input)
Figure 10. EzPort Timing Diagram
6.4.3 NFC specifications
The NAND flash controller (NFC) implements the interface to standard NAND flash
memory devices. This section describes the timing parameters of the NFC.
In the following table:
• TH is the flash clock high time and
• TL is flash clock low time,
which are defined as:
T NFC = T L + T H =
T input clock
SCALER
The SCALER value is derived from the fractional divider specified in the SIM's
CLKDIV4 register:
SCALER =
SIM_CLKDIV4[NFCFRAC] + 1
SIM_CLKDIV4[NFCDIV] + 1
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
39
Peripheral operating requirements and behaviors
In case the reciprocal of SCALER is an integer, the duty cycle of NFC clock is 50%,
means TH = TL. In case the reciprocal of SCALER is not an integer:
T L = (1 + SCALER / 2) x
T H = (1 – SCALER / 2) x
T NFC
2
T NFC
2
For example, if SCALER is 0.2, then TH = TL = TNFC/2.
TNFC
TH
TL
However, if SCALER is 0.667, then TL = 2/3 x TNFC and TH = 1/3 x TNFC.
TNFC
TH
TL
NOTE
The reciprocal of SCALER must be a multiple of 0.5. For
example, 1, 1.5, 2, 2.5, etc.
Table 24. NFC specifications
Num
Description
Min.
Max.
Unit
tCLS
NFC_CLE setup time
2TH + TL – 1
—
ns
tCLH
NFC_CLE hold time
TH + TL – 1
—
ns
tCS
NFC_CEn setup time
2TH + TL – 1
—
ns
tCH
NFC_CEn hold time
TH + TL
—
ns
tWP
NFC_WP pulse width
TL – 1
—
ns
tALS
NFC_ALE setup time
2TH + TL
—
ns
tALH
NFC_ALE hold time
TH + TL
—
ns
tDS
Data setup time
TL – 1
—
ns
tDH
Data hold time
TH – 1
—
ns
tWC
Write cycle time
TH + TL – 1
—
ns
tWH
NFC_WE hold time
TH – 1
—
ns
tRR
Ready to NFC_RE low
4TH + 3TL + 90
—
ns
tRP
NFC_RE pulse width
TL + 1
—
ns
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
40
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 24. NFC specifications (continued)
Num
Description
Min.
Max.
Unit
tRC
Read cycle time
TL + TH – 1
—
ns
tREH
NFC_RE high hold time
TH – 1
—
ns
tIS
Data input setup time
11
—
ns
NFC_CLE
tCLS
tCLH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
tDH
NFC_IOn
Figure 11. Command latch cycle timing
NFC_ALE
tALS
tALH
NFC_CEn
tCS
tWP
tCH
NFC_WE
tDS
NFC_IOn
tDH
address
Figure 12. Address latch cycle timing
tCS
tCH
tWC
NFC_CEn
tWP
tWH
tDS
tDH
NFC_WE
NFC_IOn
data
data
data
Figure 13. Write data latch cycle timing
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
41
Peripheral operating requirements and behaviors
tCH
tRC
NFC_CEn
tREH
tRP
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 14. Read data latch cycle timing in non-fast mode
tCH
tRC
NFC_CEn
tRP
tREH
NFC_RE
tIS
NFC_IOn
data
data
data
tRR
NFC_RB
Figure 15. Read data latch cycle timing in fast mode
6.4.4 DDR controller specifications
The following timing numbers must be followed to properly latch or drive data onto the
DDR memory bus. All timing numbers are relative to the DQS byte lanes.
Table 25. DDR controller — AC timing specifications
Symbol
Description
Min.
Max.
Unit
Frequency of operation
Notes
2
• DDR1
83.3
150
MHz
• DDR2
1251
150
MHz
50
150
MHz
• LPDDR
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
42
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 25. DDR controller — AC timing specifications (continued)
Symbol
Description
tDDRCK
Clock period
VOX-AC
Min.
Max.
Unit
• DDR1
6.6
12
ns
• DDR2
6.6
8
ns
• LPDDR
6.6
20
ns
0.5 x VDD_DDR
– 0.2 V
0.5 x VDD_DDR
+ 0.2 V
V
0.5 x VDD_DDR
– 0.125 V
0.5 x VDD_DDR
+ 0.125 V
V
0.4 x VDD_DDR
0.4 x VDD_DDR
DDRCK AC differential cross point voltage
• DDR1
• DDR2
• LPDDR
1.
2.
3.
4.
5.
6.
7.
8.
Notes
V
tDDRCKH
Pulse width high
0.45
0.55
tDDRCK
3
tDDRCKL
Pulse width low
0.45
0.55
tDDRCK
3
4
tCMV
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output valid
0.5 x tDDRCK –
1
—
ns
tCMH
Address, DDR_CKE, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CSn — output hold
0.5 x tDDRCK –
1
—
ns
tDQSS
Write command to first DQS latching transition
WL – 0.2 x
tDDRCK
WL + 0.2 x
tDDRCK
ns
tQS
Data and data mask output setup (DQ→DQS)
relative to DQS (DDR write mode)
0.25 x tDDRCK
–1
—
ns
5, 6
tQH
Data and data mask output hold (DQS→DQ)
relative to DQS (DDR write mode)
0.25 x tDDRCK
–1
—
ns
7
tDQSQ
DQS-DQ skew for DQS and associated DQ
signals
– (0.25 x
tDDRCK – 1)
0.25 x tDDRCK
–1
ns
8
This is minimum frequency of operation according to JEDEC DDR2 specification.
DDR data rate = 2 x DDR clock frequency
Pulse width high plus pulse width low cannot exceed min and max clock period.
Command output valid should be 1/2 the memory bus clock (tDDRCK) plus some minor adjustments for process,
temperature, and voltage variations.
This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be
larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0].
The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1];
DDR_DQ[7:0] is relative to DDR_DQS[0]
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
43
Peripheral operating requirements and behaviors
tDDRCKL
tDDRCKH
tDDRCK
DDR_CLK
DDR_CLK
tCMV
DDR_CSn, DDR_WE
tCMH
CMD
DDR_CAS, DDR_RAS
tDQSS
DDR_An
ROW
COL
tQS
DDR_DMn
tQH
DDR_DQSn
tQS
DDR_DQn
WD1
WD2
WD3 WD4
tQH
Figure 16. DDR write timing
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
44
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
tDDRCK
tDDRCKH
tDDRCKL
DDR_CLK
DDR_CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
CMD
tCMV
ROW
tCMH
COL
CL=2.5
DQS read
postamble
DQS read
preamble
DDR_DQS (CL=2.5)
DDR_DQn (CL=2.5)
RD1
CL=3
DDR_DQS (CL=3)
RD2 RD3
DQS read
preamble
RD4
DQS read
postamble
tIH
DDR_DQn (CL=3)
RD1
RD2
RD3
RD4
tIS
Figure 17. DDR read timing
Figure 18. DDR read timing, DQ vs. DQS
6.4.5 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
45
Peripheral operating requirements and behaviors
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 26. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Frequency of operation
—
FB_CLK
MHz
FB1
Clock period
20
—
ns
FB2
Address, data, and control output valid
—
11.5
ns
1
FB3
Address, data, and control output hold
0.5
—
ns
1
FB4
Data and FB_TA input setup
8.5
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 27. Flexbus full voltage range switching specifications
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
—
FB_CLK
MHz
1/FB_CLK
—
ns
Frequency of operation
Notes
FB1
Clock period
FB2
Address, data, and control output valid
—
13.5
ns
1
FB3
Address, data, and control output hold
0
—
ns
1
FB4
Data and FB_TA input setup
13.7
—
ns
2
FB5
Data and FB_TA input hold
0.5
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
46
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB3
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
Figure 19. FlexBus read timing diagram
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
47
Peripheral operating requirements and behaviors
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 20. FlexBus write timing diagram
6.5 Security and integrity modules
6.5.1 DryIce Tamper Electrical Specifications
Table 28. DryIce Tamper Electrical Specifications
Symbol
Description
Min
VBAT
3.3V supply voltage
1.71
Typ
Max
Unit
3.6
V
Notes
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
48
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 28. DryIce Tamper Electrical Specifications (continued)
Symbol
Description
ITAM
Supply current
Min
Typ
Max
Unit
• clock tamper enabled
0.9
TBD
μA
• clock and voltage tamper enabled
1.01
TBD
μA
• clock, voltage and temperature tamper enabled
1.35
TBD
μA
EXTAL32 input clock
32.768
kHz
Notes
1
Low Voltage Detect
• assertion
1.55
1.60
1.65
V
• negation
1.7
1.75
1.8
V
3.65
3.7
3.75
V
High Voltage Detect assertion
Voltage Tamper Detect operational temperature
• no false alarms
-50
150
°C
• with possible false alarms
-60
160
°C
Temperature Tamper Detect assertion
2
• low temperature detect
-55
-45
°C
• high temperature detect
110
130
°C
1.6
3.7
V
< 1.5
> 3.8
V
Temperature Tamper Detect operational voltage
• no false alarms
• with possible false alarms
Clock Tamper Detect assertion
3
• low frequency
20
• high frequency
40
• delay after loss of clock
kHz
kHz
2
ms
Clock Tamper Detect operational temperature
• no false alarms
-50
150
°C
• with possible false alarms
-60
160
1.6
3.7
V
< 1.5
> 3.8
V
Clock Tamper Detect operational voltage
• no false alarms
• with possible false alarms
1. EXTAL32 oscillator must be enabled before enabling DryIce tamper detect.
2. Temperature tamper detector assertion/negation is refreshed each 28 EXTAL32 clock cycles.
3. Clock tamper detector assertion/negation is refreshed each 28 EXTAL32 clock cycles.
6.6 Analog
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
49
Peripheral operating requirements and behaviors
6.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 29 and Table 30 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are
not direct device pins. Accuracy specifications for these pins are defined in Table 31 and
Table 32.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
6.6.1.1
16-bit ADC operating conditions
Table 29. 16-bit ADC operating conditions
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
ΔVDDA
Supply voltage
Delta to VDD (VDDVDDA)
-100
0
+100
mV
2
ΔVSSA
Ground voltage
Delta to VSS (VSSVSSA)
-100
0
+100
mV
2
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
V
VREFL
Reference
voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage
VREFL
—
VREFH
V
CADIN
Input
capacitance
• 16 bit modes
—
8
10
pF
• 8/10/12 bit
modes
—
4
5
—
2
5
Symbol
RADIN
RAS
fADCK
fADCK
Input resistance
Analog source
resistance
13/12 bit modes
ADC conversion
clock frequency
≤ 13 bit modes
ADC conversion
clock frequency
16 bit modes
fADCK < 4MHz
Notes
kΩ
3
—
—
5
kΩ
4
1.0
—
18.0
MHz
4
2.0
—
12.0
MHz
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
50
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 29. 16-bit ADC operating conditions (continued)
Symbol
Crate
Description
Conditions
ADC conversion
rate
≤ 13 bit modes
Min.
Typ.1
Max.
Unit
Notes
5
No ADC hardware
averaging
20.000
—
818.330
Ksps
Continuous
conversions enabled,
subsequent conversion
time
Crate
ADC conversion
rate
16 bit modes
5
No ADC hardware
averaging
37.037
—
461.467
Ksps
Continuous
conversions enabled,
subsequent conversion
time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS/
CAS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool: http://cache.freescale.com/
files/soft_dev_tools/software/app_software/converters/ADC_CALCULATOR_CNV.zip?fpsp=1
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
Z AS
R AS
Z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
R ADIN
ADC SAR
ENGINE
V ADIN
C AS
V AS
R ADIN
INPUT PIN
INPUT PIN
R ADIN
R ADIN
INPUT PIN
C ADIN
Figure 21. ADC input impedance equivalency diagram
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
51
Peripheral operating requirements and behaviors
6.6.1.2
16-bit ADC electrical characteristics
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)
Symbol
Description
IDDA_ADC
Supply current
fADACK
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
EFS
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
—
1.7
mA
3
• ADLPC=1, ADHSC=0
1.2
2.4
3.9
MHz
• ADLPC=1, ADHSC=1
3.0
4.0
7.3
MHz
tADACK = 1/
fADACK
• ADLPC=0, ADHSC=0
2.4
5.2
6.1
MHz
• ADLPC=0, ADHSC=1
4.4
6.2
9.5
MHz
LSB4
5
LSB4
5
LSB4
5
LSB4
VADIN =
VDDA
See Reference Manual chapter for sample times
Total unadjusted
error
• 12 bit modes
—
±4
±6.8
• <12 bit modes
—
±1.4
±2.1
Differential nonlinearity
• 12 bit modes
—
±0.7
-1.1 to
+1.9
• <12 bit modes
—
±0.2
• 12 bit modes
—
±1.0
• <12 bit modes
—
±0.5
-0.7 to
+0.5
• 12 bit modes
—
-4
-5.4
• <12 bit modes
—
-1.4
-1.8
Integral nonlinearity
Full-scale error
-0.3 to 0.5
-2.7 to
+1.9
5
EQ
ENOB
Quantization
error
• 16 bit modes
—
-1 to 0
—
• ≤13 bit modes
—
—
±0.5
Effective number 16 bit differential mode
of bits
• Avg=32
LSB4
6
• Avg=4
12.8
14.5
—
bits
11.9
13.8
—
bits
12.2
13.9
—
bits
11.4
13.1
—
bits
16 bit single-ended mode
• Avg=32
• Avg=4
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
16 bit differential mode
6.02 × ENOB + 1.76
7
• Avg=32
16 bit single-ended mode
• Avg=32
dB
—
–94
—
dB
—
-85
—
dB
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
52
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
SFDR
Description
Conditions1
Spurious free
dynamic range
16 bit differential mode
Min.
16 bit single-ended mode
EIL
Max.
Unit
Notes
7
• Avg=32
• Avg=32
Typ.2
82
95
—
dB
78
90
—
dB
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
VTEMP25
Temp sensor
slope
–40°C to 105°C
—
1.715
—
mV/°C
Temp sensor
voltage
25°C
—
719
—
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power).
For lowest power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock
speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock <16MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock <12MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock <12MHz.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
53
Peripheral operating requirements and behaviors
Figure 22. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Figure 23. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
54
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.1.3
16-bit ADC with PGA operating conditions
Table 31. 16-bit ADC with PGA operating conditions
Description
Conditions
Min.
Typ.1
Max.
Unit
VDDA
Supply voltage
Absolute
1.71
—
3.6
V
VREFPGA
PGA ref voltage
Symbol
VADIN
VCM
RPGAD
VREF_OU VREF_OU VREF_OU
T
T
T
V
Notes
2, 3
Input voltage
VSSA
—
VDDA
V
Input Common
Mode range
VSSA
—
VDDA
V
Gain = 1, 2, 4, 8
—
128
—
kΩ
IN+ to IN-4
Gain = 16, 32
—
64
—
Gain = 64
—
32
—
Differential input
impedance
RAS
Analog source
resistance
—
100
—
Ω
5
TS
ADC sampling
time
1.25
—
—
µs
6
18.484
—
450
Ksps
7
37.037
—
250
Ksps
8
Crate
ADC conversion
rate
≤ 13 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
16 bit modes
No ADC hardware
averaging
Continuous
conversions enabled
Peripheral clock = 50
MHz
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. ADC must be configured to use the internal voltage reference (VREF_OUT)
3. PGA reference is internally connected to the VREF_OUT pin. If the user wishes to drive VREF_OUT with a voltage other
than the output of the VREF module, the VREF module must be disabled.
4. For single ended configurations the input impedance of the driven input is RPGAD/2
5. The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
6. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
8 MHz ADC clock.
7. ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1
8. ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
55
Peripheral operating requirements and behaviors
6.6.1.4
16-bit ADC with PGA characteristics
Table 32. 16-bit ADC with PGA characteristics
Symbol
Description
Conditions
IDDA_PGA
Supply current
Low power
(ADC_PGA[PGALPb]=0)
IDC_PGA
Input DC current
G
BW
Gain4
Input signal
bandwidth
Min.
Typ.1
Max.
Unit
Notes
—
420
644
μA
2
A
3
Gain =1, VREFPGA=1.2V,
VCM=0.5V
—
1.54
—
μA
Gain =64, VREFPGA=1.2V,
VCM=0.1V
—
0.57
—
μA
• PGAG=0
0.95
1
1.05
• PGAG=1
1.9
2
2.1
• PGAG=2
3.8
4
4.2
• PGAG=3
7.6
8
8.4
• PGAG=4
15.2
16
16.6
• PGAG=5
30.0
31.6
33.2
• PGAG=6
58.8
63.3
67.8
—
—
4
kHz
—
—
40
kHz
—
-84
—
dB
VDDA= 3V
±100mV,
fVDDA= 50Hz,
60Hz
VCM=
500mVpp,
fVCM= 50Hz,
100Hz
• 16-bit modes
• < 16-bit modes
PSRR
Power supply
rejection ratio
CMRR
Common mode
rejection ratio
• Gain=1
—
-84
—
dB
• Gain=64
—
-85
—
dB
Input offset
voltage
• Chopping disabled
(ADC_PGA[PGACHPb]
=1)
• Chopping enabled
(ADC_PGA[PGACHPb]
=0)
—
2.4
TBD
mV
—
0.2
—
mV
Output offset =
VOFS*(Gain+1)
—
—
10
µs
5
—
TBD
TBD
ppm/°C
0 to 50°C
—
TBD
TBD
ppm/°C
—
TBD
TBD
ppm/°C
0 to 50°C, ADC
Averaging=32
—
TBD
TBD
%/V
—
TBD
TBD
%/V
VDDA from 1.71
to 3.6V
VOFS
TGSW
Gain switching
settling time
dG/dT
Gain drift over
temperature
dVOFS/dT
Offset drift over
temperature
dG/dVDDA
Gain drift over
supply voltage
Gain=1
RAS < 100Ω
• Gain=1
• Gain=64
Gain=1
• Gain=1
• Gain=64
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
56
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 32. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
EIL
Input leakage
error
All modes
Min.
Typ.1
Max.
IIn × RAS
Unit
Notes
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
VPP,DIFF
SNR
THD
SFDR
ENOB
SINAD
Maximum
differential input
signal swing
V
6
16-bit
differential
mode,
Average=32
where VX = VREFPGA × 0.583
Signal-to-noise
ratio
• Gain=1
80
90
—
dB
• Gain=64
52
66
—
dB
Total harmonic
distortion
• Gain=1
85
100
—
dB
• Gain=64
49
95
—
dB
Spurious free
dynamic range
• Gain=1
85
105
—
dB
• Gain=64
53
88
—
dB
Effective number
of bits
• Gain=1, Average=4
11.6
13.4
—
bits
• Gain=1, Average=8
TBD
12.7
—
bits
• Gain=64, Average=4
7.2
9.6
—
bits
• Gain=64, Average=8
TBD
8.7
—
bits
• Gain=1, Average=32
12.8
14.5
—
bits
• Gain=2, Average=32
11.0
14.3
—
bits
• Gain=4, Average=32
7.9
13.8
—
bits
• Gain=8, Average=32
7.3
13.1
—
bits
• Gain=16, Average=32
6.8
12.5
—
bits
• Gain=32, Average=32
6.8
11.5
—
bits
• Gain=64, Average=32
7.5
10.6
—
bits
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
16-bit
differential
mode,
Average=32,
fin=100Hz
16-bit
differential
mode,
Average=32,
fin=100Hz
16-bit
differential
mode,fin=100H
z
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to and ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
57
Peripheral operating requirements and behaviors
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
6.6.2 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
Typ.
Max.
Unit
Supply voltage
1.71
—
3.6
V
IDDHS
Supply current, High-speed mode (EN=1, PMODE=1)
—
—
200
μA
IDDLS
Supply current, low-speed mode (EN=1, PMODE=0)
—
—
20
μA
VAIN
Analog input voltage
VSS – 0.3
—
VDD
V
VAIO
Analog input offset voltage
—
—
20
mV
• CR0[HYSTCTR] = 00
—
5
—
mV
• CR0[HYSTCTR] = 01
—
10
—
mV
• CR0[HYSTCTR] = 10
—
20
—
mV
• CR0[HYSTCTR] = 11
—
30
—
mV
VH
Analog comparator hysteresis1
VCMPOh
Output high
VDD – 0.5
—
—
V
VCMPOl
Output low
—
—
0.5
V
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
—
—
40
μs
6-bit DAC current adder (enabled)
—
7
—
μA
IDAC6b
INL
6-bit DAC integral non-linearity
–0.5
—
0.5
LSB3
DNL
6-bit DAC differential non-linearity
–0.3
—
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,
VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
58
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.08
0.07
0.06
HYSTCTR
Setting
CM P Hystereris (V)
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 24. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0)
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
59
Peripheral operating requirements and behaviors
0.18
0.16
0.14
CMP
P Hystereris (V)
0.12
HYSTCTR
Setting
0.1
00
01
0
08
0.08
10
11
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
Vin level (V)
1.9
2.2
2.5
2.8
3.1
Figure 25. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1)
6.6.3 12-bit DAC electrical characteristics
6.6.3.1
Symbol
12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
V
VDACR
Reference voltage
1.13
3.6
V
TA
Temperature
−40
105
°C
CL
Output load capacitance
—
100
pF
IL
Output load current
—
1
mA
Notes
1
2
1. The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF_OUT)
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
60
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.6.3.2
Symbol
12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Description
IDDA_DACL Supply current — low-power mode
Min.
Typ.
Max.
Unit
—
—
150
μA
—
—
700
μA
Notes
P
IDDA_DAC Supply current — high-speed mode
HP
tDACLP
Full-scale settling time (0x080 to 0xF7F) —
low-power mode
—
100
200
μs
1
tDACHP
Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
—
0.7
1
μs
1
Vdacoutl
DAC output voltage range low — highspeed mode, no load, DAC set to 0x000
—
—
100
mV
Vdacouth
DAC output voltage range high — highspeed mode, no load, DAC set to 0xFFF
VDACR
−100
—
VDACR
mV
INL
Integral non-linearity error — high speed
mode
—
—
±8
LSB
2
DNL
Differential non-linearity error — VDACR > 2
V
—
—
±1
LSB
3
DNL
Differential non-linearity error — VDACR =
VREF_OUT
—
—
±1
LSB
4
VOFFSET
Offset error
—
±0.4
±0.8
%FSR
5
EG
Gain error
—
±0.1
±0.6
%FSR
5
Power supply rejection ratio, VDDA > = 2.4 V
60
90
dB
TCO
Temperature coefficient offset voltage
—
3.7
—
μV/C
TGE
Temperature coefficient gain error
—
0.000421
—
%FSR/C
Rop
Output resistance load = 3 kΩ
—
—
250
Ω
SR
Slew rate -80h→ F7Fh→ 80h
PSRR
1.
2.
3.
4.
5.
V/μs
• High power (SPHP)
1.2
1.7
—
• Low power (SPLP)
0.05
0.12
—
—
—
-80
CT
Channel to channel cross talk
BW
3dB bandwidth
6
dB
kHz
• High power (SPHP)
550
—
—
• Low power (SPLP)
40
—
—
Settling within ±1 LSB
The INL is measured for 0+100mV to VDACR−100 mV
The DNL is measured for 0+100 mV to VDACR−100 mV
The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V
Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
61
Peripheral operating requirements and behaviors
6. VDDA = 3.0V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode(DACx_C0:LPEN = 0), DAC set
to 0x800, Temp range from -40C to 105C
Figure 26. Typical INL error vs. digital code
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
62
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Figure 27. Offset at half scale vs. temperature
6.6.4 Voltage reference electrical specifications
Table 36. VREF full-range operating requirements
Symbol
Description
Min.
Max.
Unit
Supply voltage
1.71
3.6
V
TA
Temperature
−40
105
°C
CL
Output load capacitance
VDDA
100
nF
Notes
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of
the device.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
63
Peripheral operating requirements and behaviors
Table 37. VREF full-range operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
nominal VDDA and temperature=25C
1.1965
1.2
1.2027
V
Vout
Voltage reference output with— factory trim
1.1584
—
1.2376
V
Vout
Voltage reference output — user trim
1.198
—
1.202
V
Vstep
Voltage reference trim step
—
0.5
—
mV
Vtdrift
Temperature drift (Vmax -Vmin across the full
temperature range)
—
—
80
mV
Ibg
Bandgap only current
—
—
80
µA
1
Itr
High-power buffer current
—
—
TBD
mA
1
mV
1, 2
ΔVLOAD
Load regulation
• current = + 1.0 mA
—
2
—
• current = - 1.0 mA
—
5
—
Tstup
Buffer startup time
—
—
100
µs
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 38. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
TA
Temperature
0
50
°C
Notes
Table 39. VREF limited-range operating behaviors
Symbol
Vout
Description
Voltage reference output with factory trim
Min.
Max.
Unit
1.173
1.225
V
Notes
6.7 Timers
See General switching specifications.
6.8 Communication interfaces
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
64
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1
MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Table 40. MII signal switching specifications
Symbol
—
MII1
Description
RXCLK frequency
RXCLK pulse width high
Min.
Max.
Unit
—
25
MHz
35%
65%
RXCLK
period
MII2
RXCLK pulse width low
35%
65%
RXCLK
period
MII3
RXD[3:0], RXDV, RXER to RXCLK setup
5
—
ns
MII4
RXCLK to RXD[3:0], RXDV, RXER hold
5
—
ns
TXCLK frequency
—
25
MHz
35%
65%
TXCLK
—
MII5
TXCLK pulse width high
period
MII6
TXCLK pulse width low
35%
65%
TXCLK
period
MII7
TXCLK to TXD[3:0], TXEN, TXER invalid
2
—
ns
MII8
TXCLK to TXD[3:0], TXEN, TXER valid
—
25
ns
MII6
MII5
TXCLK (input)
MII8
MII7
TXD[n:0]
Valid data
TXEN
Valid data
TXER
Valid data
Figure 28. MII transmit signal timing diagram
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
65
Peripheral operating requirements and behaviors
MII2
MII1
MII3
MII4
RXCLK (input)
RXD[n:0]
Valid data
RXDV
Valid data
RXER
Valid data
Figure 29. MII receive signal timing diagram
6.8.1.2
RMII signal switching specifications
The following timing specs meet the requirements for RMII style interfaces for a range of
transceiver devices.
Table 41. RMII signal switching specifications
Num
—
Description
EXTAL frequency (RMII input clock RMII_CLK)
Min.
Max.
Unit
—
50
MHz
RMII1
RMII_CLK pulse width high
35%
65%
RMII_CLK
period
RMII2
RMII_CLK pulse width low
35%
65%
RMII_CLK
period
RMII3
RXD[1:0], CRS_DV, RXER to RMII_CLK setup
4
—
ns
RMII4
RMII_CLK to RXD[1:0], CRS_DV, RXER hold
2
—
ns
RMII7
RMII_CLK to TXD[1:0], TXEN invalid
4
—
ns
RMII8
RMII_CLK to TXD[1:0], TXEN valid
—
15
ns
6.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-date
standards, visit http://www.usb.org.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
66
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.3 USB DCD electrical specifications
Table 42. USB DCD electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDP_SRC
USB_DP source voltage (up to 250 μA)
0.5
—
0.7
V
Threshold voltage for logic high
0.8
—
2.0
V
VLGC
IDP_SRC
USB_DP source current
7
10
13
μA
IDM_SINK
USB_DM sink current
50
100
150
μA
RDM_DWN
D- pulldown resistance for data pin contact detect
14.25
—
24.8
kΩ
VDAT_REF
Data detect voltage
0.25
0.325
0.4
V
6.8.4 USB VREG electrical specifications
Table 43. USB VREG electrical specifications
Symbol
Description
Min.
Typ.1
Max.
Unit
VREGIN
Input supply voltage
2.7
—
5.5
V
IDDon
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
—
120
186
μA
IDDstby
Quiescent current — Standby mode, load
current equal zero
—
1.1
1.54
μA
IDDoff
Quiescent current — Shutdown mode
—
650
—
nA
—
—
4
μA
• VREGIN = 5.0 V and temperature=25C
• Across operating voltage and temperature
ILOADrun
Maximum load current — Run mode
—
—
120
mA
ILOADstby
Maximum load current — Standby mode
—
—
1
mA
VReg33out
Regulator output voltage — Input supply
(VREGIN) > 3.6 V
3
3.3
3.6
V
2.1
2.8
3.6
V
Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2.1
—
3.6
V
COUT
External output capacitor
1.76
2.2
8.16
μF
ESR
External output capacitor equivalent series
resistance
1
—
100
mΩ
ILIM
Short circuit current
—
290
—
mA
• Run mode
• Standby mode
VReg33out
Notes
2
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
67
Peripheral operating requirements and behaviors
6.8.5 ULPI timing specifications
The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin
Interface. Control and data timing requirements for the ULPI pins are given in the
following table. These timings apply to synchronous mode only. All timings are
measured with respect to the clock as seen at the USB_CLKIN pin.
Table 44. ULPI timing specifications
Num
Description
Min.
Typ.
Max.
Unit
USB_CLKIN
operating
frequency
—
60
—
MHz
USB_CLKIN duty
cycle
—
50
—
%
U1
USB_CLKIN clock
period
—
16.67
—
ns
U2
Input setup (control
and data)
5
—
—
ns
U3
Input hold (control
and data)
1
—
—
ns
U4
Output valid
(control and data)
—
—
9.5
ns
U5
Output hold
(control and data)
1
—
—
ns
U1
USB_CLKIN
U2
U3
ULPI_DIR/ULPI_NXT
(control input)
ULPI_DATAn (input)
U4
U5
ULPI_STP
(control output)
ULPI_DATAn (output)
Figure 30. ULPI timing diagram
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
68
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
6.8.6 CAN switching specifications
See General switching specifications.
6.8.7 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 45. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Frequency of operation
—
30
MHz
2 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
2
—
ns
1
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
2
DS5
DSPI_SCK to DSPI_SOUT valid
—
8.5
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
−2
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
15
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS7
(CPOL=0)
DSPI_SIN
DS8
Data
First data
Last data
DS5
DSPI_SOUT
First data
DS6
Data
Last data
Figure 31. DSPI classic SPI timing — master mode
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
69
Peripheral operating requirements and behaviors
Table 46. Slave mode DSPI timing (limited voltage range)
Num
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
V
15
MHz
4 x tBUS
—
ns
(tSCK/2) − 2
(tSCK/2) + 2
ns
Frequency of operation
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
14
ns
DS16
DSPI_SS inactive to DSPI_SOUT not driven
—
14
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Figure 32. DSPI classic SPI timing — slave mode
6.8.8 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provides DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 47. Master mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
V
1
—
15
MHz
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
70
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 47. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
4 x tBUS
—
ns
Notes
DS1
DSPI_SCK output cycle time
DS2
DSPI_SCK output high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DSPI_SCK to DSPI_SOUT valid
—
10
ns
DS6
DSPI_SCK to DSPI_SOUT invalid
-4.5
—
ns
DS7
DSPI_SIN to DSPI_SCK input setup
20.5
—
ns
DS8
DSPI_SCK to DSPI_SIN input hold
0
—
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS3
DS1
DS2
DS4
DSPI_SCK
DS8
DS7
(CPOL=0)
DSPI_SIN
Data
First data
Last data
DS5
DSPI_SOUT
First data
DS6
Data
Last data
Figure 33. DSPI classic SPI timing — master mode
Table 48. Slave mode DSPI timing (full voltage range)
Num
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
V
—
7.5
MHz
8 x tBUS
—
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DSPI_SCK input cycle time
DS10
DSPI_SCK input high/low time
DS11
DSPI_SCK to DSPI_SOUT valid
—
20
ns
DS12
DSPI_SCK to DSPI_SOUT invalid
0
—
ns
DS13
DSPI_SIN to DSPI_SCK input setup
2
—
ns
DS14
DSPI_SCK to DSPI_SIN input hold
7
—
ns
DS15
DSPI_SS active to DSPI_SOUT driven
—
19
ns
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
71
Peripheral operating requirements and behaviors
Table 48. Slave mode DSPI timing (full voltage range) (continued)
Num
DS16
Description
DSPI_SS inactive to DSPI_SOUT not driven
Min.
Max.
Unit
—
19
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DSPI_SOUT
First data
DS13
DS16
DS11
Data
Last data
DS14
DSPI_SIN
First data
Data
Last data
Figure 34. DSPI classic SPI timing — slave mode
6.8.9 I2C switching specifications
See General switching specifications.
6.8.10 UART switching specifications
See General switching specifications.
6.8.11 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 49. SDHC switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
72
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 49. SDHC switching specifications
(continued)
Num
Symbol
SD1
fpp
Description
Min.
Max.
Unit
Clock frequency (low speed)
0
400
kHz
fpp
Clock frequency (SD\SDIO full speed)
0
25
MHz
fpp
Clock frequency (MMC full speed)
0
20
MHz
fOD
Clock frequency (identification mode)
0
400
kHz
SD2
tWL
Clock low time
7
—
ns
SD3
tWH
Clock high time
7
—
ns
SD4
tTLH
Clock rise time
—
3
ns
SD5
tTHL
Clock fall time
—
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
SDHC output delay (output valid)
-5
6.5
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD7
tISU
SDHC input setup time
5
—
ns
SD8
tIH
SDHC input hold time
0
—
ns
SD3
SD2
SD1
SDHC_CLK
SD6
Output SDHC_CMD
Output SDHC_DAT[3:0]
SD7
SD8
Input SDHC_CMD
Input SDHC_DAT[3:0]
Figure 35. SDHC timing
6.8.12 I2S/SAI Switching Specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial clock
polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
73
Peripheral operating requirements and behaviors
is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been
inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the
frame sync (FS) signal shown in the following figures.
Table 50. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
3.6
Unit
Operating voltage
1.71
V
S1
I2S_MCLK cycle time1
40
S2
I2S_MCLK pulse width high/low
45%
55%
MCLK period
S3
I2S_TX_BCLK cycle time (output)1
80
—
ns
I2S_RX_BCLK cycle time (output)1
160
—
S4
I2S_TX_BCLK pulse width high/low
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
I2S_TX_BCLK to I2S_TXD valid
—
15
ns
S8
I2S_TX_BCLK to I2S_TXD invalid
0
—
ns
S9
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
25
—
ns
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S11
I2S_TX_FS input assertion to I2S_TXD output valid2
—
21
ns
ns
1. This parameter is limited in VLPx modes.
2. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 36. I2S/SAI timing — master modes
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
74
Preliminary
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 51. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
I2S_RX_BCLK cycle time (input)
80
—
ns
I2S_TX_BCLK cycle time (input)
160
—
S12
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
—
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
ns
S15
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
29
ns
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
0
—
ns
S17
I2S_RXD setup before I2S_RX_BCLK
10
—
ns
S18
I2S_RXD hold after I2S_RX_BCLK
2
—
ns
S19
I2S_TX_FS input assertion to I2S_TXD output valid1
—
21
ns
S11
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
I2S_TX_FS/
I2S_RX_FS (output)
S16
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
Figure 37. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
75
Dimensions
6.9.1 TSI electrical specifications
Table 52. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
VDDTSI
Operating voltage
1.71
—
3.6
V
Target electrode capacitance range
1
20
500
pF
1
fREFmax
Reference oscillator frequency
—
8
TBD
MHz
2
fELEmax
Electrode oscillator frequency
—
0.5
TBD
MHz
2
Internal reference capacitor
TBD
1
TBD
pF
Oscillator delta voltage
TBD
600
TBD
mV
2
—
1.133
1.5
μA
2, 3
—
36
50
—
1.133
1.5
μA
2, 4
—
36
50
CELE
CREF
VDELTA
IREF
IELE
Reference oscillator current source base current
• 1uA setting (REFCHRG=0)
• 32uA setting (REFCHRG=31)
Electrode oscillator current source base current
• 1uA setting (EXTCHRG=0)
• 32uA setting (EXTCHRG=31)
Notes
Pres5
Electrode capacitance measurement precision
—
8.3333
38.4
pF/count
5
Pres20
Electrode capacitance measurement precision
—
8.3333
38.4
pF/count
6
Pres100
Electrode capacitance measurement precision
—
8.3333
38.4
pF/count
7
MaxSens
Maximum sensitivity
0.003
12.5
—
fF/count
8
Resolution
—
—
16
bits
Response time @ 20 pF
8
15
25
μs
Current added in run mode
—
55
—
μA
Low power mode current adder
—
1.3
TBD
μA
Res
TCon20
ITSI_RUN
ITSI_LP
9
10
1.
2.
3.
4.
5.
6.
7.
8.
The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed.
Fixed external capacitance of 20 pF.
The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current.
The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current.
Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16.
Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16.
Sensitivity defines the minimum capacitance change when a single count from the TSI module changes, it is equal to (Cref
* Iext)/( Iref * PS * NSCN). Sensitivity depends on the configuration used. The typical value listed is based on the following
configuration: Iext = 5 μA, EXTCHRG = 4, PS = 128, NSCN = 2, Iref = 16 μA, REFCHRG = 15, Cref = 1.0 pF. The minimum
sensitivity describes the smallest possible capacitance that can be measured by a single count (this is the best sensitivity
but is described as a minimum because it’s the smallest number). The minimum sensitivity parameter is based on the
following configuration: Iext = 1 μA, EXTCHRG = 0, PS = 128, NSCN = 32, Iref = 32 μA, REFCHRG = 31, Cref= 0.5 pF
9. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1
electrode, EXTCHRG = 15.
10. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of
20 pF. Data is captured with an average of 7 periods window.
7 Dimensions
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
76
Preliminary
Freescale Semiconductor, Inc.
Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
Then use this document number
256-pin MAPBGA
98ASA00346D
8 Pinout
8.1 K61 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
E2
PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1
UART1_TX
SDHC0_D1
I2C1_SDA
RTC_CLKO
UT
F2
PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT
UART1_RX
SDHC0_D0
I2C1_SCL
SPI1_SIN
F3
PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK
UART1_CTS SDHC0_DCL
_b
K
G2
PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS SDHC0_CM
_b
D
G7
VDD
VDD
VDD
H7
VDDINT
VDDINT
VDDINT
H8
VSS
VSS
VSS
F1
PTF17
DISABLED
PTF17
SPI2_SCK
FTM0_CH4
UART0_RX
G1
PTF18
DISABLED
PTF18
SPI2_SOUT
FTM1_CH0
UART0_TX
G3
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0
UART3_TX
SDHC0_D3
G4
PTE5
DISABLED
PTE5
SPI1_PCS2
UART3_RX
SDHC0_D2
FTM3_CH0
H2
PTE6
DISABLED
PTE6
SPI1_PCS3
UART3_CTS I2S0_MCLK
_b
FTM3_CH1
H1
PTF19
DISABLED
PTF19
SPI2_SIN
FTM1_CH1
UART5_RX
H5
PTF20
DISABLED
PTF20
SPI2_PCS1
FTM2_CH0
UART5_TX
EzPort
SPI1_SOUT
USB_SOF_
OUT
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
77
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
H3
PTE7
DISABLED
H4
PTE8
ADC2_SE16 ADC2_SE16 PTE8
J1
PTE9
ADC2_SE17 ADC2_SE17 PTE9
J2
PTE10
DISABLED
K1
PTE11
K3
ALT2
PTE7
ALT3
ALT4
ALT5
ALT6
UART3_RTS I2S0_RXD0
_b
FTM3_CH2
I2S0_RXD1
UART5_TX
I2S0_RX_FS
FTM3_CH3
I2S0_TXD1
UART5_RX
I2S0_RX_BC
LK
FTM3_CH4
PTE10
UART5_CTS I2S0_TXD0
_b
FTM3_CH5
ADC3_SE16 ADC3_SE16 PTE11
UART5_RTS I2S0_TX_FS
_b
FTM3_CH6
PTE12
ADC3_SE17 ADC3_SE17 PTE12
I2S0_TX_BC
LK
FTM3_CH7
G8
VDD
VDD
VDD
H9
VSS
VSS
VSS
J3
PTE16
ADC0_SE4a ADC0_SE4a PTE16
SPI0_PCS0
UART2_TX
FTM_CLKIN
0
FTM0_FLT3
K2
PTE17
ADC0_SE5a ADC0_SE5a PTE17
SPI0_SCK
UART2_RX
FTM_CLKIN
1
LPTMR0_AL
T3
L4
PTE18
ADC0_SE6a ADC0_SE6a PTE18
SPI0_SOUT
UART2_CTS I2C0_SDA
_b
M3
PTE19
ADC0_SE7a ADC0_SE7a PTE19
SPI0_SIN
UART2_RTS I2C0_SCL
_b
L2
VSS
VSS
VSS
M1
USB0_DP
USB0_DP
USB0_DP
M2
USB0_DM
USB0_DM
USB0_DM
L1
VOUT33
VOUT33
VOUT33
L3
VREGIN
VREGIN
VREGIN
N1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
PGA2_DP/
ADC2_DP0/
ADC3_DP3/
ADC0_DP1
N2
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
PGA2_DM/
ADC2_DM0/
ADC3_DM3/
ADC0_DM1
P1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
PGA3_DP/
ADC3_DP0/
ADC2_DP3/
ADC1_DP1
P2
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
PGA3_DM/
ADC3_DM0/
ADC2_DM3/
ADC1_DM1
R1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
R2
PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
ALT7
EzPort
CMP3_OUT
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
78
Preliminary
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
T1
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
T2
PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
N5
VDDA
VDDA
VDDA
P4
VREFH
VREFH
VREFH
M4
VREFL
VREFL
VREFL
N4
VSSA
VSSA
VSSA
P3
ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22 ADC0_SE22 ADC0_SE22
N3
ADC0_SE16/ ADC0_SE16/ ADC0_SE16/
CMP1_IN2/ CMP1_IN2/ CMP1_IN2/
ADC0_SE21 ADC0_SE21 ADC0_SE21
T3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
R3
DAC0_OUT/ DAC0_OUT/ DAC0_OUT/
CMP1_IN3/ CMP1_IN3/ CMP1_IN3/
ADC0_SE23 ADC0_SE23 ADC0_SE23
R4
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP0_IN4/
CMP2_IN3/
ADC1_SE23
M5
TAMPER0/
RTC_WAKE
UP_B
TAMPER0/
RTC_WAKE
UP_B
TAMPER0/
RTC_WAKE
UP_B
L5
TAMPER1
TAMPER1
TAMPER1
L6
TAMPER2
TAMPER2
TAMPER2
R5
TAMPER3
TAMPER3
TAMPER3
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
P6
TAMPER4
TAMPER4
TAMPER4
R6
TAMPER5
TAMPER5
TAMPER5
T6
XTAL32
XTAL32
XTAL32
T5
EXTAL32
EXTAL32
EXTAL32
P5
VBAT
VBAT
VBAT
N6
TAMPER6
TAMPER6
TAMPER6
M6
TAMPER7
TAMPER7
TAMPER7
G9
VDD
VDD
VDD
H10 VDDINT
VDDINT
VDDINT
J8
VSS
VSS
VSS
P7
PTE24
ADC0_SE17/ ADC0_SE17/ PTE24
EXTAL1
EXTAL1
CAN1_TX
UART4_TX
I2S1_TX_FS
EWM_OUT_ I2S1_RXD1
b
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
79
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
I2S1_TX_BC
LK
ALT5
ALT6
ALT7
R7
PTE25
ADC0_SE18/ ADC0_SE18/ PTE25
XTAL1
XTAL1
CAN1_RX
UART4_RX
M7
PTE26
ADC3_SE5b ADC3_SE5b PTE26
ENET_1588
_CLKIN
UART4_CTS I2S1_TXD0
_b
K7
PTE27
ADC3_SE4b ADC3_SE4b PTE27
L7
PTE28
ADC3_SE7a ADC3_SE7a PTE28
T7
PTA0
JTAG_TCLK/ TSI0_CH1
SWD_CLK/
EZP_CLK
PTA0
UART0_CTS FTM0_CH5
_b/
UART0_COL
_b
JTAG_TCLK/ EZP_CLK
SWD_CLK
N8
PTA1
JTAG_TDI/
EZP_DI
TSI0_CH2
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
T8
PTA2
JTAG_TDO/
TRACE_SW
O/EZP_DO
TSI0_CH3
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/
TRACE_SW
O
EZP_DO
P8
PTA3
JTAG_TMS/
SWD_DIO
TSI0_CH4
PTA3
UART0_RTS FTM0_CH0
_b
JTAG_TMS/
SWD_DIO
R8
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5
PTA4/
LLWU_P3
T12 PTA5
DISABLED
PTA5
G10 VDD
VDD
VDD
J9
VSS
VSS
VSS
P9
PTF21
ADC3_SE6b ADC3_SE6b PTF21
N9
PTF22
ADC3_SE7b ADC3_SE7b PTF22
R12 PTA6
EWM_IN
I2S1_TXD1
RTC_CLKO
UT
USB_CLKIN
EzPort
UART4_RTS I2S1_MCLK
_b
FTM0_CH1
USB_CLKIN
NMI_b
FTM0_CH2
RMII0_RXE
R/
MII0_RXER
CMP2_OUT
FTM2_CH1
UART5_RTS
_b
I2C0_SCL
FTM1_CH0
UART5_CTS
_b
ADC3_SE6a ADC3_SE6a PTA6
ULPI_CLK
FTM0_CH3
I2S1_RXD0
TRACE_CLK
OUT
P12 PTA7
ADC0_SE10 ADC0_SE10 PTA7
ULPI_DIR
FTM0_CH4
I2S1_RX_BC
LK
TRACE_D3
N12 PTA8
ADC0_SE11 ADC0_SE11 PTA8
ULPI_NXT
FTM1_CH0
I2S1_RX_FS
FTM1_QD_P TRACE_D2
HA
T13 PTA9
ADC3_SE5a ADC3_SE5a PTA9
ULPI_STP
FTM1_CH1
MII0_RXD3
FTM1_QD_P TRACE_D1
HB
P13 PTA10
ADC3_SE4a ADC3_SE4a PTA10
ULPI_DATA
0
FTM2_CH0
MII0_RXD2
FTM2_QD_P TRACE_D0
HA
R13 PTA11
ADC3_SE15 ADC3_SE15 PTA11
ULPI_DATA
1
FTM2_CH1
MII0_RXCLK
FTM2_QD_P
HB
M10 PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
RMII0_RXD1
/MII0_RXD1
I2S0_TXD0
N10 PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
RMII0_RXD0
/MII0_RXD0
I2S0_TX_FS FTM1_QD_P
HB
R11 PTA14
CMP3_IN0
CMP3_IN0
PTA14
SPI0_PCS0
UART0_TX
RMII0_CRS_
DV/
MII0_RXDV
I2S0_RX_BC I2S0_TXD1
LK
EZP_CS_b
I2S0_TX_BC JTAG_TRST
LK
_b
FTM1_QD_P
HA
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
80
Preliminary
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
P11 PTA15
CMP3_IN1
CMP3_IN1
ALT1
ALT2
ALT3
ALT4
RMII0_TXEN
/MII0_TXEN
ALT5
ALT6
PTA15
SPI0_SCK
UART0_RX
PTA16
SPI0_SOUT
UART0_CTS RMII0_TXD0
_b/
/MII0_TXD0
UART0_COL
_b
I2S0_RX_FS I2S0_RXD1
T14 VSS
VSS
VSS
CMP3_IN2
CMP3_IN2
T11 PTA17
ADC1_SE17 ADC1_SE17 PTA17
SPI0_SIN
UART0_RTS RMII0_TXD1
_b
/MII0_TXD1
I2S0_MCLK
P10 PTF23
ADC3_SE10 ADC3_SE10 PTF23
I2C0_SDA
FTM1_CH1
TRACE_CLK
OUT
R10 PTF24
ADC3_SE11 ADC3_SE11 PTF24
CAN1_RX
FTM1_QD_P
HA
TRACE_D3
R9
PTF25
ADC3_SE12 ADC3_SE12 PTF25
CAN1_TX
FTM1_QD_P
HB
TRACE_D2
T9
PTF26
ADC3_SE13 ADC3_SE13 PTF26
FTM2_QD_P
HA
TRACE_D1
T10 PTF27
ADC3_SE14 ADC3_SE14 PTF27
FTM2_QD_P
HB
TRACE_D0
J7
VDD
VDD
VDD
K8
VSS
VSS
VSS
T15 PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN
0
T16 PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN
1
LPTMR0_AL
T1
R16 RESET_b
RESET_b
RESET_b
N13 PTA24
CMP3_IN4
CMP3_IN4
PTA24
ULPI_DATA
2
MII0_TXD2
FB_A29
R14 PTA25
CMP3_IN5
CMP3_IN5
PTA25
ULPI_DATA
3
MII0_TXCLK
FB_A28
M13 PTA26
ADC2_SE15 ADC2_SE15 PTA26
ULPI_DATA
4
MII0_TXD3
FB_A27
R15 PTA27
ADC2_SE14 ADC2_SE14 PTA27
ULPI_DATA
5
MII0_CRS
FB_A26
P14 PTA28
ADC2_SE13 ADC2_SE13 PTA28
ULPI_DATA
6
MII0_TXER
FB_A25
N14 PTA29
ADC2_SE12 ADC2_SE12 PTA29
ULPI_DATA
7
MII0_COL
FB_A24
P16 PTF0
ADC2_SE11 ADC2_SE11 PTF0
CAN0_TX
FTM3_CH0
I2S1_RXD1
L13 PTF1
ADC2_SE10 ADC2_SE10 PTF1
CAN0_RX
FTM3_CH1
I2S1_RX_BC
LK
M12 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
I2C0_SCL
FTM1_CH0
PTB0/
LLWU_P5
RMII0_MDIO
/MII0_MDIO
EzPort
I2S0_RXD0
N11 PTA16
ADC0_SE8/
ADC1_SE8/
ADC2_SE8/
ADC3_SE8/
TSI0_CH0
ALT7
FTM1_QD_P
HA
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
81
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
M11 PTB1
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
ADC2_SE9/
ADC3_SE9/
TSI0_CH6
PTB1
P15 PTB2
ALT2
ALT3
ALT4
ALT5
ALT6
I2C0_SDA
FTM1_CH1
RMII0_MDC/
MII0_MDC
FTM1_QD_P
HB
ADC0_SE12/ ADC0_SE12/ PTB2
TSI0_CH7
TSI0_CH7
I2C0_SCL
UART0_RTS ENET0_158
_b
8_TMR0
FTM0_FLT3
M14 PTB3
ADC0_SE13/ ADC0_SE13/ PTB3
TSI0_CH8
TSI0_CH8
I2C0_SDA
UART0_CTS ENET0_158
_b/
8_TMR1
UART0_COL
_b
FTM0_FLT0
N15 PTB4
ADC1_SE10 ADC1_SE10 PTB4
ENET0_158
8_TMR2
FTM1_FLT0
M15 PTB5
ADC1_SE11 ADC1_SE11 PTB5
ENET0_158
8_TMR3
FTM2_FLT0
L14 PTB6
ADC1_SE12 ADC1_SE12 PTB6
FB_AD23
L15 PTB7
ADC1_SE13 ADC1_SE13 PTB7
FB_AD22
K14 PTB8
DISABLED
PTB8
K15 PTB9
DISABLED
PTB9
J13
PTB10
J14
UART3_RTS
_b
FB_AD21
SPI1_PCS1
UART3_CTS
_b
FB_AD20
ADC1_SE14 ADC1_SE14 PTB10
SPI1_PCS0
UART3_RX
I2S1_TX_BC FB_AD19
LK
FTM0_FLT1
PTB11
ADC1_SE15 ADC1_SE15 PTB11
SPI1_SCK
UART3_TX
I2S1_TX_FS FB_AD18
FTM0_FLT2
K9
VSS
VSS
VSS
J10
VDD
VDD
VDD
N16 PTF2
ADC2_SE6a ADC2_SE6a PTF2
I2C1_SCL
FTM3_CH2
I2S1_RX_FS
M16 PTF3
ADC2_SE7a ADC2_SE7a PTF3
I2C1_SDA
FTM3_CH3
I2S1_RXD0
L16 PTF4
ADC2_SE4b ADC2_SE4b PTF4
FTM3_CH4
I2S1_TXD0
J15
TSI0_CH9
TSI0_CH9
PTB16
SPI1_SOUT
UART0_RX
I2S1_TXD0
FB_AD17
EWM_IN
H13 PTB17
TSI0_CH10
TSI0_CH10
PTB17
SPI1_SIN
UART0_TX
I2S1_TXD1
FB_AD16
EWM_OUT_
b
H14 PTB18
TSI0_CH11
TSI0_CH11
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_BC FB_AD15
LK
FTM2_QD_P
HA
K16 PTF5
ADC2_SE5b ADC2_SE5b PTF5
FTM3_CH5
I2S1_TX_FS
J16
ADC2_SE6b ADC2_SE6b PTF6
FTM3_CH6
I2S1_TX_BC
LK
PTB16
PTF6
H15 PTB19
TSI0_CH12
TSI0_CH12
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS FB_OE_b
G13 PTB20
ADC2_SE4a ADC2_SE4a PTB20
SPI2_PCS0
FB_AD31/
CMP0_OUT
NFC_DATA1
5
G14 PTB21
ADC2_SE5a ADC2_SE5a PTB21
SPI2_SCK
FB_AD30/
CMP1_OUT
NFC_DATA1
4
ALT7
EzPort
FTM2_QD_P
HB
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
82
Preliminary
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
G15 PTB22
DISABLED
PTB22
SPI2_SOUT
H16 PTB23
DISABLED
PTB23
SPI2_SIN
SPI0_PCS5
FB_AD28/
CMP3_OUT
NFC_DATA1
2
G16 PTC0
ADC0_SE14/ ADC0_SE14/ PTC0
TSI0_CH13 TSI0_CH13
SPI0_PCS4
PDB0_EXTR
G
FB_AD14/
I2S0_TXD1
NFC_DATA1
1
F13 PTC1/
LLWU_P6
ADC0_SE15/ ADC0_SE15/ PTC1/
TSI0_CH14 TSI0_CH14 LLWU_P6
SPI0_PCS3
UART1_RTS FTM0_CH0
_b
FB_AD13/
I2S0_TXD0
NFC_DATA1
0
F14 PTC2
ADC0_SE4b/ ADC0_SE4b/ PTC2
CMP1_IN0/ CMP1_IN0/
TSI0_CH15 TSI0_CH15
SPI0_PCS2
UART1_CTS FTM0_CH1
_b
FB_AD12/
I2S0_TX_FS
NFC_DATA9
E13 PTC3/
LLWU_P7
CMP1_IN1
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
F15 PTF7
ADC2_SE7b ADC2_SE7b PTF7
FTM3_CH7
UART3_RX
I2S1_TXD1
L9
VSS
VSS
VSS
K10 VDD
VDD
VDD
F16 PTF8
DISABLED
PTF8
FTM3_FLT0
UART3_TX
I2S1_MCLK
E14 PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
FB_AD11/
CMP1_OUT
NFC_DATA8
I2S1_TX_BC
LK
E15 PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_AL I2S0_RXD0
T2
FB_AD10/
CMP0_OUT
NFC_DATA7
I2S1_TX_FS
F12 PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_EXTR I2S0_RX_BC FB_AD9/
I2S0_MCLK
G
LK
NFC_DATA6
G12 PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS FB_AD8/
NFC_DATA5
H12 PTC8
ADC1_SE4b/ ADC1_SE4b/ PTC8
CMP0_IN2 CMP0_IN2
FTM3_CH4
I2S0_MCLK
F11 PTC9
ADC1_SE5b/ ADC1_SE5b/ PTC9
CMP0_IN3 CMP0_IN3
FTM3_CH5
I2S0_RX_BC FB_AD6/
FTM2_FLT0
LK
NFC_DATA3
G11 PTC10
ADC1_SE6b ADC1_SE6b PTC10
I2C1_SCL
FTM3_CH6
I2S0_RX_FS FB_AD5/
I2S1_MCLK
NFC_DATA2
H11 PTC11/
LLWU_P11
ADC1_SE7b ADC1_SE7b PTC11/
LLWU_P11
I2C1_SDA
FTM3_CH7
I2S0_RXD1
J12
PTC12
DISABLED
PTC12
UART4_RTS
_b
FB_AD27
K13 PTC13
DISABLED
PTC13
UART4_CTS
_b
FB_AD26
J11
DISABLED
PTC14
UART4_RX
FB_AD25
PTC14
CMP1_IN1
PTC3/
LLWU_P7
FB_AD29/
CMP2_OUT
NFC_DATA1
3
K12 PTF9
CMP2_IN4
CMP2_IN4
PTF9
UART3_RTS
_b
L12 PTF10
CMP2_IN5
CMP2_IN5
PTF10
UART3_CTS
_b
F10 PTC15
DISABLED
PTC15
EzPort
UART4_TX
I2S0_TX_BC
LK
FB_AD7/
NFC_DATA4
FB_RW_b/
NFC_WE
FTM3_FLT0
FB_AD24
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
83
Pinout
256
MAP
BGA
N7
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
VSS
VSS
VSS
L10 VDD
VDD
VDD
K11 PTF11
DISABLED
PTF11
UART2_RTS
_b
L11 PTF12
DISABLED
PTF12
UART2_CTS
_b
F9
PTC16
DISABLED
PTC16
CAN1_RX
UART3_RX
ENET0_158
8_TMR0
FB_CS5_b/ NFC_RB
FB_TSIZ1/
FB_BE23_16
_b
E9
PTC17
DISABLED
PTC17
CAN1_TX
UART3_TX
ENET0_158
8_TMR1
FB_CS4_b/ NFC_CE0_b
FB_TSIZ0/
FB_BE31_24
_b
M9
PTC18
DISABLED
PTC18
UART3_RTS ENET0_158
_b
8_TMR2
FB_TBST_b/ NFC_CE1_b
FB_CS2_b/
FB_BE15_8_
b
M8
PTC19
DISABLED
PTC19
UART3_CTS ENET0_158
_b
8_TMR3
FB_CS3_b/ FB_TA_b
FB_BE7_0_b
L8
PTD0/
LLWU_P12
DISABLED
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS FTM3_CH0
_b
FB_ALE/
FB_CS1_b/
FB_TS_b
I2S1_RXD1
F8
PTD1
ADC0_SE5b ADC0_SE5b PTD1
SPI0_SCK
UART2_CTS FTM3_CH1
_b
FB_CS0_b
I2S1_RXD0
K6
PTD2/
LLWU_P13
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
FTM3_CH2
FB_AD4
I2S1_RX_FS
J6
PTD3
DISABLED
PTD3
SPI0_SIN
UART2_TX
FTM3_CH3
FB_AD3
I2S1_RX_BC
LK
K5
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS FTM0_CH4
_b
FB_AD2/
EWM_IN
NFC_DATA1
J5
PTD5
ADC0_SE6b ADC0_SE6b PTD5
SPI0_PCS2
UART0_CTS FTM0_CH5
_b/
UART0_COL
_b
FB_AD1/
EWM_OUT_
NFC_DATA0 b
K4
PTD6/
LLWU_P15
ADC0_SE7b ADC0_SE7b PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FB_AD0
FTM0_CH6
ALT7
EzPort
FTM0_FLT0
H6
PTF13
DISABLED
PTF13
UART2_RX
G6
PTF14
DISABLED
PTF14
UART2_TX
T4
VSS
VSS
E7
PTD7
DISABLED
PTD7
CMT_IRO
UART0_TX
J4
PTD8
DISABLED
PTD8
I2C0_SCL
UART5_RX
FB_A16/
NFC_CLE
F7
PTD9
DISABLED
PTD9
I2C0_SDA
UART5_TX
FB_A17/
NFC_ALE
E6
PTD10
DISABLED
PTD10
UART5_RTS
_b
FB_A18/
NFC_RE
VSS
FTM0_CH7
FTM0_FLT1
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
84
Preliminary
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
G5
PTD11
DISABLED
PTD11
SPI2_PCS0
UART5_CTS SDHC0_CLK
_b
IN
FB_A19
F5
PTD12
DISABLED
PTD12
SPI2_SCK
FTM3_FLT0
SDHC0_D4
FB_A20
F4
PTD13
DISABLED
PTD13
SPI2_SOUT
SDHC0_D5
FB_A21
E5
PTD14
DISABLED
PTD14
SPI2_SIN
SDHC0_D6
FB_A22
E4
PTD15
DISABLED
PTD15
SPI2_PCS1
SDHC0_D7
FB_A23
F6
PTF15
DISABLED
PTF15
E1
PTF16
DISABLED
PTF16
B1
DDR_VDD
DDR_VDD
DDR_VDD
A1
DDR_VSS
DDR_VSS
DDR_VSS
D3
DDR_DQS1
DISABLED
DDR_DQS1
D1
DDR_DQ8
DISABLED
DDR_DQ8
C1
DDR_DQ9
DISABLED
DDR_DQ9
B5
DDR_VDD
DDR_VDD
DDR_VDD
A5
DDR_VSS
DDR_VSS
DDR_VSS
D5
DDR_VSS
DDR_VSS
DDR_VSS
C2
DDR_DQ10
DISABLED
DDR_DQ10
B2
DDR_DQ11
DISABLED
DDR_DQ11
C3
DDR_DQ12
DISABLED
DDR_DQ12
B8
DDR_VDD
DDR_VDD
DDR_VDD
A12 DDR_VSS
DDR_VSS
DDR_VSS
C4
DDR_DQ13
DISABLED
DDR_DQ13
B3
DDR_DQ14
DISABLED
DDR_DQ14
A2
DDR_DQ15
DISABLED
DDR_DQ15
A3
DDR_DM1
DISABLED
DDR_DM1
E8
DDR_VSS
DDR_VSS
DDR_VSS
B12 DDR_VDD
DDR_VDD
DDR_VDD
A16 DDR_VSS
DDR_VSS
DDR_VSS
C6
DDR_VREF
DDR_VREF
DDR_VREF
C5
DDR_DQ0
DISABLED
DDR_DQ0
B4
DDR_DQ1
DISABLED
DDR_DQ1
A4
DDR_DQ2
DISABLED
DDR_DQ2
C16 DDR_VDD
DDR_VDD
DDR_VDD
C7
DDR_VSS
DDR_VSS
DDR_VSS
B6
DDR_DQ3
DISABLED
DDR_DQ3
D6
DDR_DQ4
DISABLED
DDR_DQ4
A6
DDR_DQ5
DISABLED
DDR_DQ5
A7
DDR_ODT
DISABLED
DDR_ODT
ALT7
EzPort
UART0_RTS
_b
SPI2_PCS0
FTM0_CH3
UART0_CTS
_b/
UART0_COL
_b
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
85
Pinout
256
MAP
BGA
Pin Name
Default
ALT0
ALT1
E11 DDR_VSS
DDR_VSS
DDR_VSS
D2
DDR_VDD
DDR_VDD
DDR_VDD
C9
DDR_VSS
DDR_VSS
DDR_VSS
B7
DDR_DQ6
DISABLED
DDR_DQ6
A8
DDR_DQ7
DISABLED
DDR_DQ7
C8
DDR_DQS0
DISABLED
DDR_DQS0
D9
DDR_DM0
DISABLED
DDR_DM0
D4
DDR_VDD
DDR_VDD
DDR_VDD
C14 DDR_VSS
DDR_VSS
DDR_VSS
A9
DDR_BA0
DISABLED
DDR_BA0
B10 DDR_BA1
DISABLED
DDR_BA1
B9
DDR_BA2
DISABLED
DDR_BA2
A10 DDR_CKB
DISABLED
DDR_CKB
A11 DDR_CK
DISABLED
DDR_CK
D7
DDR_VDD
DDR_VDD
DDR_VDD
D8
DDR_VSS
DDR_VSS
DDR_VSS
D10 DDR_A0
DISABLED
DDR_A0
C11 DDR_A1
DISABLED
DDR_A1
B11 DDR_A2
DISABLED
DDR_A2
C12 DDR_A3
DISABLED
DDR_A3
E10 DDR_VDD
DDR_VDD
DDR_VDD
D12 DDR_VSS
DDR_VSS
DDR_VSS
C10 DDR_A4
DISABLED
DDR_A4
A13 DDR_A5
DISABLED
DDR_A5
A14 DDR_A6
DISABLED
DDR_A6
D11 DDR_A7
DISABLED
DDR_A7
A15 DDR_A8
DISABLED
DDR_A8
E12 DDR_VDD
DDR_VDD
DDR_VDD
E3
DDR_VSS
DDR_VSS
DDR_VSS
B16 DDR_CKE
DISABLED
DDR_CKE
B15 DDR_A9
DISABLED
DDR_A9
B13 DDR_A10
DISABLED
DDR_A10
B14 DDR_A11
DISABLED
DDR_A11
C15 DDR_A12
DISABLED
DDR_A12
D16 DDR_A13
DISABLED
DDR_A13
D15 DDR_A14
DISABLED
DDR_A14
E16 DDR_RAS_
B
DISABLED
DDR_RAS_
B
C13 DDR_CAS_
B
DISABLED
DDR_CAS_
B
D14 DDR_CS_B
DISABLED
DDR_CS_B
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
86
Preliminary
Freescale Semiconductor, Inc.
Pinout
256
MAP
BGA
Pin Name
Default
D13 DDR_WE_B
DISABLED
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
DDR_WE_B
8.2 K61 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
87
Revision History
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
DDR_VSS DDR_DQ15 DDR_DM1 DDR_DQ2 DDR_VSS DDR_DQ5 DDR_ODT DDR_DQ7
DDR_BA0
DDR_CKB
DDR_CK
DDR_VSS
DDR_A5
DDR_A6
DDR_A8
DDR_VSS
A
B
DDR_VDD DDR_DQ11 DDR_DQ14 DDR_DQ1 DDR_VDD DDR_DQ3 DDR_DQ6 DDR_VDD DDR_BA2
DDR_BA1
DDR_A2
DDR_VDD
DDR_A10
DDR_A11
DDR_A9
DDR_CKE
B
C
DDR_DQ9 DDR_DQ10 DDR_DQ12 DDR_DQ13 DDR_DQ0 DDR_VREF DDR_VSS DDR_DQS0 DDR_VSS
DDR_A4
DDR_A1
DDR_A3
DDR_
CAS_B
DDR_VSS
DDR_A12
DDR_VDD
C
D
DDR_DQ8 DDR_VDD DDR_DQS1 DDR_VDD DDR_VSS DDR_DQ4 DDR_VDD DDR_VSS DDR_DM0
DDR_A0
DDR_A7
DDR_VSS DDR_WE_B DDR_CS_B DDR_A14
DDR_A13
D
PTC4/
LLWU_P8
PTC5/
LLWU_P9
DDR_
RAS_B
E
PTC2
PTF7
PTF8
F
PTB20
PTB21
PTB22
PTC0
G
PTC8
PTB17
PTB18
PTB19
PTB23
H
PTC14
PTC12
PTB10
PTB11
PTB16
PTF6
J
VDD
PTF11
PTF9
PTC13
PTB8
PTB9
PTF5
K
VSS
VDD
PTF12
PTF10
PTF1
PTB6
PTB7
PTF4
L
PTC19
PTC18
PTA12
PTB1
PTB0/
LLWU_P5
PTA26
PTB3
PTB5
PTF3
M
E
PTF16
PTE0
DDR_VSS
PTD15
PTD14
PTD10
PTD7
DDR_VSS
PTC17
F
PTF17
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTD13
PTD12
PTF15
PTD9
PTD1
PTC16
PTC15
PTC9
G
PTF18
PTE3
PTE4/
LLWU_P2
PTE5
PTD11
PTF14
VDD
VDD
VDD
VDD
PTC10
PTC7
H
PTF19
PTE6
PTE7
PTE8
PTF20
PTF13
VDDINT
VSS
VSS
VDDINT
PTC11/
LLWU_P11
J
PTE9
PTE10
PTE16
PTD8
PTD5
PTD3
VDD
VSS
VSS
VDD
K
PTE11
PTE17
PTE12
PTE27
VSS
VSS
L
VOUT33
VSS
VREGIN
PTE18
TAMPER1 TAMPER2
PTE28
PTD0/
LLWU_P12
M
USB0_DP
USB0_DM
PTE19
VREFL
TAMPER0/
TAMPER7
RTC_
WAKEUP_B
PTE26
PTD6/
PTD4/
PTD2/
LLWU_P15 LLWU_P14 LLWU_P13
DDR_VDD DDR_VSS DDR_VDD
PTC3/
LLWU_P7
PTC6/
PTC1/
LLWU_P10 LLWU_P6
N
PGA2_DP/ PGA2_DM/
ADC0_SE16/
ADC2_DP0/ ADC2_DM0/
CMP1_IN2/
ADC3_DP3/ ADC3_DM3/
ADC0_SE21
ADC0_DP1 ADC0_DM1
VSSA
VDDA
TAMPER6
VSS
PTA1
PTF22
PTA13/
LLWU_P4
PTA16
PTA8
PTA24
PTA29
PTB4
PTF2
N
P
PGA3_DP/ PGA3_DM/
ADC1_SE16/
ADC3_DP0/ ADC3_DM0/
CMP2_IN2/
ADC2_DP3/ ADC2_DM3/
ADC0_SE22
ADC1_DP1 ADC1_DM1
VREFH
VBAT
TAMPER4
PTE24
PTA3
PTF21
PTF23
PTA15
PTA7
PTA10
PTA28
PTB2
PTF0
P
R
DAC1_OUT/
PGA0_DP/ PGA0_DM/ DAC0_OUT/
CMP0_IN4/
ADC0_DP0/ ADC0_DM0/ CMP1_IN3/
TAMPER3 TAMPER5
CMP2_IN3/
ADC1_DP3 ADC1_DM3 ADC0_SE23
ADC1_SE23
PTE25
PTA4/
LLWU_P3
PTF25
PTF24
PTA14
PTA6
PTA11
PTA25
PTA27
RESET_b
R
T
VREF_OUT/
PGA1_DP/ PGA1_DM/
CMP1_IN5/
ADC1_DP0/ ADC1_DM0/
CMP0_IN5/
ADC0_DP3 ADC0_DM3
ADC1_SE18
T
1
2
3
VSS
EXTAL32
XTAL32
PTA0
PTA2
PTF26
PTF27
PTA17
PTA5
PTA9
VSS
PTA18
PTA19
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 38. K61 256 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
88
Preliminary
Freescale Semiconductor, Inc.
Revision History
Table 53. Revision History
Rev. No.
Date
1
6/2011
2
11/2011
Substantial Changes
Initial public revision. Corrected USB conditions.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Added AC electrical specifications.
Updated Part identification section for 120 MHz CPU frequency.
Updated Voltage and current operating ratings section.
Updated Voltage and current operating requirements section.
Updated LVD and POR operating requirements section.
Updated Voltage and current operating behaviors section.
Updated Power mode transition operating behaviors section.
Updated Power consumption operating behaviors section.
In Run mode supply current vs. core frequency section, added Run and VLPR modes
supply current vs. core frequency diagrams.
In Device clock specifications section, updated flash clock frequency and DDR clock
frequency.
Updated Thermal attributes.
In MCG specifications section, updated total deviation of trimmed average DCO output
Frequency, PLL reference frequency range, and lock detector detection time.
In Oscillator frequency specifications section, updated crystal startup time — 32 kHz.
Updated NFC specifications section.
Updated DDR controller specifications section.
In DryIce Tamper Electrical Specifications section, updated supply current.
In DSPI switching specifications section, updated master and slave modes frequency
of operation for limited voltage and full voltage ranges.
In I2S/SAI Switching Specifications section, updated cycle time for master and slave
modes.
In USB DCD electrical specifications section, updated data detect voltage.
In TSI electrical specifications, updated reference oscillator frequency.
Updated Pinouts.
Updated Pinouts.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
89
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Rev. 3, 2/2012
Preliminary
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