ISL84051, ISL84052, ISL84053 ® Data Sheet October 2, 2007 FN6047.8 Low Voltage, Single and Dual Supply, 8 to 1 Multiplexer, Dual 4 to 1 Multiplexer and a Triple SPDT Analog Switch Features The Intersil ISL84051, ISL84052, ISL84053 devices are precision, bidirectional, analog switches configured as a 8-Channel multiplexer/demultiplexer (ISL84051), a dual differential 4-Channel multiplexer/demultiplexer (ISL84052) and a triple single pole/double throw (SPDT) switch (ISL84053) designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. All devices have an inhibit pin to simultaneously open all signal paths. • Pin Compatible with MAX4581, MAX4582, MAX4583 and with Industry Standard 74HC4051, 74HC4052 and 74HC4053 • Drop-in Replacements for MAX4051/MAX4051A, MAX4052/MAX4052A and MAX4053/MAX4053A • ON-Resistance (rON) Max, VS = ±5V. . . . . . . . . . . . 100Ω • ON-Resistance (rON) Max, VS = +3V. . . . . . . . . . . . 525Ω • rON Matching Between Channels . . . . . . . . . . . . . . . . . . <6Ω • Low Charge Injection . . . . . . . . . . . . . . . . . . . . . 10pC (Max) ON-resistance is 60Ω with a ±5V supply and 125Ω with a single +5V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25°C or 5nA at +85°C with a ±5V supply. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single +3.3V and +5V supply or dual ±5V supplies. The ISL84051 is a 8-to-1 multiplexer device. The ISL84052 is a dual 4-to-1 multiplexer device. The ISL84053 is a committed triple SPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this family. ISL84051 ISL84052 ISL84053 8:1 Mux DUAL 4:1 Mux TRIPLE SPDT 60Ω 60Ω 60Ω 50ns/40ns 50ns/40ns 50ns/40ns 125Ω 125Ω 125Ω 90ns/60ns 90ns/60ns 90ns/60ns 250Ω 250Ω 250Ω 3V tON/tOFF 180ns/100ns 180ns/100ns 180ns/100ns Packages 16 Ld SOIC 16 Ld SOIC 16 Ld SOIC 16 Ld QSOP 16 Ld QSOP 16 Ld QSOP 16 Ld TSSOP 16 Ld TSSOP ±5V rON ±5V tON/tOFF 5V rON 5V tON/tOFF 3V rON Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” 1 • Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . . ±2V to ±6 • Fast Switching Action (VS = +5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns • Guaranteed Max Off-leakage @ VS = ±5V. . . . . . . . . . 5nA • Guaranteed Break-Before-Make • TTL, CMOS Compatible • Pb-Free Available (RoHS Compliant) Applications TABLE 1. FEATURES AT A GLANCE CONFIGURATION • Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V • Portable Equipment • Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems • Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph • Audio and Video Signal Routing • Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003-2004, 2006-2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL84051, ISL84052, ISL84053 Pinouts ISL84052 (16 LD SOIC, QSOP, TSSOP) TOP VIEW ISL84051 (16 LD SOIC, QSOP, TSSOP) TOP VIEW NO1 1 16 V+ NO0B 1 16 V+ NO3 2 15 NO2 NO1B 2 15 NO1A COM 3 14 NO4 COMB 3 14 NO2A NO7 4 13 NO0 NO3B 4 13 COMA NO5 5 12 NO6 NO2B 5 12 NO0A 11 NO3A 11 ADDC INH 6 V- 7 10 ADDB V- 7 GND 8 9 ADDA GND 8 INH 6 LOGIC LOGIC 10 ADDB 9 ADDA ISL84053 (16 LD SOIC, QSOP) TOP VIEW NOB 1 16 V+ NCB 2 15 COMB NOA 3 14 COMC COMA 4 13 NOC NCA 5 12 NCC INH 6 11 ADDC V- 7 10 ADDB GND 8 9 ADDA NOTE: 1. Switches Shown for Logic “0” Inputs. 2 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Ordering Information PART NUMBER ISL84051IB* PART MARKING 84051IB Truth Tables TEMP. RANGE (°C) ISL84051 PACKAGE PKG. DWG. # -40 to +85 16 Ld SOIC M16.15 ISL84051IBZ* 84051IBZ (Note) -40 to +85 16 Ld SOIC (Pb-free) M16.15 ISL84051IA* -40 to +85 16 Ld QSOP M16.15A ISL84051IAZ* 84051 IAZ (Note) -40 to +85 16 Ld QSOP (Pb-free) M16.15A ISL84051IVZ* 84051 IVZ (Note) -40 to +85 16 Ld TSSOP M16.173 (Pb-free) ISL84052IB* -40 to +85 16 Ld SOIC M16.15 ISL84052IBZ* 84052IBZ (Note) -40 to +85 16 Ld SOIC (Pb-free) M16.15 ISL84052IA* -40 to +85 16 Ld QSOP M16.15A ISL84052IAZ* 84052 IAZ (Note) -40 to +85 16 Ld QSOP (Pb-free) M16.15A ISL84052IVZ* 84052 IVZ (Note) -40 to +85 16 Ld TSSOP M16.173 (Pb-free) ISL84053IB* -40 to +85 16 Ld SOIC M16.15 ISL84053IBZ* 84053IBZ (Note) -40 to +85 16 Ld SOIC (Pb-free) M16.15 ISL84053IA* -40 to +85 16 Ld QSOP -40 to +85 16 Ld QSOP (Pb-free) 84051 IA 84052IB 84052 IA 84053IB 84053 IA ISL84053IAZ* 84053 IAZ (Note) ADDA SWITCH ON 1 X X X None 0 0 0 0 NO0 0 0 0 1 NO1 0 0 1 0 NO2 0 0 1 1 NO3 0 1 0 0 NO4 0 1 0 1 NO5 0 1 1 0 NO6 0 1 1 1 NO7 ISL84052 ADDA SWITCH ON 1 X X None 0 0 0 NO0 M16.15A 0 0 1 NO1 M16.15A 0 1 0 NO2 0 1 1 NO3 FUNCTION V+ Positive Power Supply Input V- Negative Power Supply Input. Connect to GND for Single Supply Configurations. GND Ground Connection INH Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. ISL84053 INH ADDC ADDB ADDA SWITCH ON 1 X X X None 0 X X 0 NCA 0 X X 1 NOA 0 X 0 X NCB 0 X 1 X NOB 0 0 X X NCC 0 1 X X NOC NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and 10V. X = Don’t Care. Analog Switch Common Pin NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin ADD ADDB ADDB Pin Description COM ADDC INH *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PIN INH Address Input Pin 3 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 0.3V Input Voltages INH, NO, NC, ADD (Note 2) . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±100mA ESD Rating HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >2kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 160 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Package). . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range ISL8405x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEMP (°C) MIN (Notes 5, 6) TYP Full V- - V+ V VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V (see Figure 5) +25 - 60 100 Ω Full - - 125 Ω rON Matching Between Channels, ΔrON VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V (Note 7) +25 - - 6 Ω Full - - 12 Ω rON Flatness, rFLAT(ON) VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V, 0V (Note 8) +25 - - 10 Ω Full - - 15 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = ±4.5V (Note 9) +25 -0.1 0.002 0.1 nA Full -5 - 5 nA COM OFF Leakage Current, ICOM(OFF), (ISL84051) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = ±4.5V (Note 9) +25 -0.1 0.002 0.1 nA Full -5 - 5 nA COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = ±4.5V (Note 9) +25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA COM ON Leakage Current, ICOM(ON), (ISL84051) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V (Note 9) +25 -0.1 0.002 0.1 nA Full -5 - 5 nA COM ON Leakage Current, ICOM(ON), (ISL84052, ISL84053) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V (Note 9) +25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VINH, VADDH Full 2.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.8 V Full -1 0.03 1 µA PARAMETER TEST CONDITIONS MAX (Notes 5, 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL VS = ±5.5V, VINH, VADD = 0V or V+ 4 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Electrical Specifications - 5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEMP (°C) MIN (Notes 5, 6) TYP VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 1) +25 - 50 175 ns Full - - 225 ns VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 1) +25 - 40 150 ns Full - - 200 ns Address Transition Time, tTRANS VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 1) +25 - 75 250 ns Break-Before-Make Time, tBBM VS = ±5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 3) +25 2 10 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) +25 - 2 10 pC NO/NC OFF-Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) +25 - 3 - pF COM OFF-Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) ISL84051 +25 - 21 - pF ISL84052 +25 - 12 - pF ISL84053 +25 - 9 - pF ISL84051 +25 - 26 - pF ISL84052 +25 - 18 - pF ISL84053 +25 - 14 - pF +25 - <90 - dB +25 - < -90 - dB Full ±2 - ±6 V +25 -1 0.1 1 µA Full -10 - 10 µA 25 -1 0.1 1 µA Full -10 - 10 µA PARAMETER TEST CONDITIONS MAX (Notes 5, 6) UNITS DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF COM ON-Capacitance, CCOM(ON) OFF Isolation f = 1MHz, VNO or VNC = VCOM = 0V (see Figure 7) RL = 50Ω, CL = 15pF, f = 100kHz VNO or VNC = 1VRMS (see Figures 4 and 6) Crosstalk, (ISL84052, ISL84053 Only) POWER SUPPLY CHARACTERISTICS Power Supply Range VS = ±5.5V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, I- Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNIT S Full 0 - V+ V V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V (see Figure 5) +25 - 125 225 Ω Full - - 280 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V (Note 9) +25 -1 0.002 1 nA Full -10 - 10 nA COM OFF Leakage Current, ICOM(OFF), (ISL84051) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V (Note 9) +25 -1 0.002 1 nA Full -10 - 10 nA COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V (Note 9) +25 -1 0.002 1 nA Full -5 - 5 nA PARAMETER TEST CONDITIONS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON-Resistance, rON 5 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. (Continued) TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNIT S +25 -1 0.002 1 nA Full -10 - 10 nA Input Voltage High, VINH, VADDH Full 2.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.8 V V+ = 5.5V, VINH, VADD = 0V or V+ Full -1 0.03 1 µA V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V (see Figure 1) +25 - 90 200 ns Full - - 275 ns V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 1) +25 - 60 125 ns Full - - 175 ns Break-Before-Make Time, tBBM V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 3) +25 - 30 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) +25 - 2 10 pC OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz VNO or VNC = 1VRMS (see Figures 4 and 6) +25 - <90 - dB +25 - <-90 - dB Full 2 - 12 V +25 -1 - 1 µA Full -10 - 10 µA PARAMETER TEST CONDITIONS COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = VNO or VNC = 4.5V (Note 9) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Crosstalk, (Note 10) (ISL84052, ISL840533 Only) POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Electrical Specifications: 3.3V Supply PARAMETER Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. TEST CONDITIONS TEMP (°C) MIN (Notes 5, 6) TYP MAX (Notes 5, 6) UNITS Full 0 - V+ V +25 - 250 525 Ω Full - - 700 Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V ON-Resistance, rON NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V (Note 9) +25 -1 0.002 1 nA Full -10 - 10 nA COM OFF Leakage Current, ICOM(OFF), (ISL84051) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V (Note 9) +25 -1 0.002 1 nA Full -10 - 10 nA COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V (Note 9) +25 -1 0.002 1 nA Full -5 - 5 nA COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = VNO or VNC = 3V (Note 9) +25 -1 0.002 1 nA Full -10 - 10 nA 6 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Electrical Specifications: 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified. (Continued) TEMP (°C) MIN (Notes 5, 6) TYP Input Voltage High, VINH, VADDH Full 2.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.8 V V+ = 3.6V, VINH, VADD = 0V or V+ Full -1 0.03 1 µA V+ = 3V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 1) +25 - 180 600 ns Full - - 700 ns V+ = 3V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 1) +25 - 100 300 ns Full - - 400 ns Break-Before-Make Time, tBBM V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0V to 3V (see Figure 3) +25 - 90 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2) +25 - 1 10 pC OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz VNO or VNC = 1VRMS, (see Figures 4 and 6) +25 - <90 - dB +25 - <-90 - dB Full 2 - 12 V +25 -1 - 1 µA Full -10 - 10 µA PARAMETER TEST CONDITIONS MAX (Notes 5, 6) UNITS DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF Crosstalk, (Note 10) (ISL84052, ISL84053 Only) POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 3.6V, V- = 0V, VINH, VADD = 0V or V+ Switch On or Off Positive Supply Current, I+ NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested. 7. ΔrON = rON (MAX) - rON (MIN). 8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 9. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C. 10. Between any two switches. 7 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms C V+ V+ V- C NO0 C ISL84051 NO1-NO7 VOUT COM INH GND ADDA-C LOGIC INPUT C 3V LOGIC INPUT V+ V- C RL 300Ω CL 35pF C tr < 20ns tf < 20ns 50% V+ NO0 ISL84052 0V NO1-NO3 tON VOUT COM INH 90% SWITCH OUTPUT VOUT 90% GND ADDA-B LOGIC INPUT RL 300Ω CL 35pF 0V tOFF Logic input waveform is inverted for switches that have the opposite logic sense. V+ C V+ NCX NOX C V- C ISL84053 COMX VOUT INH GND ADDX LOGIC INPUT RL 300Ω CL 35pF Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------R L + r ON FIGURE 1A. INHIBIT tON /tOFF MEASUREMENT POINTS FIGURE 1B. INHIBIT tON /tOFF TEST CIRCUIT FIGURE 1. SWITCHING TIMES 8 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms (Continued) C V+ V- V+ V- C NO0 ISL84051 NO7 C C VOUT COM NO1-NO6 ADDA-C GND INH RL 300Ω LOGIC INPUT C 3V LOGIC INPUT 50% V+ tTRANS V- VOUT NO0 C ISL84052 NO3 C SWITCH OUTPUT V- C tr < 20ns tf < 20ns 0V VNOX V+ CL 35pF ADDA-B GND 90% VOUT COM NO1-NO2 INH RL 300Ω LOGIC INPUT 0V CL 35pF 10% VNOX V+ C tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. V+ V- NCX V- C ISL84053 NOX COMX C ADDX LOGIC INPUT C GND VOUT INH RL 300Ω CL 35pF Repeat test for other switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (NO or NC) R + r L ON FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT FIGURE 1. SWITCHING TIMES (Continued) 9 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms (Continued) V+ V- C C 3V VOUT RG OFF OFF LOGIC INPUT ON COM NO or NC 0V 0Ω ADDX SWITCH OUTPUT VOUT VG ΔVOUT GND INH LOGIC INPUT CL 1nF Q = ΔVOUT x CL Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ C V- C VOUT NO0-NO7 V+ C COM CL 35pF RL 300Ω ADDA-C ISL84051 LOGIC INPUT GND tr < 20ns tf < 20ns 3V V+ C LOGIC INPUT INH V- C C 0V COM CL 35pF RL 300Ω ADDA-B 80% SWITCH OUTPUT VOUT VOUT NO0-NO3 V+ ISL84052 LOGIC INPUT 0V tBBM GND V+ C V- C NCX C VOUT NOX V+ INH COMX ISL84053 CL 35pF RL 300Ω ADDX GND LOGIC INPUT INH Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 10 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms V+ (Continued) V- C V+ V- C C C rON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX 1mA 0V OR V+ ADDX 0V OR V+ ANALYZER COM GND 0V OR V+ V1 ADDX COM INH GND INH RL FIGURE 5. rON TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT V+ SIGNAL GENERATOR V- C V+ C 50Ω COMA ISL84052 AND ISL84053 0V OR V+ NOB or NCB COMB ADDX IMPEDANCE ANALYZER 0V OR V+ ANALYZER GND C NO OR NC NOA or NCA ADDX V- C NC COM GND INH INH RL FIGURE 6. CROSSTALK TEST CIRCUIT 11 FIGURE 7. CAPACITANCE TEST CIRCUIT FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Detailed Description Power-Supply Considerations The ISL84051, ISL84052, ISL84053 analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (60Ω) and high speed operation (tON = 50ns, tOFF = 40ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (3μW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. The ISL8405x construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL8405x 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (see Figure 8). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS OPTIONAL PROTECTION DIODE V+ 1kΩ LOGIC VNO OR NC VCOM VOPTIONAL PROTECTION DIODE FIGURE 8. INPUT OVERVOLTAGE PROTECTION 12 This family of switches performs equally well when operated with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and ON-resistance degrade at lower supply voltages. Refer to the “Electrical Specification” tables beginning on page 4 and “Typical Performance Curves” beginning on page 13 for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. Logic-Level Thresholds V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH level is about 3.5V. This is still below the CMOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 100MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off isolation is the resistance to this feed through, while crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high off isolation and crosstalk rejection provided by this family. At 10MHz, off isolation is about 55dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. Typical Performance Curves TA = +25°C, Unless Otherwise Specified 225 200 70 VCOM = (V+) - 1V ICOM = 1mA V- = -5V 60 175 150 +85°C 40 +25°C 30 -40°C 20 400 V- = 0V 300 200 +85°C +25°C 100 -40°C 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 50 V+ = 2.7V V- = 0V 75 160 140 120 100 80 60 100 90 +85°C 80 70 +25°C 60 50 40 1 0 +85°C V+ = 5V +25°C V+ = 3.3V -40°C V- = 0V V- = 0V -40°C 3 2 4 5 FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE ICOM = 1mA 2 VS = ±2V +85°C +25°C 1 -40°C 0 VS = ±3V +85°C Q (pC) rON (Ω) +25°C -40°C VCOM (V) FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE 120 110 100 90 80 70 60 50 90 80 70 60 50 40 30 60 +85°C 125 100 rON (Ω) rON (Ω) 50 ICOM = 1mA +25°C V+ = 5V V- = 0V -1 -40°C VS = ±5V VS = ±5V +85°C +25°C -2 40 30 -3 -40°C -5 20 -5 -4 -3 -2 -1 0 1 2 3 4 VCOM (V) FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE 13 5 -2.5 0 VCOM (V) 5 2.5 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) 500 +25°C +25°C 100 +25°C 200 +25°C 100 50 +85°C tOFF (ns) +85°C -40°C 0 250 V- = 0V 200 +85°C 150 50 0 100 V- = 0V 80 +85°C +25°C 40 20 -40°C 0 0 2 -40°C 60 +25°C 100 3 4 5 6 7 8 9 10 11 12 -40°C 2 3 4 6 5 8 7 10 9 11 12 V+ (V) V+ (V) FIGURE 13. INHIBIT TURN-ON TIME vs SUPPLY VOLTAGE 300 FIGURE 14. INHIBIT TURN-OFF TIME vs SUPPLY VOLTAGE 250 VCOM = (V+) - 1V VCOM = (V+) - 1V V- = 0V 250 200 tRANS (ns) 200 tRANS (ns) VCOM = (V+) - 1V V- = -5V -40°C 150 -40°C 300 tON (ns) 200 VCOM = (V+) - 1V V- = -5V 400 150 150 100 +25°C 100 +25°C +85°C 50 +85°C 50 -40°C -40°C 0 0 3 4 5 6 7 8 9 10 11 2 13 12 3 4 V+ (V) 6 FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE -10 VS = ±5V 3 ISL84053 GAIN 0 -3 ISL84052 ISL84053 ISL84051 ISL84052 0 45 90 135 180 RL = 50Ω 10M 100M FREQUENCY (Hz) FIGURE 17. FREQUENCY RESPONSE 14 600M CROSSTALK (dB) ISL84051 PHASE 10 V+ = 3V TO 12V or -20 VS = ±2V TO ±5V RL = 50Ω -30 VIN = 0.2VP-P TO 5VP-P PHASE (°) NORMALIZED GAIN (dB) FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE 1M 5 V± (V) 20 30 -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 OFF ISOLATION (dB) 2 CROSSTALK -90 90 -100 100 -110 1k 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 18. CROSSTALK AND OFF ISOLATION FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: ISL84051: 193 ISL84052: 193 ISL84053: 193 PROCESS: Si Gate CMOS 15 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M INCHES E -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC - 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 α 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 1.27 BSC H N NOTES: MILLIMETERS 16 0° 16 8° 0° 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 16 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M 2 INCHES E1 GAUGE PLANE -B1 B M L 0.05(0.002) -A- SYMBOL MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - A1 3 A D -C- e α c 0.10(0.004) C A M 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - B S 0.002 D 0.193 0.201 4.90 5.10 3 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 N α NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 0.006 E1 e A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 0.70 6 16 8o 0o - 6.50 7 8o Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 17 FN6047.8 October 2, 2007 ISL84051, ISL84052, ISL84053 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP) M16.15A N INDEX AREA H 0.25(0.010) M 16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150” WIDE BODY) B M E -B1 2 INCHES GAUGE PLANE 3 0.25 0.010 SEATING PLANE -A- A D h x 45° -C- e α A2 A1 B 0.17(0.007) M L C 0.10(0.004) C A M B S NOTES: SYMBOL MIN MAX MIN MAX NOTES A 0.061 0.068 1.55 1.73 - A1 0.004 0.0098 0.102 0.249 - A2 0.055 0.061 1.40 1.55 - B 0.008 0.012 0.20 0.31 9 C 0.0075 0.0098 0.191 0.249 - D 0.189 0.196 4.80 4.98 3 E 0.150 0.157 3.81 3.99 4 e 0.025 BSC 0.635 BSC - H 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 L 0.016 0.035 0.41 0.89 6 8° 0° N 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS α 16 0° 16 7 8° 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 2 6/04 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN6047.8 October 2, 2007