ALSC ASM161JEUS/T Up supervisory circuit Datasheet

ASM161 / ASM162
October 2003
rev 1.0
µP Supervisory Circuit
General Description
Key Features
The ASM161 and ASM162 are cost effective, low power
•
•
•
•
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supervisory
circuits
that
monitor
power
supplies
in
microprocessor, microcontroller and digital systems. If the
power supply drops below the reset threshold level, a reset is
asserted and remains asserted for atleast 800ms after VCC has
risen above the reset threshold. An improved manual reset
architecture gives the system designer additional flexibility.
•
The debounced manual reset input is negative edge triggered.
•
The reset pulse period generated by a MR transition is a
minimum of 800 ms and a maximum of 2 sec duration. In
addition, The MR input signal is blocked for an additional 49µS
minimum after the reset pulse ends. During the MR disable
period, the microcontroller is guaranteed a time period free of
additional manual reset signals. During this period DRAM
contents can be refreshed or other critical system tasks
undertaken. Low power consumption makes the ASM161/162
ideal for use in portable and battery operated equipments. With
3V supplies power consumption is 8µW typically and 30µW
maximum. The ASM161 has an open-drain, active-LOW
RESET output and requires an external pull-up resistor. The
ASM162 has an active HIGH RESET output.
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•
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Edge triggered manual reset input
single pulse output
49µS minimum MR disable period after reset
CMOS/TTL logic or switch interface
Debounced input
Low supply current extends battery life
• 6µA / 15µA typ/max at 5.5V
• 4.5µA / 10µA typ/max at 3.6V
Long reset period
• 0.8 sec minimum, 2 sec maximum
Two reset polarity options
• ASM161: Active LOW, open-drain
• ASM162: Active HIGH
Pinout matches the AS811/812
Small 4-Pin SOT-143 package
Two temperature ranges: 00 to 700c and -400c to +850c
Applications
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PDAs
Appliances
Computers and embedded controllers
Wireless communication systems
Battery operated and intelligent instruments
Automotive systems
Safety systems
Typical Operating Circuit
The ASM161/162 are offered in compact 4-pin SOT-143
packages. No external components are required to trim
threshold voltage for monitoring different supply voltages. With
six different factory set, reset, threshold ranges from 2.63V to
VCC
4.63V, the ASM161/162 are suitable for monitoring 5V, 3.6V
and 3.0V supplies. The ASM161/162 are available in
ASM161
(ASM162)
RESET
(RESET)
Reset Threshold
Part Suffix
Voltage (V)
L
4.63
M
4.38
J
4.00
T
3.08
S
2.93
R
2.63
VCC
VCC
temperature ranges 00 to 700c and -400c to +850c.
20k for
ASM161
only
RESET
(RESET)
µP
MR
GND
GND
Alliance Semiconductor
2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
ASM161 / ASM162
October 2003
rev 1.0
Block Diagram
4
Reset Circuit
+
3
VCC
ASM161/162
-
Voltage
Divider
* Edge Trigger
Bandgap
Reference
4
2
ASM161
RESET (ASM161)
RESET (ASM162)
2
MR
Debounce
Reset
Circuit
~
~
MR
RPU
~
VCC
* Non-retriggerable, edge
triggered manual reset
1
GND
Pin Configuration
SOT-143
GND
SOT-143
4
1
VCC
GND
1
ASM161
RESET
VCC
3
MR
ASM162
3
2
4
MR
RESET
2
RESET is open drain
Pin Description
Pin #
Pin Name
ASM161
ASM162
1
1
GND
Description
Ground.
Active-LOW, open-drain reset output. RESET remains LOW while VCC is below the
2
-
RESET
reset threshold and for 800ms minimum after VCC rises above the reset threshold.
An external pull-up resistor is needed.
-
2
RESET
Active HIGH reset output. RESET remains HIGH while VCC is below the reset
threshold and for 800ms after VCC rises above the reset threshold.
3
3
MR
Manual reset input. A negative going edge transition on MR asserts reset. Reset
remains asserted for one reset time-out period (800 ms min). This active-LOW
input has an internal pull-up resistor. It can be driven from a TTL or CMOS logic line
or shorted to ground with a switch. Leave open if unused.
4
4
VCC
Power supply input voltage.
µP Supervisory Circuit
Notice: The information in this document is subject to change without notice
2 of 9
ASM161 / ASM162
October 2003
rev 1.0
Detailed Descriptions
The MR pin must be taken HIGH and LOW again after the
tMRD period has been completed to initiate another reset
The reset function ensures the microprocessor is properly
pulse.
reset and powers up into a known condition after a power
The manual reset input has an internal 20kΩ pull-up resistor.
failure.
MR can be left open if not used.
tMD
Reset Timing
A reset is generated whenever the supply voltage is below
the threshold level (VCC < VTH). The reset duration is at least
MR
Triggering
Pulse
800ms after VCC has risen above the reset threshold and is
guaranteed to be no more than 2 seconds. The rest signal
tMRD
remains active as long as the monitored supply voltage is
Reset
Time-Out
below the internal threshold voltage.
RESET
*Second and following edges ignored
The ASM161 has an open-drain, active LOW RESET output
Figure 1: Manual Reset Timing
(which is guaranteed to be in the correct state for VCC down
to 1.1 V). The ASM161 uses an external pull-up resistor.
Ready
for
next
MR
MR input is blocked
*........
Output leakage current is under 1µA. A high resistance value
Application Information
can be used to minimize current drain.
Glitch Resistance
The ASM161/162 are relatively immune to short duration
The ASM162 generates an active-HIGH RESET output.
negative-going VCC transients/glitches. A VCC transient that
goes 100mV below the reset threshold and lasts 20s or less
will not typically cause a reset pulse.
Part Number
Reset Polarity
ASM161
LOW (use external pull-up resistor)
ASM162
HIGH
VCC
100KΩ
ASM162
Power Supply
RESET
MR
Manual Reset
The ASM161/162 have a unique manual reset circuit. A
GND
negative going edge transition on MR initiates the reset. A
manual reset generates a single reset pulse of fixed length.
The output-reset pulse remains asserted for the Reset Active
Figure 2: RESET valid with VCC under 1.1V
Time-Out Period tRP and then clears. Once the reset pulse is
Valid Reset with VCC under 1.1V
completed, the MR input remains disabled for at least 49µS
To ensure that logic inputs connected to the ASM162 RESET
but not more than 122µS. This period is specified as tMRD.
pin are in a known state when VCC is under 1.1V, a 100kΩ
pull-down resistor at RESET is needed. The value is not
During the MR disabled period, the microcontroller is
critical.
guaranteed a time period free of new manual reset signals.
This period can be used to refresh critical DRAM contents or
This scheme does not work with the open-drain outputs of
other system tasks.
ASM161.
µP Supervisory Circuit
Notice: The information in this document is subject to change without notice
3 of 9
ASM161 / ASM162
October 2003
rev 1.0
Absolute Maximum Ratings
Parameter
Min
Max
Unit
VCC
-0.3
6.0
V
RESET, RESET and MR
-0.3
VCC + 0.3
V
20
mA
Rate of Rise at VCC
100
V/µs
Power Dissipation (TA = 70°C)
320
mW
Pin Terminal Voltage with respect to Ground
Input Current at VCC and MR
Operating Temperature Range
-40
85
°C
Storage Temperature Range
-65
160
°C
300
°C
Lead Temperature (soldering, 10 sec)
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged time periods may affect device reliability.
µP Supervisory Circuit
Notice: The information in this document is subject to change without notice
4 of 9
ASM161 / ASM162
October 2003
rev 1.0
Electrical Characteristics
Unless otherwise noted, VCC is over the full range and TA = 00 to 700c for ASM161/162 X C and TA = -400c to +850c for ASM161/
162 X E devices. Typical values at TA = 250c, VCC = 5V for L/M/J devices, VCC = 3.3V for T/S devices and VCC = 3V for R devices
Parameter
Input Voltage (VCC)
Range
Supply Current
(Unloaded)
Symbol
VCC
ICC
Conditions
TA = 0°C to 70°C
VCC < 5.5V,
TA = -40°C to +85°C
L/M/J
TA = 0°C to 70°C,
VCC < 3.6V,
TA = -40°C to +85°C
R/S/T
L Devices
TA = 25°C
4.56
Note 1
4.50
TA = 25°C
4.31
Note 1
4.25
TA = 25°C
3.93
Note 1
3.89
TA = 25°C
3.04
Note 1
3.00
TA = 25°C
2.89
Note 1
2.85
TA = 25°C
2.59
Note 1
2.55
J devices
VTH
T devices
S devices
R devices
Reset Threshold Temp
Coefficient
Reset Pulse Width
MR Minimum Pulse
Width
6
VCC = VTH to (VTH -100mV)
tRPW
TA = 0°C to 70°C
800
TA = -40°C to 85°C
560
tMR
Unit
5.5
V
15
4.5
10
4.63
4.70
4.75
4.38
4.45
4.50
4.00
4.06
4.10
3.08
V
3.11
3.15
2.93
2.96
3.00
2.63
2.66
2.70
30
ppm/
°C
20
µS
1400
2000
ms
2240
10
MR Glitch Immunity
MR to RESET Propagation Delay
Max
µA
TCVTH
VCC to reset delay
Typ
1.1
TA = 0°C to 70°C,
M devices
Reset Threshold
Min
tMD
µP Supervisory Circuit
Notice: The information in this document is subject to change without notice
µS
100
ns
0.5
µs
5 of 9
ASM161 / ASM162
October 2003
rev 1.0
Parameter
Symbol
VIH
VIL
MR Input Threshold
VCC > VTH(MAX), L/M/J devices
VIH
VIL
MR Delay to MR Retrigger
Conditions
tMRD
Min
0.7VCC
TA = 0°C to 70°C
VCC = VTH min., ISINK = 3.2mA,
VOH
VDRAIN < 6.0V, 0°C < TA < 70°C
1
VCC = VTH min., ISINK = 1.2mA,
0.3
ASM162 R/S/T
V
µA
V
VCC = VTH min., ISINK = 3.2mA,
1.8<VCC<VTHmin., ISOURCE = 150 µA
KΩ
0.3
0.4
ASM162 L/M/J
HIGH RESET Output
Voltage (ASM162)
30
0.4
ASM161 L/M/J
VOL
20
0.3
VCC > 1.1, ISINK = 50µA
Low RESET output voltage (ASM162)
122
85
ASM161 R/S/T
ILKG
85
V
µS
TA = -40°C to 85°C
VCC = VTH min., ISINK = 1.2mA,
RESET Output Leakage Current (ASM161)
V
V
0.25VCC
49
Unit
V
0.8
10
VOL
Max
2.3
VCC > VTH(MAX), R/S/T devices
MR pull-up resistance
Low RESET output voltage (ASM161)
Typ
0.8VCC
V
Notes: 1. Over operating temperature range.
µP Supervisory Circuit
Notice: The information in this document is subject to change without notice
6 of 9
ASM161 / ASM162
October 2003
rev 1.0
Package Dimensions
Plastic SOT - 143 (4Pin)
e1
B
Inches
E
B1
Min
H
e
Max
A
0.031
0.047
0.787
1.194
A1
0.001
0.005
0.025
0.127
B
0.014
0.022
0.356
0.559
B1
0.030
0.038
0.762
0.965
C
0.0034
0.006
0.086
0.152
D
0.105
0.120
2.667
3.048
E
0.047
0.055
1.194
1.397
e
0.070
0.080
1.778
2.032
e1
0.071
0.079
1.803
2.007
H
0.082
0.098
2.083
2.489
L
0.004
0.012
0.102
0.305
A
a = 0° -8°
e
Min
Plastic SOT-143 (4-Pin)
D
A1
Max
Millimeters
C
L
Plastic SOT - 143 (4 pin)
µP Supervisory Circuit
Notice: The information in this document is subject to change without notice
7 of 9
ASM161 / ASM162
October 2003
rev 1.0
Ordering Information
Part Number1
Reset
Threshold
(V)
Temperature
Range
(°C)
Pin-Package
Package Marking
(XX Lot Code)
ASM161LCUS/T
4.63
0 TO 70
4-SOT-143
TAXX
ASM161MCUS/T
4.38
0 TO 70
4-SOT-143
TBXX
ASM161JCUS/T
4.00
0 TO 70
4-SOT-143
TCXX
ASM161TCUS/T
3.08
0 TO 70
4-SOT-143
TDXX
ASM161SCUS/T
2.93
0 TO 70
4-SOT-143
TEXX
ASM161RCUS/T
2.63
0 TO 70
4-SOT-143
TFXX
ASM162LCUS/T
4.63
0 TO 70
4-SOT-143
TGXX
ASM162MCUS/T
4.38
0 TO 70
4-SOT-143
THXX
ASM162JCUS/T
4.00
0 TO 70
4-SOT-143
TIXX
ASM162TCUS/T
3.08
0 TO 70
4-SOT-143
TJXX
ASM162SCUS/T
2.93
0 TO 70
4-SOT-143
TKXX
ASM162RCUS/T
2.63
0 TO 70
4-SOT-143
TLXX
ASM161LEUS/T
4.63
-40 TO 85
4-SOT-143
TMXX
ASM161MEUS/T
4.38
-40 TO 85
4-SOT-143
TNXX
ASM161JEUS/T
4.00
-40 TO 85
4-SOT-143
TOXX
ASM161TEUS/T
3.08
-40 TO 85
4-SOT-143
TPXX
ASM161SEUS/T
2.93
-40 TO 85
4-SOT-143
TQXX
ASM161REUS/T
2.63
-40 TO 85
4-SOT-143
TRXX
ASM162LEUS/T
4.63
-40 TO 85
4-SOT-143
TSXX
ASM162MEUS/T
4.38
-40 TO 85
4-SOT-143
TTXX
ASM162JEUS/T
4.00
-40 TO 85
4-SOT-143
TUXX
ASM162TEUS/T
3.08
-40 TO 85
4-SOT-143
TVXX
ASM162SEUS/T
2.93
-40 TO 85
4-SOT-143
TWXX
ASM162REUS/T
2.63
-40 TO 85
4-SOT-143
TXXX
Notes: 1. Tape and Reel packaging is indicated by the /T designation.
µP Supervisory Circuit
Notice: The information in this document is subject to change without notice
8 of 9
ASM161 / ASM162
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Fax: 408 - 855 - 4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM161 / ASM162
Document Version: 1.0
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or
registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the
right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the
right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these
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