AD ADM1185ARMZ Quad voltage monitor and sequencer Datasheet

Quad Voltage Monitor and Sequencer
ADM1185
Preliminary Technical Data
FEATURES
Powered from 2.7V to 5.5V on the VCC pin
Monitors Four Supplies via 0.8% Accurate Comparators
Four inputs can be programmed for voltage levels with
resistor dividers
Three Open-Drain Enable Outputs
Open-Drain Power Good Output
10-pin MSOP Package
FUNCTIONAL BLOCK DIAGRAM
VCC
ADM1185
POWER AND
REFERENCE
GENERATOR
REF=0.6V
OUT1
VIN1
REF=0.6V
APPLICATIONS
OUT2
Monitor and Alarm Functions
Power Supply Sequencing
Telecommunication and Datacommunication Equipment
PC/Servers
VIN2
REF=0.6V
OUT3
VIN3
LOGIC
REF=0.6V
GENERAL DESCRIPTION
The ADM1185 is an integrated four channel voltage monitoring
device. A 2.7V to 5.5V power supply is required on the VCC pin
to power the device.
VIN4
PWRGD
REF=0.6V
Four precision comparators monitor four voltage rails. All
comparators have a 0.6V reference with a worst-case accuracy
of 0.8%. Resistor networks external to the VIN1-VIN4 pins set
the trip points.
GND
Figure 1.
There are four open-drain outputs on the device. A digital core
interprets the comparator outputs and asserts the outputs as
appropriate.
APPLICATIONS DIAGRAM
3.3V IN
2.5V OUT
1.8V OUT
1.2V OUT
IN
Regulator1
VCC
VIN1
OUT1
VIN2
OUT2
VIN3
OUT3
EN
2.5V OUT
OUT
IN
VIN4
Regulator2
EN
1.8V OUT
OUT
ADM1185
GND
IN
PWRGD
Regulator3
EN
OUT
1.2V OUT
POWER
GOOD
Figure 2.
Rev. PrK June 2006
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© 2006 Analog Devices, Inc. All rights reserved.
ADM1185
Preliminary Technical Data
TABLE OF CONTENTS
REVISION HISTORY
Rev. PrK | Page 2 of 12
Preliminary Technical Data
ADM1185
ADM1185—SPECIFICATIONS
VVCC = 2.7V to 5.5V, TA = -40°C to +85°C
Table 1.
Parameter
VCC Pin
Operating Voltage Range, VVCC
Supply Current, IVCC
VIN1-VIN4 Pins
Input Current, IVINLEAK
Input Rising Threshold, VTHR
Input Rising Hysteresis, VHYST (=VTHR -VTHF)
OUT1-OUT3, PWRGD Pins
Output low voltage, VOUTL
Leakage Current, IALERT
VVCC that guarantees outputs valid
VIN1 to OUT1 Delay
VIN4 to PWRGD Delay
High-to-Low Propagation Delay
Low-to-High Propagation Delay
Min
Typ
Max
Units
30
5.5
100
V
µA
100
0.6048
nA
V
mV
VVINx = 0.7V
0.4
0.4
1
V
V
µA
V
VVCC = 2.7 V, ISINK = 2mA
VVCC = 1 V, ISINK =100µA
2.7
-100
0.5952
0.6000
9
-1
1
100
100
190
190
280
280
30
30
Rev. PrK | Page 3 of 12
ms
ms
µs
µs
Conditions
All outputs will be guaranteed to be either
low or giving a valid output level from VVCC
= 1V.
VVIN1 Rising
VVIN4 Rising, condition only valid at certain
operational states, refer to state diagram
VVCC =3.3V, see TPC1
VVCC =3.3V, see TPC1
ADM1185
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC Pin
VIN1-VIN4 Pin
OUT1-OUT3, PWRGD Pins
Power Dissipation
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
TBD
−65°C to +125°C
−40°C to +85°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only. Functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
Ambient temperature = 25°C, unless otherwise noted.
300°C
150°C
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrK | Page 4 of 12
Preliminary Technical Data
ADM1185
PIN CONFIGURATIONS
GND
1
VIN1
2
VIN2
3
VIN3
4
VIN4
5
ADM1185
TOP VIEW
10
Vcc
9
OUT1
8
OUT2
(NOT TO SCALE) 7 OUT3
6
PWRGD
Figure 3. Pin Configurations
PIN FUNCTIONAL DESCRIPTIONS
Table 3.
Pin No.
1
2
Name
GND
VIN1
3
VIN2
4
VIN3
5
VIN4
6
PWRGD
7
OUT3
8
OUT2
9
OUT1
10
VCC
Description
Chip Ground Pin.
Non-inverting input of comparator 1. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 2. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 3. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Non-inverting input of comparator 4. The voltage on this pin is compared with a 0.6V reference. Can be used
to monitor a voltage rail via a resistor divider.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN4 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if any of the voltages on the VIN1VIN4 pins falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN3 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN2 is greater than 0.6V. After power-up (after PWRGD asserts) this output will be driven low
if the voltage on VIN1 falls below 0.6V.
Open-drain output. During a power-up sequence (before PWRGD asserts) this output will assert high when
the voltage on VIN1 is greater than 0.6V. A time delay of 190ms (typical) is included before assertion of this
pin. After power-up (after PWRGD asserts) this output will be driven low if the voltage on VIN1 falls below
0.6V.
Positive supply input pin. The operating supply voltage range is 2.7 V to 5.5 V.
Rev. PrK | Page 5 of 12
ADM1185
Preliminary Technical Data
TYPICAL PERFORMANCE CURVES
v(pad)
Output 800
Low
775
Voltage
(mV) 750
Voltage
(mV)
725
700
675
650
625
600
575
550
525
500
475
x1e-3
450
425
400
375
350
325
300
275
250
2mA. 85degC/SLOW
225
200
175
150
125
100
75
50
25
0
.5
Duration (us)
TPC 1. Maximum transient duration Without Causing an Output Pulse vs.
Output Comparator Overdrive
Rev. PrK | Page 6 of 12
1
1.5
2
2.5
3
3.5
vsupply
Supply Voltage
(V)
4
4.5
TPC 2. Output Low Voltage vs. Supply Voltage
5
5.5
Preliminary Technical Data
ADM1185
Functional Description
The operation of the ADM1185 is explained in this section in
the context of the device in a voltage monitoring and
sequencing application (figure 4, above). In this application, the
ADM1185 will monitor four separate voltage rails, turn on
three regulators in a predefined sequence and generate a power
good signal to turn on a controller when all power supplies are
up and stable.
POWER ON SEQUENCING AND MONITORING
The main supply (in this case 3.3V) powers up the device via
the VCC pin as the voltage rises. A supply voltage of 2.7V to
5.5V is needed to power the device.
The VIN1 pin is monitoring the main 3.3V supply. An external
resistor divider will scale this voltage down for monitoring at
the VIN1 pin. The resistor ratio is chosen so that the VIN1
voltage is 0.6V when the main voltage rises to the preferred
level at start-up (some voltage below the nominal 3.3V level). In
this case, R1 is 4.6K and R2 is 1.2K so that a voltage level of
2.9V will correspond to 0.6V on the non-inverting input of the
first comparator.
VOLTAGE MONITORING AFTER POWER ON
V
3.3V
2.9V
0V
t
ADM1185
4.6K
VIN1
2.9V supply
gives 0.6V
at VIN1 pin
The assertion of OUT1 will turn on Regulator1. The 2.5V
output of this regulator will begin to rise. This will be detected
by input VIN2 (with a similar resistor divider scheme as shows
in figure 5). When VIN2 sees the 2.5V rail rise above its UV
point it will assert output OUT2, turning on Regulator2. A
capacitor can be placed on the VIN2 pin to slow the rise of the
voltage on this pin- this effectively sets a time delay between the
2.5V rail powering up and the next Regulator being enabled.
The same scheme is implemented with the other input and
output pins. Every rail that is turned on via an output pin
OUT(n) is monitored via input pin VIN(n+1).
The final comparator inside the VIN4 pin detects the final
supply turning on, which is 1.2V in this case. All of the output
pins (OUT1-OUT3) are logically ANDed together to generate a
system power good signal (PWRGD). There is an internal
190ms delay associated with the assertion of the PWRGD
output.
Table 4 below is a truth table that steps through the power on
sequence of the outputs. Any associated internal time delays are
also shown.
1.2K
0.6V
TO LOGIC
CORE
Once PWRGD is asserted the logical core latches into a
different mode of operation. During the initial power up phase
each output is directly dependant on an input (i.e. VIN3
asserting causes OUT3 to assert). When power up is complete
this function is redundant.
Once in the PWRGD state the following behavior can be
observed:
•
If the main 3.3V supply that is monitored via VIN1
faults in the power good state then the PWRGD
output is deasserted to warn the downstream
controller and all of the outputs OUT1-OUT3 are
immediately turned off, disabling all locally generated
supplies.
•
If a supply monitored by VIN2-VIN4 fails the
PWRGD output is deasserted to warn the controller
but the other outputs are not deasserted.
Figure 4.Setting the undervoltage threshold with an external resistor divider
OUT1 is an open drain active high output. In this application,
OUT1 is connected to the enable pin of a regulator. Before the
voltage on VIN1 has reached 0.6V this output is switched to
ground, disabling regulator 1. (Note that all outputs are driven
to ground as long as there is 1V on the VCC pin of the
ADM1185). When the main system voltage reaches 2.9V VIN1
will detect 0.6V and this will cause OUT1 to assert after a
190ms delay. When this occurs the open drain output will
switch high and the external pull-up resistor will pull the
voltage on the regulator 1 enable pin above its turn-on
threshold, turning on the output of regulator 1.
Table 5 and table 6 are truth tables that highlight the behavior of
the ADM1185 under various fault situations during normal
operation (i.e. in the mode of operation after PWRGD has
asserted).
Rev. PrK | Page 7 of 12
ADM1185
Preliminary Technical Data
3.3V IN
2.5V OUT
1.8V OUT
1.2V OUT
IN
Regulator1
VCC
VIN1
OUT1
VIN2
OUT2
VIN3
OUT3
EN
2.5V OUT
OUT
IN
Regulator2
VIN4
EN
1.8V OUT
OUT
ADM1185
GND
IN
PWRGD
Regulator3
EN
OUT
1.2V OUT
POWER
GOOD
Figure 5. Applications Diagram showing ADM1185 in a voltage monitoring and sequencing application
State1 Start
IN1=OK
(Delay=100ms min)
State2
OUT1
On
IN2=OK
IN1=FAULT
State3
OUT1,2
On
IN3=OK
IN1=FAULT
State4
OUT1,2,3
On
IN4=OK
(Delay=100ms min)
IN1=FAULT
State5 PWRGD
IN1=FAULT
IN2.IN3.IN3=FAULT
Figure 6. Flow Diagram highlighting the different modes of operation o the logical core
State
1
2
3
4
5
State Name
OUT1
OUT2
OUT3
OUT4
Next Event
Next State
Reset*
Out1 On
Out1,2 On
Out1,2,3 On
PowerGood
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
IN1 High for 190ms
IN1 and IN2 High for 30us
IN1 and IN3 High for 30us
All High for 190ms
IN2 or IN3 or IN4 Low for
30us
IN1 Low for 30 us
Out1 On
Out1,2 On
Out1,2,3 On
PowerGood
Out1,2,3 On
Table 4. Truth table
Rev. PrK | Page 8 of 12
Start
Preliminary Technical Data
ADM1185
VIN1
V T(falling)
=0.6V
VIN1
V T (rising)
V T (rising)
tPROP
tPROP
OUT1
OUT1
OUT2
190ms
OUT2
190ms
tPROP
OUT3
OUT3
PWRGD
PWRGD
190ms
190ms
NOTE* The rising threshold on the VIN1-VIN4 pins will be slightly
higher than 0.6V as there is some hysteresis on this pin.
Figure 6. Power-up Waveforms
NOTE* The rising threshold on the VIN1-VIN4 pins will be slightly
higher than 0.6V as there is some hysteresis on this pin.
Figure 7. Waveforms showing reaction to a temporary low glitch on the
main supply
Rev. PrK | Page 9 of 12
ADM1185
Preliminary Technical Data
CASCADING MULTIPLE DEVICES
Multiple ADM1185 devices can be cascaded in situations where
a large number of supplies must be monitored and/or
sequenced. There are numerous configurations for
interconnecting devices. The most suitable configuration will
depend on the application. Figures 8, 9 and 10 show some
methods for cascading multiple ADM1185 devices.
3.3V
3.3V
ADM1185-A
VCC
3.3V
VIN1
V1
VIN2
V2
VIN3
V3
VIN4
Reg1
OUT1
EN1
V1
Reg2
OUT2
Reg3
OUT3
GND
Note: Supplies
scaled down with
resistor dividers
V2
EN2
EN3
V3
PWRGD
3.3V
ADM1185-B
VCC
VIN1
V4
VIN2
V5
VIN3
V6
VIN4
Reg4
OUT1
EN4
OUT2
V5
EN5
Reg6
OUT3
GND
V4
Reg5
EN6
PWRGD
Figure 8. Cascading multiple ADM1185 devices, option 1
Rev. PrK | Page 10 of 12
V6
POWER GOOD
Preliminary Technical Data
ADM1185
3.3V
3.3V
ADM1185-A
VCC
3.3V
Reg1
VIN1
V1
VIN2
V2
VIN3
3.3V
VIN4
OUT1
EN1
V1
Reg2
OUT2
V2
EN2
Reg3
OUT3
GND
EN3
V3
PWRGD
Note: Supplies
scaled down with
resistor dividers
3.3V
ADM1185-B
VCC
V3
Reg4
VIN1
V4
VIN2
V5
VIN3
V6
VIN4
OUT1
EN4
V4
Reg5
OUT2
V5
EN5
Reg6
OUT3
GND
EN6
V6
PWRGD
POWER GOOD
Figure 9. Cascading multiple ADM1185 devices, option 2
3.3V
3.3V
ADM1185-A
VCC
3.3V
VIN1
V1
VIN2
V2
VIN3
3.3V
VIN4
Reg1
OUT1
EN1
V1
Reg2
OUT2
V2
EN2
Reg3
OUT3
GND
EN3
V3
PWRGD
Note: Supplies
scaled down with
resistor dividers
3.3V
ADM1185-B
VCC
3.3V
VIN1
OUT1
V3
VIN2
OUT2
V5
VIN3
V6
VIN4
Reg4
Reg5
OUT3
GND
V4
EN4
EN5
PWRGD
V5
POWER GOOD
Figure 10. Cascading multiple ADM1185 devices, option 3
Rev. PrK | Page 11 of 12
ADM1185
Preliminary Technical Data
OUTLINE DIMENSIONS
0.122 (3.10)
0.114 (2.90)
10
6
0.114 (2.90)
1
PR06196-0-6/06(PrK)
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
5
PIN
1
0.0197 (0.50)
BSC
0.120 (3.05)
0.120 (3.05)
0.112 (2.85)
0.037 (0.94)
0.112 (2.85)
0.043 (1.10)
MAX
0.031 (0.78)
0.006 (0.15)
0.012 (0.30)
0.002 (0.05)
0.006 (0.15)
SEATING
PLANE
0.009 (0.23)
6o
o
0
0.005 (0.13)
0.028 (0.70)
0.016 (0.40)
Figure 9. 10-Lead MSOP Package
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1185ARMZ1
Temperature Range
-40°C to +85°C
Package Description
MSOP-10
Z=PB-free part
Rev. PrK | Page 12 of 12
Package Outline
RM-10
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