Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY54/74FCT543T 8-Bit Latched Registered Transceiver SCCS030 - May 1994 - Revised March 2000 Features Functional Description • Function, pinout, and drive compatible with FCT and F logic • FCT-C speed at 5.3 ns max. (Com’l) FCT-A speed at 6.5 ns max. (Com’l) • Reduced VOH (typically = 3.3V) versions of equivalent FCT functions • Edge-rate control circuitry for significantly improved noise characteristics • Power-off disable feature • Matched rise and fall times • Fully compatible with TTL input and output logic levels • ESD > 2000V • Sink current 64 mA (Com’l), 48 mA (Mil) Source current 32 mA (Com’l), 12 mA (Mil) • Separation controls for data flow in each direction • Back to back latches for storage • Extended commercial range of −40˚C to +85˚C Functional Block Diagram The FCT543T octal latched transceiver contains two sets of eight D-type latches with separate latch enable (LEAB, LEBA) and output enable (OEAB, OEBA) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B enable (CEAB) input must be LOW in order to enter data from A or to take data from B, as indicated in the truth table. With CEAB LOW, a LOW signal on the A-to-B latch enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their output no longer change with the A inputs. With CEAB and OEAB both LOW, the three-stage B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB, LEAB, and OEAB inputs. The outputs are designed with a power-off disable feature to allow for live insertion of boards. Logic Block Diagram Detail A B0 D Q A0 LE A0 A1 A2 A3 A4 A5 A6 CEAB Q D OEAB CEBA LE LEAB OEBA LEBA A1 B1 A2 B2 A3 B3 A4 Detail A x 7 A7 B0 B1 B2 B3 B4 B5 B6 B7 B4 A5 B5 A6 B6 A7 B7 Pin Configurations SOIC/QSOP Top View OEBA OEAB LEBA 1 24 CEAB OEBA 2 23 A0 3 22 B0 LEAB A1 4 21 B1 A2 5 20 B2 A3 6 19 B3 A4 7 18 B4 A5 8 17 B5 A6 9 16 B6 A7 10 15 B7 CEAB 11 14 LEAB GND 12 13 OEAB CEBA LEBA Copyright VCC CEBA © 2000, Texas Instruments Incorporated CY54/74FCT543T Maximum Ratings[4, 5] Pin Description Name (Above which the useful life may be impaired. For user guidelines, not tested.) Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) Ambient Temperature with Power Applied............................................. –65°C to +135°C CEBA B-to-A Enable Input (Active LOW) Supply Voltage to Ground Potential ............... –0.5V to +7.0V LEAB A-to-B Latch Enable Input (Active LOW) DC Input Voltage ........................................... –0.5V to +7.0V LEBA B-to-A Latch Enable Input (Active LOW) DC Output Voltage......................................... –0.5V to +7.0V A A-to-B Data Inputs or B-to-A Three-State Outputs DC Output Current (Maximum Sink Current/Pin) ...... 120 mA B B-to-A Data Inputs or A-to-B Three-State Outputs Power Dissipation .......................................................... 0.5W Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Function Table[1, 2] Inputs Latch Outputs CEAB LEAB OEAB A-to-B[3] B H X X Storing High Z X H X Storing X X X H X High Z L L L Transparent Current A Inputs L H L Storing Previous A Inputs Operating Range Range Range VCC Commercial DT 0°C to +70°C 5V ± 5% Commercial T, AT, CT –40°C to +85°C 5V ± 5% Military[6] All –55°C to +125°C 5V ± 10% Notes: 1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. 2. A-to-B data flow shown: B-to-A flow control is the same, except using CEBA, LEBA, and OEBA. 3. Before LEAB LOW-to-HIGH Transition. 4. Unless otherwise noted, these limits are over the operating free-air temperature range. 5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 6. TA is the “instant on” case temperature. 2 Ambient Temperature CY54/74FCT543T Electrical Characteristics Over the Operating Range Parameter VOH Description Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage [8] Test Conditions Min. Typ.[7] Max. Unit VCC=Min., IOH=–32 mA Com’l 2.0 V VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V VCC=Min., IOH=–12 mA Mil 2.4 3.3 V VCC=Min., IOL=64 mA Com’l 0.3 0.55 V VCC=Min., IOL=48mA Mil 0.3 0.55 V 2.0 V 0.8 VH Hysteresis All inputs 0.2 VIK Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 IIH Input HIGH Current IIH Input HIGH Current[8] IIL Input LOW Current[8] IOZH Off State HIGH-Level Output Current IOZL V V –1.2 V VCC=Max., VIN=VCC 5 µA VCC=Max., VIN=2.7V ±1 µA VCC=Max., VIN=0.5V ±1 µA VCC=Max., VOUT = 2.7V 10 µA Off State LOW-Level Output Current VCC= Max., VOUT = 0.5V –10 µA IOS Output Short Circuit Current[9] VCC=Max., VOUT=0.0V –225 mA IOFF Power-Off Disable VCC=0V, VOUT=4.5V ±1 µA –60 –120 Capacitance[8] Parameter Description Typ.[7] Max. Unit CIN Input Capacitance 5 10 pF COUT Output Capacitance 9 12 pF Notes: 7. Typical values are at VCC=5.0V, TA=+25˚C ambient. 8. This parameter is specified but not tested. 9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 3 CY54/74FCT543T Power Supply Characteristics Parameter ICC Description Test Conditions Quiescent Power Supply Current VCC=Max., VIN≤0.2V, VIN≥VCC–0.2V Typ.[7] Max. Unit 0.1 0.2 mA ∆ICC Quiescent Power Supply Current VCC=Max., VIN=3.4V, (TTL inputs) f1=0, Outputs Open 0.5 2.0 mA ICCD Dynamic Power Supply Current[11] VCC=Max., One Input Toggling, 50% Duty Cycle, Outputs Open, CEAB and OEAB=LOW, CEBA=HIGH, VIN≤0.2V or VIN≥VCC–0.2V 0.06 0.12 mA/MHz IC Total Power Supply Current[12] VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, CEAB and OEAB=LOW,CEBA=HIGH, f0=LEAB = 10 MHz, VIN≤0.2V or VIN≥VCC–0.2V 0.7 1.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, One Bit Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB = 10 MHz, VIN=3.4V or VIN=GND 1.2 3.4 mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB = 10 MHz, VIN≤0.2V or VIN≥VCC–0.2V 2.8 5.6[13] mA VCC=Max., f0=10 MHz, 50% Duty Cycle, Outputs Open, Eight Bits Toggling at f1=5 MHz, CEAB and OEAB=LOW, CEBA=HIGH, f0=LEAB = 10 MHz, VIN=3.4V or VIN=GND 5.1 14.6[13] mA [10] Notes: 10. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 11. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 12. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 13. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 4 CY54/74FCT543T Switching Characteristics Over the Operating Range[14] FCT543T Military Parameter Description FCT543AT Commercial Commercial Min.[14] Max. Min.[14] Max. Min.[14] Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Transparent Mode A to B or B to A 2.0 10.0 2.5 8.5 2.5 6.5 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A, LEAB to B 2.5 14.0 2.5 12.5 2.5 8.0 ns 1, 5 tPZH tPZL Output Enable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 2.0 14.0 2.0 12.0 2.0 9.0 ns 1, 7, 8 tPZH tPZL Output Disable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 2.0 13.0 2.0 9.0 2.0 7.5 ns 1, 7, 8 tS Set-Up Time HIGH or LOW, A or B to LEBA or LEAB 3.0 2.0 2.0 ns 9 tH Hold Time HIGH or LOW, A or B to LEBA or LEAB 2.0 2.0 2.0 ns 9 tW Pulse Width LOW[8] LEBA or LEAB 5.0 5.0 5.0 ns 5 FCT543CT Commercial Parameter Description Min.[14] Max. Unit Fig. No.[15] tPLH tPHL Propagation Delay Transparent Mode A to B or B to A 2.5 5.3 ns 1, 3 tPLH tPHL Propagation Delay LEBA to A, LEAB to B 2.5 7.0 ns 1, 5 tPZH tPZL Output Enable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 2.0 8.0 ns 1, 7, 8 tPZH tPZL Output Disable Time OEBA or OEAB to A or B CEBA or CEAB to A or B 2.0 6.5 ns 1, 7, 8 tS Set-Up Time, HIGH or LOW, A or B to LEBA or LEAB 2.0 ns 9 tH Hold Time, HIGH or LOW, A or B to LEBA or LEAB 2.0 ns 9 tW Pulse Width LOW LEBA or LEAB[8] 5.0 ns 5 Notes: 14. Minimum limits are specified but not tested on Propagation Delays. 15. See “Parameter Measurement Information” in the General Information Section. 5 CY54/74FCT543T Ordering Information Speed (ns) 5.3 6.5 8.5 10.0 Ordering Code Package Name Package Type CY74FCT543CTQCT Q13 24-Lead (150-Mil) QSOP CY74FCT543CTSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT543ATQCT Q13 24-Lead (150-Mil) QSOP CY74FCT543ATSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY74FCT543TQCT Q13 24-Lead (150-Mil) QSOP CY74FCT543TSOC/SOCT S13 24-Lead (300-Mil) Molded SOIC CY54FCT543TDMB D14 24-Lead (300-Mil) CerDIP Document #: 38-00264-B 6 Operating Range Commercial Commercial Commercial Military CY54/74FCT543T Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D-9 Config.A 24-Lead Quarter Size Outline Q13 7 CY54/74FCT543T Package Diagrams (continued) 24-Lead (300-Mil) Molded SOIC S13 8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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