LINER LTC3892-2 Low iq, 60v synchronous boostbuck controller Datasheet

LTC7813
Low IQ, 60V Synchronous
Boost+Buck Controller
Features
Description
Synchronous Boost and Buck Controllers
nn When Cascaded, Allows V Above, Below, or Equal
IN
to Regulated VOUT of Up to 60V
nn Wide Bias Input Voltage Range: 4.5V to 60V
nn Output Remains in Regulation Through Input Dips
(e.g. Cold Crank) Down to 2.2V
nn Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE)
nn Low EMI with Low Input and Output Ripple
nn Fast Output Transient Response
nn No External Bootstrap Diodes Required
nn High Light Load Efficiency
nn Low Operating I : 29µA (One Channel On)
Q
nn Low Operating I : 34µA (Both Channels On)
Q
nn R
or
Lossless
DCR Current Sensing
SENSE
nn Buck Output Voltage Range: 0.8V ≤ V
OUT ≤ 60V
nn Boost Output Voltage Up 60V
nn Phase-Lockable Frequency (75kHz to 850kHz)
nn Small 32-Pin 5mm × 5mm QFN Package
The LTC®7813 is a high performance synchronous
Boost+Buck DC/DC switching regulator controller that
drives all N-channel power MOSFET stages. It contains
independent step-up (boost) and step-down (buck)
controllers that can regulate two separate outputs or be
cascaded to regulate an output voltage from an input
voltage that can be above, below, or equal to the output
voltage. The LTC7813 operates from a wide 4.5V to 60V
input supply range. When biased from the output of the
boost regulator, the LTC7813 can operate from an input
supply as low as 2.2V after start-up. The 34μA no-load
quiescent current (both channels on) extends operating
runtime in battery-powered systems.
nn
Unlike conventional buck-boost regulators, the LTC7813’s
cascaded Boost+Buck solution has continuous, nonpulsating, input and output currents, substantially reducing
voltage ripple and EMI. The LTC7813 has independent
feedback and compensation points for the boost and buck
regulation loops, enabling a fast output transient response
that can be externally optimized.
Applications
nn
nn
Automotive and Industrial Power Systems
High Power Battery Operated Systems
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective
owners.
Typical Application
Wide Input Range to 10V/10A Low IQ Cascaded Boost+Buck Regulator
VIN
8V TO 60V
DOWN TO
2.2V AFTER
START-UP
2.2µH
47µF
10µH
VMID, 12V**
6.8µF
×4
22µF
×3
22µF
×3
47µF
1.62k
2.32k
15k
33pF
0.1µF
1µF
0.1µF
0.1µF
SENSE2+ SENSE2– BG2 SW2 BOOST2
TG2
VFB2
VBIAS
TG1
BOOST1
ITH2
TRACK/SS1 SS2
RB1
332k
RA1
11.5k
SW1 BG1
SENSE1+ SENSE1– VFB1
LTC7813
RUN1 RUN2 ITH1
47µF
VOUT
10V
10A*
EXTVCC
FREQ PLLIN/MODE GND DRVCC
INTVCC VPRG2 ILIM DRVUV DRVSET
7813 TA01
VIN
8.87k
0.1µF
6.19k
470pF
100pF
3300pF
22nF
37.4k
4.7µF
0.1µF
0.1µF
* WHEN VIN <8V MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
**VMID = 12V WHEN VIN < 12V
VMID FOLLOWS VIN WHEN VIN > 12V
7813f
For more information www.linear.com/LTC7813
1
LTC7813
Absolute Maximum Ratings
Pin Configuration
(Note 1)
EXTVCC
VBIAS
BG2
BOOST2
TG2
SW2
BG1
BOOST1
TOP VIEW
32 31 30 29 28 27 26 25
SW1 1
24 DRVCC
TG1 2
23 SS2
22 DRVSET
TRACK/SS1 3
VPRG2 4
21 DRVUV
33
GND
ITH1 5
20 ITH2
VFB1 6
19 VFB2
SENSE1+ 7
18 ILIM
SENSE1– 8
17 RUN2
RUN1
INTVCC
PGOOD1
SENSE2–
GND
SENSE2+
FREQ
9 10 11 12 13 14 15 16
PLLIN/MODE
Bias Input Supply Voltage (VBIAS)............... –0.3V to 65V
Topside Driver Voltages
BOOST1, BOOST2................................... –0.3V to 76V
Switch Voltage (SW1, SW2)........................... –5V to 70V
DRVCC, (BOOST1-SW1), (BOOST2-SW2).....–0.3V to 11V
BG1, BG2, TG1, TG2............................................ (Note 8)
RUN1, RUN2 Voltages................................. –0.3V to 65V
SENSE1+, SENSE2+, SENSE1–
SENSE2– Voltages...................................... –0.3V to 65V
PLLIN/MODE, FREQ, DRVSET Voltages........ –0.3V to 6V
EXTVCC Voltage.......................................... –0.3V to 14V
ITH1, ITH2, VFB1 Voltages............................. –0.3V to 6V
VFB2 Voltage................................................ –0.3V to 65V
VPRG2 Voltage............................................. –0.3V to 6V
TRACK/SS1, SS2 Voltages............................ –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC7813E, LTC7813I........................... –40°C to 125°C
LTC7813H........................................... –40°C to 150°C
LTC7813MP........................................ –55°C to 150°C
Storage Temperature Range................... –65°C to 150°C
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 150°C, θJA = 44°C/W
EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC7813EUH#PBF
LTC7813EUH#TRPBF
7813
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC7813IUH#PBF
LTC7813IUH#TRPBF
7813
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 125°C
LTC7813HUH#PBF
LTC7813HUH#TRPBF
7813
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 150°C
LTC7813MPUH#PBF
LTC7813MPUH#TRPBF
7813
32-Lead (5mm × 5mm) Plastic QFN
–55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
7813f
For more information www.linear.com/LTC7813
LTC7813
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VBIAS = 12V, VRUN1,2 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG2 = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VBIAS
Bias Input Supply Operating Voltage Range
4.5
60
V
VOUT1
Buck Regulated Output Voltage Set Point
0.8
60
V
VOUT2
Boost Regulated Output Voltage Set Point
60
V
VSENSE2(CM)
SENSE2 Pins Common Mode Range
(BOOST Converter Input Supply Voltage)
60
V
VFB1
Buck Regulated Feedback Voltage
VFB2
2.2
(Note 4) ITH1 Voltage = 1.2V
0°C to 85°C
Boost Regulated Feedback Voltage
(Note 4) ITH2 Voltage = 1.2V
VPRG2 = 0V
VPRG2 = FLOAT
VPRG2 = INTVCC
l
0.792
0.788
0.800
0.800
0.808
0.812
V
V
l
l
l
1.182
9.78
11.74
1.200
10.00
12.00
1.218
10.22
12.26
V
V
V
–2
±50
nA
IFB1
Buck Feedback Current
(Note 4)
IFB2
Boost Feedback Current
(Note 4)
VPRG2 = 0V
VPRG2 = FLOAT
VPRG2 = INTVCC
±0.01
4
5
±0.05
6
7
µA
µA
µA
Reference Voltage Line Regulation
(Note 4) VBIAS = 4.5V to 60V
0.002
0.02
%/V
Output Voltage Load Regulation
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
l
0.01
0.1
%
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 2V
l
–0.01
–0.1
%
gm1,2
Transconductance Amplifier gm
(Note 4) ITH1,2 = 1.2V, Sink/Source 5µA
IQ
Input DC Supply Current
(Note 5), VDRVSET = 0V
Pulse-Skipping or Forced Continuous Mode
(One Channel On)
RUN1 = 5V and RUN2 = 0V or
RUN2 = 5V and RUN1 = 0V
VFB1 = 0.83V (No Load), VFB2 = 1.25V (No Load)
1.6
0.8
mA
mA
Pulse-Skipping or Forced Continuous Mode
(Both Channels On)
RUN1,2 = 5V, VFB1 = 0.83V (No Load),
VFB2 = 1.25V (No Load)
2.2
mA
Sleep Mode (One Channel On, Buck)
RUN1 = 5V and RUN2 = 0V
VFB1 = 0.83V (No Load)
Sleep Mode (One Channel On, Boost)
Sleep Mode (Both Channels On)
UVLO
2
mmho
29
55
µA
RUN2 = 5V and RUN1 = 0V, VFB2 = 1.25V (No Load)
29
50
µA
RUN1 = 5V and RUN2 = 5V,
VFB1 = 0.83V (No Load), VFB2 = 1.25V (No Load)
34
55
µA
Shutdown
RUN1,2 = 0V
3.6
10
µA
Undervoltage Lockout
DRVCC Ramping Up
DRVUV = 0V
DRVUV = INTVCC
l
l
4.0
7.5
4.2
7.8
V
V
DRVCC Ramping Down
DRVUV = 0V
DRVUV = INTVCC
l
l
3.6
6.4
3.8
6.7
4.0
7.0
V
V
7
10
Buck Feedback Overvoltage Protection
Measured at VFB1 Relative to Regulated VFB1
l
SENSE1+ Pin Current
SENSE2+ Pin Current
13
%
±1
µA
170
SENSE1– Pin Current
VSENSE1– < VINTVCC – 0.5V
VSENSE1– > VINTVCC + 0.5V
SENSE2– Pin Current
VSENSE2+, VSENSE2– = 12V
700
µA
±1
µA
µA
±1
µA
7813f
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3
LTC7813
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VBIAS = 12V, VRUN1,2 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG2 = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Duty Factor for TG
Buck (Channel 1) in Dropout, FREQ = 0V
Boost (Channel 2)
97.5
99
100
%
%
Maximum Duty Factor for BG
Buck (Channel 1) in Overvoltage
Boost (Channel 2)
100
96
%
%
ITRACK/SS1
Soft-Start Charge Current
VTRACK/SS1 = 0V
8
10
12
µA
ISS2
Soft-Start Charge Current
VSS2 = 0V
8
10
12
µA
VRUN1,2 ON
RUN Pin On Threshold
VRUN1, VRUN2 Rising
l
1.22
1.275
1.33
V
ILIM = Float
ILIM = 0V
ILIM = INTVCC
l
l
l
65
43
90
RUN Pin Hysteresis
75
VSENSE1,2(MAX) Maximum Current Sense Threshold
75
50
100
mV
85
58
109
mV
mV
mV
Gate Driver
TG1,2
Pull-Up On-Resistance
Pull-Down On-Resistance
VDRVSET = INTVCC
2.2
1.0
Ω
Ω
BG1,2
Pull-Up On-Resistance
Pull-Down On-Resistance
VDRVSET = INTVCC
2.2
1.0
Ω
Ω
BOOST1,2 to DRVCC Switch On-Resistance
VSW1,2 = 0V, VDRVSET = INTVCC
3.7
Ω
TG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
BG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
Buck (Channel 1)
Boost (Channel 2)
55
85
ns
ns
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF Each Driver, VDRVSET = INTVCC
Buck (Channel 1)
Boost (Channel 2)
50
80
ns
ns
tON(MIN)1
Buck Minimum On-Time
(Note 7) VDRVSET = INTVCC
80
ns
tON(MIN)2
Boost Minimum On-Time
(Note 7) VDRVSET = INTVCC
120
ns
DRVCC Linear Regulator
DRVCC Voltage from Internal VBIAS LDO
VEXTVCC = 0V
7V < VBIAS < 60V, DRVSET = 0V
11V < VBIAS < 60V, DRVSET = INTVCC
DRVCC Load Regulation from VBIAS LDO
DRVCC Voltage from Internal EXTVCC LDO
ICC = 0mA to 50mA, VEXTVCC = 0V
7V < VEXTVCC < 13V, DRVSET = 0V
11V < VEXTVCC < 13V, DRVSET = INTVCC
DRVCC Load Regulation from Internal
EXTVCC LDO
ICC = 0mA to 50mA, VEXTVCC = 8.5V,
VDRVSET = 0V
EXTVCC LDO Switchover Voltage
EXTVCC Ramping Positive
DRVSET = 0V or RDRVSET ≤ 100kΩ
DRVSET = INTVCC
5.8
9.6
5.8
9.6
4.5
7.4
EXTVCC Hysteresis
4
Programmable DRVCC
RDRVSET = 50kΩ, VEXTVCC = 0V
Programmable DRVCC
RDRVSET = 70kΩ, VEXTVCC = 0V
Programmable DRVCC
RDRVSET = 90kΩ, VEXTVCC = 0V
6.4
6.0
10.0
6.2
10.4
V
V
0.9
2.0
%
6.0
10.0
6.2
10.4
V
V
0.7
2.0
%
4.7
7.7
4.9
8.0
V
V
250
mV
5.0
V
7.0
9.0
7.6
V
V
7813f
For more information www.linear.com/LTC7813
LTC7813
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VBIAS = 12V, VRUN1,2 = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG2 = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Oscillator and Phase-Locked Loop
PLLIN VIH
PLLIN VIL
Programmable Frequency
RFREQ =25kΩ, PLLIN/MODE = DC Voltage
105
Programmable Frequency
RFREQ = 65kΩ, PLLIN/MODE = DC Voltage
Programmable Frequency
RFREQ = 105kΩ, PLLIN/MODE = DC Voltage
Low Fixed Frequency
VFREQ = 0V, PLLIN/MODE = DC Voltage
High Fixed Frequency
VFREQ = INTVCC, PLLIN/MODE = DC Voltage
Synchronizable Frequency
PLLIN/MODE = External Clock
l
75
PLLIN/MODE Input High Level
PLLIN/MODE Input Low Level
PLLIN/MODE = External Clock
PLLIN/MODE = External Clock
l
l
2.5
375
440
kHz
505
835
320
350
485
535
kHz
kHz
380
kHz
585
kHz
850
kHz
0.5
V
V
BOOST2 Charge Pump
BOOST2 Charge Pump Available Output
Current
FREQ = 0V, PLLIN/MODE = INTVCC
VBOOST2 = 16.5V, VSW2 = 12V
VBOOST2 = 19V, VSW2 = 12V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Ratings for extended periods may affect device reliability and
lifetime.
Note 2: The LTC7813 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC7813E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC7813I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LTC7813H is guaranteed over the –40°C to 150°C operating junction
temperature range and the LTC7813MP is tested and guaranteed over
the –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
temperature (TJ, in °C) is calculated from the ambient temperature
(TA, in °C) and power dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA = 44°C.
75
35
µA
µA
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC7813 is tested in a feedback loop that servos VITH1,2 to a
specified voltage and measures the resultant VFB1,2. The specification at
85°C is not tested in production and is assured by design, characterization
and correlation to production testing at other temperatures (125°C for
the LTC7813E and LTC7813I, 150°C for the LTC7813H and LTC7813MP).
For the LTC7813I and LTC7813H, the specification at 0°C is not tested in
production and is assured by design, characterization and correlation to
production testing at –40°C. For the LTC7813MP, the specification at 0°C
is not tested in production and is assured by design, characterization and
correlation to production testing at –55°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current >40% of IMAX (See Minimum On-Time
Considerations in the Applications Information section).
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
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5
LTC7813
Typical Performance Characteristics
Efficiency vs Load Current,
VIN = 24V
Efficiency vs Load Current,
VIN = 18V
100
100
100
80
80
80
70
70
70
50
40
30
0
0.0001
0.001
0.01
0.1
LOAD CURRENT (A)
1
50
40
30
0
0.0001
7
0.001
Power Loss vs Load Current,
VIN = 18V
10
FIGURE 15 CIRCUIT
VOUT = 24V
Power Loss vs Load Current,
VIN = 24V
1
7
0.001
0.0001
92
IOUT = 2A
IOUT = 4A
5 10 15 20 25 30 35 40 45 50 55 60
INPUT VOLTAGE (V)
7813 G07
6
REGULATED FEEDBACK VOLTAGE (mV)
EFFICIENCY (%)
94
7
Power Loss vs Load Current,
VIN = 36V
FIGURE 15 CIRCUIT
VOUT = 24V
0.1
0.001
0.01
0.1
LOAD CURRENT (A)
1
0.001
0.0001
7
Burst Mode
PS Mode
FC Mode
0.001
0.01
0.1
LOAD CURRENT (A)
1.212
806
1.209
802
800
798
796
794
792
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7813 G08
7
Boost Regulated Feedback
Voltage vs Temperature
808
804
1
7813 G06
Buck Regulated Feedback Voltage
vs Temperature
96
1
7813 G05
Efficiency vs Input Voltage
FIGURE 15 CIRCUIT
VOUT = 24V
0.01
0.1
LOAD CURRENT (A)
0.01
BM
Burst Mode
PS ModePS
FC Mode
REGULATED FEEDBACK VOLTAGE (V)
0.01
0.1
LOAD CURRENT (A)
0.001
1
7813 G04
90
10
FIGURE 15 CIRCUIT
VOUT = 24V
POWER LOSS (W)
POWER LOSS (W)
0.001
Burst Mode
PS Mode
FC Mode
7813 G03
0.01
0.001
0.0001
30
0
0.0001
7
0.1
0.01
Burst Mode
PS Mode
FC Mode
40
10
1
0.1
98
1
50
7813 G02
1
100
0.01
0.1
LOAD CURRENT (A)
60
20
Burst Mode
PS Mode
FC Mode
10
7813 G01
PS = PULSE-SKIPPING
FC = FORCED CONTINUOUS
10
60
20
Burst Mode
PS Mode
FC Mode
10
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
60
20
FIGURE 15 CIRCUIT
90 VOUT = 24V
FIGURE 15 CIRCUIT
90 VOUT = 24V
FIGURE 15 CIRCUIT
90 VOUT = 24V
POWER LOSS (W)
Efficiency vs Load Current,
VIN = 36V
1.206
1.203
1.2
1.197
1.194
1.191
1.188
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7813 G09
7813f
For more information www.linear.com/LTC7813
LTC7813
Typical Performance Characteristics
Load Step at VIN = 18V,
Burst Mode Operation
Load Step at VIN = 24V,
Burst Mode Operation
Load Step at VIN = 36V,
Burst Mode Operation
VOUT
500mV/DIV
AC-COUPLED
VOUT
500mV/DIV
AC-COUPLED
VOUT
500mV/DIV
AC-COUPLED
IL1
1A/DIV
IL1
1A/DIV
IL1
1A/DIV
200µs/DIV
7813 G10
200µs/DIV
7813 G11
200µs/DIV
FIGURE 15 CIRCUIT
VOUT = 24V
FIGURE 15 CIRCUIT
VOUT = 24V
FIGURE 15 CIRCUIT
VOUT = 24V
Load Step at VIN = 18V,
Pulse-Skipping Mode
Load Step at VIN = 24V,
Pulse-Skipping Mode
Load Step at VIN = 36V,
Pulse-Skipping Mode
VOUT
500mV/DIV
AC-COUPLED
VOUT
500mV/DIV
AC-COUPLED
VOUT
500mV/DIV
AC-COUPLED
IL1
1A/DIV
IL1
1A/DIV
IL1
1A/DIV
200µs/DIV
7813 G13
200µs/DIV
7813 G14
200µs/DIV
FIGURE 15 CIRCUIT
VOUT = 24V
FIGURE 15 CIRCUIT
VOUT = 24V
FIGURE 15 CIRCUIT
VOUT = 24V
Load Step at VIN = 18V,
Forced Continuous Mode
Load Step at VIN = 24V,
Forced Continuous Mode
Load Step at VIN = 36V,
Forced Continuous Mode
VOUT
500mV/DIV
AC-COUPLED
VOUT
500mV/DIV
AC-COUPLED
VOUT
500mV/DIV
AC-COUPLED
IL1
1A/DIV
IL1
1A/DIV
IL1
1A/DIV
200µs/DIV
FIGURE 15 CIRCUIT
VOUT = 24V
7813 G16
200µs/DIV
7813 G17
FIGURE 15 CIRCUIT
VOUT = 24V
200µs/DIV
7813 G12
7813 G15
7813 G18
FIGURE 15 CIRCUIT
VOUT = 24V
7813f
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7
LTC7813
Typical Performance Characteristics
DRVCC VOLTAGE (V)
DRVCC VOLTAGE (V)
9
8
7
5
6.2
6
EXTVCC = 0V
5.8
5.6
EXTVCC = 8.5V
5
4.8
4.2
4
0 5 10 15 20 25 30 35 40 45 50 55 60 65
INPUT VOLTAGE (V)
EXTVCC = 5V
25
50
75
100
LOAD CURRENT (mA)
125
EXTVCC FALLING
500
400
SENSE2+ PIN (BOOST)
100
180
EXTVCC RISING
VIN = 12V
SENSE2+ PIN
160
600
500
400
300
200
140
120
100
80
60
40
100
0
-75 -50 -25
0 5 10 15 20 25 30 35 40 45 50 55 60 65
VSENSE COMMON MODE VOLTAGE (V)
DRVSET = GND
Boost SENSE2 Pins Input Current
vs Temperature
VOUT1 > INTVCC + 0.5V
700
DRVCC
6
7813 G21
SENSE CURRENT (µA)
SENSE1– CURRENT (µA)
SENSE CURRENT (µA)
600
0
7
200
800
SENSE1– PIN (BUCK)
200
EXTVCC RISING
EXTVCC FALLING
4
-75 -50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
150
900
800
300
8
Buck SENSE1– Pin Input Bias
Current vs Temperature
SENSE Pins Input Current
vs VSENSE Voltage
DRVSET = INTVCC
7813 G20
7813 G19
700
9
5
VBIAS = 12V
DRVSET = GND
0
DRVCC
10
5.4
5.2
4.6
4.4
DRVSET = GND
6
11
6.4
DRVSET = INTVCC
10
EXTVCC Switchover and DRVCC
Voltages vs Temperature
DRVCC VOLTAGE (V)
11
DRVCC and EXTVCC
vs Load Current
DRVCC Line Regulation
20
VOUT1 < INTVCC – 0.5V
0
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
SENSE2– PIN
0 25 50 75 100 125 150
TEMPERATURE (°C)
7813 G23
7813 G24
7813 G22
Maximum Current Sense
Threshold vs Duty Cycle
100
80
BOOST
70
BUCK
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
7813 G25
8
TRACK/SS1 and SS2 Pull-Up
Current vs Temperature
12
5% DUTY CYCLE
80
TRACK/SS AND SS2 CURRENT (µA)
90
CURRENT SENSE VOLTAGE (mV)
MAXIMUM CURRENT SENSE VOLTAGE (µA)
100
Maximum Current Sense
Threshold vs ITH Voltage
PULSE-SKIPPING
60
Burst Mode
OPERATION
40
20
ILIM = GND
ILIM = FLOAT
ILIM = INTVCC
0
–20
–40
FORCED CONTINUOUS MODE
0
0.2
0.4
0.6 0.8
VITH (V)
1
1.2
1.4
7813 G26
11.5
11
10.5
10
9.5
9
8.5
8
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7813 G27
7813f
For more information www.linear.com/LTC7813
LTC7813
Typical Performance Characteristics
Shutdown Current vs
Input Voltage
Shutdown Current vs Temperature
VBIAS = 12V
SHUTDOWN CURRENT (µA)
6
5
4
3
2
80
12
70
10
8
6
4
2
1
0
-75 -50 -25
0
0 25 50 75 100 125 150
TEMPERATURE (°C)
7813 G28
30
ILIM = INTVCC
ILIM = FLOAT
ILIM = GND
0
0
400
FREQ = GND
10
6
5
4
1
0
150°C
25°C
–55°C
FREQ = 350kHz
10MΩ LOAD BETWEEN BOOST2 AND SW2
5 10 15 20 25 30 35 40 45 50 55 60 65
SW2 VOLTAGE (V)
7813 G34
CHARGE PUMP CHARGING CURRENT (µA)
BOOST2 – SW2 VOLTAGE (V)
7
2
5.5
5
4.5
4
RISING
0 25 50 75 100 125 150
TEMPERATURE (°C)
DRVUV = GND
FALLING
3
-75 -50 -25
0 25 50 75 100 125 150
TEMPERATURE (°C)
7813 G33
BOOST2 Charge Pump Charging
Current vs Switch Voltage
120
100
8
FALLING
6
BOOST2 Charge Pump Charging
Current vs Frequency
9
DRVUV = INTVCC
7813 G32
BOOST2 Charge Pump Output
Voltage vs SW2 Voltage
3
6.5
3.5
7813 G31
RISING
7
450
300
-75 -50 -25
100 200 300 400 500 600 700 800
VFB1 FEEDBACK VOLTAGE (mV)
7.5
500
350
0 25 50 75 100 125 150
TEMPERATURE (°C)
Undervoltage Lockout Threshold
vs Temperature
DRVCC VOLTAGE (V)
FREQUENCY (kHz)
MAXIMUM CURRENT SENSE VOLTAGE (mV)
40
DRVSET = GND
20
7813 G30
FREQ = INTVCC
550
80
50
DRVSET = INTV CC
30
8
90
10
40
0
–75 –50 –25
0 5 10 15 20 25 30 35 40 45 50 55 60 65
VBIAS INPUT VOLTAGE (V)
600
60
DRVSET = 70kΩ
50
Oscillator Frequency vs
Temperature
100
20
60
7813 G29
Buck Foldback Current Limit
70
VBIAS = 12V
ONE CHANNEL ON
Burst Mode OPERATION
10
90
80
–55°C
70
25°C
60
50
40
150°C
30
20
10
VBOOST2 = 16.5V
VSW2 = 12V
0
100
200 300 400 500 600 700
OPERATING FREQUENCY (kHz)
800
7813 G35
CHARGE PUMP CHARGING CURRENT (µA)
SHUTDOWN CURRENT (µA)
7
Quiescent Current vs Temperature
14
QUIESCENT CURRENT (µA)
8
110
– 55°C
100
90
80
VBOOST2 – VSW2 = 4.5V
70
25°C
150°C
60
50
40
30
20
10
0
VBOOST2 – VSW2 = 7.0V
–55°C
25°C
150°C
FREQ = 350kHz
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SW2 VOLTAGE (V)
7813 G36
7813f
For more information www.linear.com/LTC7813
9
LTC7813
Typical Performance Characteristics
Buck Inductor Current at Light
Load
Start-Up
Boost Inductor Current at Light
Load
FORCED CONTINUOUS MODE
FORCED CONTINUOUS MODE
VOUT
5V/DIV
IL1
2A/DIV
IL2
2A/DIV
Burst Mode OPERATION
Burst Mode OPERATION
RUN
5V/DIV
PULSE-SKIPPING MODE
5ms/DIV
FIGURE 15 CIRCUIT
7813 G37
5µs/DIV
FIGURE 15 CIRCUIT
VIN = 32V
VOUT = 24V
IOUT = 1mA
7813 G38
PULSE-SKIPPING MODE
5µs/DIV
FIGURE 15 CIRCUIT
VIN = 18V
VOUT = 24V
IOUT = 1mA
7813 G39
Pin Functions
SW1, SW2 (Pins 1, 30): Switch Node Connections to
Inductors.
TG1, TG2 (Pins 2, 29): High Current Gate Drives for Top
N-Channel MOSFETs. These are the outputs of floating
drivers with a voltage swing equal to DRVCC superimposed
on the switch node voltage SW.
TRACK/SS1, SS2 (Pins 3, 23): External Tracking and SoftStart Input. For the buck channel, the LTC7813 regulates
the VFB1 voltage to the smaller of 0.8V, or the voltage on
the TRACK/SS1 pin. For the boost channel, the LTC7813
regulates the VFB2 voltage to the smaller of 1.2V, or the
voltage on the SS2 pin. An internal 10µA pull-up current
source is connected to this pin. A capacitor to ground at
this pin sets the ramp time to final regulated output voltage.
Alternatively, a resistor divider on another voltage supply
connected to the TRACK/SS1 pin allows the LTC7813 buck
output to track the other supply during start-up.
VPRG2 (Pin 4): Channel 2 Output Control Pin. This pin
sets the boost channel to adjustable output mode using
external feedback resistors or fixed 10V/12V output mode
using internal resistive dividers. Grounding this pin allows
the output to be programmed through the VFB2 pin using
external resistors, regulating VFB2 to the 1.2V reference.
Floating this pin or connecting it to INTVCC programs the
output to 10V or 12V (respectively), with VFB2 used to
sense the output voltage.
10
ITH1, ITH2 (Pins 5, 20): Error Amplifier Outputs and
Switching Regulator Compensation Points. Each associated channel’s current comparator trip point increases
with this control voltage.
VFB1 (Pin 6): This pin receives the remotely sensed feedback
voltage for the buck controller from an external resistive
divider across the output.
SENSE1+, SENSE2+ (Pins 7, 12): The (+) Input to the
Differential Current Comparators. The ITH pin voltage and
controlled offsets between the SENSE– and SENSE+ pins
in conjunction with RSENSE set the current trip threshold.
For the boost channel, the SENSE2+ pin supplies current
to the current comparator.
SENSE1–, SENSE2– (Pins 8, 13): The (–) Input to the
Differential Current Comparators. When SENSE1– for the
buck channel is greater than INTVCC, the SENSE1– pin
supplies current to the current comparator.
FREQ (Pin 9): The frequency control pin for the internal
VCO. Connecting this pin to GND forces the VCO to a fixed
low frequency of 350kHz. Connecting this pin to INTVCC
forces the VCO to a fixed high frequency of 535kHz.
Other frequencies between 50kHz and 900kHz can be
programmed using a resistor between FREQ and GND.
The resistor and an internal 20µA source current create a
voltage used by the internal oscillator to set the frequency.
For more information www.linear.com/LTC7813
7813f
LTC7813
Pin Functions
PLLIN/MODE (Pin 10): External Synchronization Input
to Phase Detector and Forced Continuous Mode Input.
When an external clock is applied to this pin, the phaselocked loop will force the rising TG1 and BG2 signals
to be synchronized with the rising edge of the external
clock, and the regulators will operate in forced continuous
mode. When not synchronizing to an external clock, this
input, which acts on both controllers, determines how the
LTC7813 operates at light loads. Pulling this pin to ground
selects Burst Mode® operation. An internal 100k resistor
to ground also invokes Burst Mode operation when the
pin is floated. Tying this pin to INTVCC forces continuous
inductor current operation. Tying this pin to a voltage
greater than 1.1V and less than INTVCC – 1.3V selects
pulse-skipping operation. This can be done by connecting
a 100k resistor from this pin to INTVCC.
GND (Pin 11, Exposed Pad Pin 33): Ground. The exposed
pad must be soldered to the PCB for rated electrical and
thermal performance.
PGOOD1 (Pin 14): Open-Drain Logic Output. PGOOD1 is
pulled to ground when the voltage on the VFB1 pin is not
within ±10% of its set point.
INTVCC (Pin 15): Output of the Internal 5V Low Dropout
Regulator. The low voltage analog and digital circuits
are powered from this voltage source. A low ESR 0.1µF
ceramic bypass capacitor should be connected between
INTVCC and GND, as close as possible to the IC.
RUN1, RUN2 (Pins 16, 17): Run Control Inputs for Each
Controller. Forcing either of these pins below 1.2V shuts
down that controller. Forcing both of these pins below
0.7V shuts down the entire LTC7813, reducing quiescent
current to approximately 3.6µA.
ILIM (Pin 18): Current Comparator Sense Voltage Range
Input. Tying this pin to GND or INTVCC or floating it sets
the maximum current sense threshold (for both channels)
to one of three different levels (50mV, 100mV, or 75mV,
respectively).
VFB2 (Pin 19): If VPRG2 is grounded, this pin receives the
remotely sensed feedback voltage for the boost controller from an external resistive divider across the output. If
VPRG2 is floated or tied to INTVCC, this pin receives the
remotely sensed output voltage of the boost controller.
DRVUV (Pin 21): Determines the higher or lower DRVCC
UVLO and EXTVCC switchover thresholds, as listed on
the Electrical Characteristics table. Connecting DRVUV to
GND chooses the lower thresholds whereas tying DRVUV
to INTVCC chooses the higher thresholds.
DRVSET (Pin 22): Sets the regulated output voltage of the
DRVCC LDO regulator. Connecting this pin to GND sets
DRVCC to 6V whereas connecting it to INTVCC sets DRVCC
to 10V. Voltages between 5V and 10V can be programmed
by placing a resistor (50k to 100k) between the DRVSET
pin and GND.
DRVCC (Pin 24): Output of the Internal or External Low
Dropout (LDO) Regulator. The gate drivers are powered
from this voltage source. The DRVCC voltage is set by the
DRVSET pin. Must be decoupled to ground with a minimum
of 4.7µF ceramic or other low ESR capacitor. Do not use
the DRVCC pin for any other purpose.
EXTVCC (Pin 25): External Power Input to an Internal LDO
Connected to DRVCC. This LDO supplies DRVCC power,
bypassing the internal LDO powered from VBIAS whenever
EXTVCC is higher than its switchover threshold (4.7V or
7.7V depending on the DRVSET pin). See EXTVCC Connection in the Applications Information section. Do not float
or exceed 14V on this pin. Do not connect EXTVCC to a
voltage greater than VBIAS. Connect to GND if not used.
VBIAS (Pin 26): Main Supply Pin. A bypass capacitor should
be tied between this pin and the GND pin.
BG1, BG2 (Pins 31, 27): High Current Gate Drives for
Bottom N-Channel MOSFETs. Voltage swing at these pins
is from ground to DRVCC.
BOOST1, BOOST2 (Pins 32, 28): Bootstrapped Supplies
to the Topside Floating Drivers. Capacitors are connected
between the BOOST and SW pins. Voltage swing at BOOST1
is from approximately DRVCC to (VIN1 + DRVCC). Voltage
swing at BOOST2 is from approximately DRVCC to (VOUT2
+ DRVCC).
7813f
For more information www.linear.com/LTC7813
11
LTC7813
Functional Diagrams
BUCK CHANNEL 1
FREQ
DRVCC
VIN1
20µA
BOOST1
VCO CLK
TOP
DROPOUT
DET
PFD
S
Q
R
Q
TG1
BOT
CIN1
CB1
SW1
TOP ON
L1
DRVCC
BG1
BOT
SWITCHING
LOGIC
SHDN
RSENSE1
VOUT1
COUT1
GND
SYNC
DET
PLLIN/MODE
+
–
0.425V
100k
ILIM
+
–
ICMP
SLEEP
+
+– –
–+
IR
SENSE1+
3mV
2.8V
0.65V
+
–
PGOOD1
+
–
SENSE1–
0.88V
SLOPE COMP
VFB1
0.72V
OV
3.5V
150nA
SHDN
RST
2(VFB)
FOLDBACK
RB1
VFB1
–
+
0.80V
TRACK/SS1
+
–
0.88V
EA +
RA1
CC1
ITH1
CC1A
10µA
RC1
TRACK/SS1
CSS1
SHDN
RUN1
7813 FD01
20µA
DRVSET
2.00V
1.20V
DRVUV
EXTVCC
DRVCC LDO/UVLO
CONTROL
VIN
R
4R
+
–
DRVCC
EN
+
–
EN
4.7V/
7.7V
–
+
INTVCC
LDO
INTVCC
12
7813f
For more information www.linear.com/LTC7813
LTC7813
Functional Diagrams
BOOST CHANNEL 2
DRVCC
CHARGE
PUMP
BOOST2
CLK
S
Q
R
Q
BOTTOM
TOP
VOUT2
CB2
TG2
COUT2
L2
SW2
SHDN
SWITCHING
LOGIC
DRVCC
BOT
RSENSE2
VIN2
CIN2
BG2
GND
PLLIN/MODE
+
–
0.425V
ILIM
+
–
ICMP
SLEEP
+
+– –
–+
IR
SENSE2–
3mV
2.8V
0.7V
SENSE2+
SLOPE COMP
+
–
SNSLO
2V
VPRG2
EA
OV
3.5V
RB2
VFB2
–
+
+
1.2V
SS2
+
–
1.32V
CC2
ITH2
150nA
CC2A
10µA
SHDN
VOUT2
RA2
RC2
SS2
CSS2
SNSLO
RUN2
7813 FD02
7813f
For more information www.linear.com/LTC7813
13
LTC7813
Operation
(Refer to the Functional Diagrams)
Main Control Loop
The LTC7813 uses a constant frequency, current mode
control architecture. Channel 1 is a buck (step-down)
controller, and channel 2 is a boost (step-up) controller.
During normal operation, the external top MOSFET for
the buck channel (the external bottom MOSFET for the
boost controller) is turned on when the clock for that
channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin (which is generated with an external resistor divider
connected across the output voltage, VOUT, to ground)
to the internal 0.800V reference voltage (1.2V reference
voltage for the boost). When the load current increases,
it causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the top MOSFET for the buck (the bottom MOSFET for
the boost) is turned off each cycle, the bottom MOSFET is
turned on (the top MOSFET for the boost) until either the
inductor current starts to reverse, as indicated by the current comparator IR, or the beginning of the next clock cycle.
DRVCC/EXTVCC/INTVCC Power
Power for the top and bottom MOSFET drivers is derived
from the DRVCC pin. The DRVCC supply voltage can be
programmed from 5V to 10V through control of the
DRVSET pin. When the EXTVCC pin is tied to a voltage
below its switchover voltage (4.7V or 7.7V depending
on the DRVUV voltage), the VBIAS LDO (low dropout
linear regulator) supplies power from VBIAS to DRVCC. If
EXTVCC is taken above its switchover voltage, the VBIAS
LDO is turned off and an EXTVCC LDO is turned on. Once
enabled, the EXTVCC LDO supplies power from EXTVCC
to DRVCC. Using the EXTVCC pin allows the DRVCC power
to be derived from a high efficiency external source such
as the LTC7813 buck regulator output.
Each top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during each
cycle through an internal switch whenever SW goes low.
14
For buck channel 1, if the input voltage decreases to a
voltage close to its output, the loop may enter dropout
and attempt to turn on the top MOSFET continuously. The
dropout detector detects this and forces the top MOSFET off
for about one-twelfth of the clock period every tenth cycle
to allow CB to recharge, resulting in about 99% duty cycle.
The INTVCC supply powers most of the other internal circuits
in the LTC7813. The INTVCC LDO regulates to a fixed value
of 5V and its power is derived from the DRVCC supply.
Shutdown and Start-Up (RUN, TRACK/SS Pins)
The two channels of the LTC7813 can be independently
shut down using the RUN1 and RUN2 pins. Pulling a RUN
pin below 1.22V shuts down the main control loop for
that channel. Pulling both pins below 0.7V disables both
controllers and most internal circuits, including the DRVCC
and INTVCC LDOs. In this state, the LTC7813 draws only
3.6μA of quiescent current.
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Each RUN pin
may be externally pulled up or driven directly by logic. Each
RUN pin can tolerate up to 65V (absolute maximum), so it
can be conveniently tied to VBIAS in always-on applications
where one or both controllers are enabled continuously
and never shut down.
The start-up of each controller’s output voltage VOUT
is controlled by the voltage on the TRACK/SS pin
(TRACK/SS1 for channel 1, SS2 for channel 2). When the
voltage on the TRACK/SS pin is less than the 0.8V internal
reference for the buck and the 1.2V internal reference for
the boost, the LTC7813 regulates the VFB voltage to the
TRACK/SS pin voltage instead of the corresponding reference voltage. This allows the TRACK/SS pin to be used to
program a soft-start by connecting an external capacitor
from the TRACK/SS pin to GND. An internal 10μA pull-up
current charges this capacitor creating a voltage ramp on
the TRACK/SS pin. As the TRACK/SS voltage rises linearly
from 0V to 0.8V/1.2V (and beyond up to about 4V), the
output voltage VOUT rises smoothly from zero (VIN for the
boost) to its final value.
7813f
For more information www.linear.com/LTC7813
LTC7813
Operation
(Refer to the Functional Diagrams)
Alternatively the TRACK/SS1 pin for the buck channel
can be used to cause the start-up of VOUT1 to track that of
another supply. Typically, this requires connecting to the
TRACK/SS1 pin an external resistor divider from the other
supply to ground (see the Applications Information section).
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC7813 can be enabled to enter high efficiency Burst
Mode operation, constant frequency pulse-skipping mode,
or forced continuous conduction mode at low load currents.
To select Burst Mode operation, tie the PLLIN/MODE pin to
GND. To select forced continuous operation, tie the PLLIN/
MODE pin to INTVCC. To select pulse-skipping mode, tie
the PLLIN/MODE pin to a DC voltage greater than 1.1V and
less than INTVCC – 1.3V. This can be done by connecting
a 100kΩ resistor between PLLIN/MODE and INTVCC.
When a controller is enabled for Burst Mode operation,
the minimum peak current in the inductor is set to approximately 25% of the maximum sense voltage (30%
for the boost) even though the voltage on the ITH pin
indicates a lower value. If the average inductor current is
higher than the load current, the error amplifier, EA, will
decrease the voltage on the ITH pin. When the ITH voltage drops below 0.425V, the internal sleep signal goes
high (enabling sleep mode) and both external MOSFETs
are turned off. The ITH pin is then disconnected from the
output of the EA and parked at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC7813 draws. If
one channel is in sleep mode and the other is shut down,
the LTC7813 draws only 29μA of quiescent current (with
DRVSET = 0V). If both controllers are enabled in sleep
mode, the LTC7813 draws only 34μA of quiescent current. In sleep mode, the load current is supplied by the
output capacitor. As the output voltage decreases, the
EA’s output begins to rise. When the output voltage drops
enough, the ITH pin is reconnected to the output of the
EA, the sleep signal goes low, and the controller resumes
normal operation by turning on the top external MOSFET
(the bottom external MOSFET for the boost) on the next
cycle of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET (the top external MOSFET for the boost) just
before the inductor current reaches zero, preventing it
from reversing and going negative. Thus, the controller
operates discontinuously.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and
less interference to audio circuitry. In forced continuous
mode, the output ripple is independent of load current.
Clocking the LTC7813 from an external source enables
forced continuous mode (see the Frequency Selection
and Phase-Locked Loop section).
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC7813 operates in PWM pulse-skipping mode
at light loads. In this mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator, ICMP, may remain tripped for several cycles
and force the external top MOSFET (bottom for the boost)
to stay off for the same number of cycles (i.e., skipping
pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous
operation, exhibits low output ripple as well as low audio
noise and reduced RF interference as compared to Burst
Mode operation. It provides higher low current efficiency
than forced continuous mode, but not nearly as high as
Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
7813f
For more information www.linear.com/LTC7813
15
LTC7813
Operation
(Refer to the Functional Diagrams)
The switching frequency of the LTC7813’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to GND, tied to
INTVCC or programmed through an external resistor. Tying
FREQ to GND selects 350kHz while tying FREQ to INTVCC
selects 535kHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 10.
A phase-locked loop (PLL) is available on the LTC7813
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC7813’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of TG1 and BG2 to the rising edge of the synchronizing signal.
The VCO input voltage is prebiased to the operating frequency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1 and BG2. The
ability to prebias the loop filter allows the PLL to lock-in
rapidly without deviating far from the desired frequency.
The typical capture range of the LTC7813’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guarantee to be between 75kHz and 850kHz. In other words, the
LTC7813’s PLL is guaranteed to lock to an external clock
source whose frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling). It is recommended
that the external clock source swings from ground (0V)
to at least 2.5V.
Boost Controller Operation When VIN2 > VOUT2
When the input voltage to the boost channel rises above
its regulated VOUT2 voltage, the controller can behave
differently depending on the mode, inductor current and
VIN2 voltage. In forced continuous mode, the loop works
16
to keep the top MOSFET on continuously once VIN2 rises
above VOUT2. An internal charge pump delivers current to
the boost capacitor from the BOOST2 pin to maintain a
sufficiently high TG2 voltage. Because the LTC7813 uses
internal switches and does not require external bootstrap
diodes, the charge pump only has to overcome small
leakage currents (board leakage, etc.).
In pulse-skipping mode, if VIN is between 0% and 10%
above the regulated VOUT2 voltage, TG2 turns on if the
inductor current rises above approximately 3% of the
programmed ILIM current. If the part is programmed in
Burst Mode operation under this same VIN2 window, then
TG2 turns on at the same threshold current as long as
the chip is awake (the buck channel is awake and switching). If the buck channel is asleep or shut down in this
VIN2 window, then TG2 will remain off regardless of the
inductor current.
If VIN rises more than 10% above the regulated VOUT
voltage in any mode, the controller turns on TG2 regardless of the inductor current. In Burst Mode operation,
however, the internal charge pump turns off if the entire
chip is asleep (if the buck channel is also asleep or shut
down). With the charge pump off, there would be nothing
to prevent the boost capacitor from discharging, resulting in an insufficient TG2 voltage needed to keep the top
MOSFET completely on. The charge pump turns back on
when the chip wakes up, and it remains on as long as the
buck channel is actively switching.
Boost Controller at Low SENSE Pin Common Voltage
The current comparator of the boost controller is powered
directly from the SENSE2+ pin and can operate to voltages
as low as 2.2V. Since this is lower than the VBIAS UVLO of
the chip, VBIAS can be connected to the output of the boost
controller, as illustrated in the typical application circuit in
Figure 12. This allows the boost controller to handle input
voltage transients down to 2.2V while maintaining output
voltage regulation. If SENSE2+ falls below 2.0V, then
switching stops and SS2 is pulled low. If SENSE2+ rises
back above 2.2V, the SS2 pin will be released, initiating a
new soft-start sequence.
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LTC7813
Operation
(Refer to the Functional Diagrams)
Buck Controller Output Overvoltage Protection
Buck Foldback Current
The buck channel has an overvoltage comparator that
guards against transient overshoots as well as other more
serious conditions that may overvoltage the output. When
the VFB1 pin rises by more than 10% above its regulation
point of 0.800V, the top MOSFET is turned off and the
bottom MOSFET is turned on until the overvoltage condition is cleared.
When the buck output voltage falls to less than 70% of
its nominal level, foldback current limiting is activated,
progressively lowering the peak current limit in proportion
to the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB1 voltage is keeping up with the
TRACK/SS1 voltage). There is no foldback current limiting
for the boost channel.
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17
LTC7813
Applications Information
Cascaded Boost+Buck Regulator
The LTC7813 can be configured to regulate two separate,
completely independent outputs, one boost and one buck.
Or, it can be configured as a cascaded Boost+Buck single
output converter that regulates an output voltage from
an input voltage that can be above, below, or equal to the
output voltage. When cascaded, the input voltage feeds
the boost regulator, which generates an intermediate node
supply (VMID) that then serves as the input to the buck
regulator, which then regulates the output voltage.
When used as a cascaded Boost+Buck regulator, the
LTC7813 has distinct advantages compared to traditional
single inductor buck-boost regulators. Even though it
requires two inductors, these inductors are individually
smaller and provide inherent filtering at the input and
output, substantially reducing conducted EMI and voltage ripple, thereby requiring less input and output filtering. Even though they are cascaded, the boost and buck
regulators are independently optimized and compensated.
The buck regulator provides a very fast transient response
compared to a buck-boost regulator, further reducing
the amount of output capacitance that is required. The
LTC7813 also features a very low quiescent current Burst
Mode which dramatically reduces power loss and increases
efficiency at light loads. Thus, for those applications that
require low EMI, low ripple, fast transient response, low
quiescent current, and/or high light load efficiency, the
LTC7813 cascaded Boost+Buck regulator provides an
excellent solution.
The Typical Application on the first page is a basic LTC7813
application circuit. LTC7813 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
has become popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
18
power MOSFETs are selected. Finally, input and output
capacitors are selected.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current comparators.
Buck Controller (SENSE1 + /SENSE1 – ): The common
mode voltage range on these pins is 0V to 65V (absolute
maximum), enabling the LTC7813 to regulate buck output
voltages up to a nominal 60V set point (allowing margin
for tolerances and transients). The SENSE1+ pin is high
impedance over the full common mode range, drawing
at most ±1μA. This high impedance allows the current
comparators to be used in inductor DCR sensing. The
impedance of the SENSE1– pin changes depending on
the common mode voltage. When SENSE1– is less than
INTVCC – 0.5V, a small current of less than 1μA flows
out of the pin. When SENSE1– is above INTVCC + 0.5V,
a higher current (≈700μA) flows into the pin. Between
INTVCC – 0.5V and INTVCC + 0.5V, the current transitions
from the smaller current to the higher current.
Boost Controller (SENSE2+/SENSE2–): The common
mode input range for these pins is 2.2V to 60V, allowing
the boost converter to operate from inputs over this full
range. The SENSE2+ pin also provides power to the current comparator and draws about 170μA during normal
operation (when not shut down or asleep in Burst Mode
operation). There is a small bias current of less than 1μA
that flows into the SENSE2– pin. This high impedance on
the SENSE2– pin allows the current comparator to be used
in inductor DCR sensing.
Filter components mutual to the sense lines should be
placed close to the LTC7813, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing current elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing is
used (Figure 2b), R1 should be placed close to the switching node, to prevent noise from coupling into sensitive
small-signal nodes.
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LTC7813
Applications Information
TO SENSE FILTER
NEXT TO THE CONTROLLER
VIN1
(VOUT2)
BOOST
TG
CURRENT FLOW
INDUCTOR OR RSENSE
LTC7813
VOUT1
(VIN2)
BG
7813 F01
Figure 1. Sense Lines Placement with Inductor or Sense Resistor
Low Value Resistor Current Sensing
SENSE1+
(SENSE2–)
The current comparators have a maximum threshold
VSENSE(MAX) of 50mV, 75mV or 100mV. The current
comparator threshold voltage sets the peak of the inductor current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ∆IL. To calculate the sense resistor value,
use the equation:
VSENSE(MAX)
∆I
IMAX + L
2
GND
7813 F02a
(2a) Using a Resistor to Sense Current
VIN1
(VOUT2)
BOOST
INDUCTOR
TG
LTC7813
L
SW
For applications requiring the highest possible efficiency
at high load currents, the LTC7813 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
VOUT1
(VIN2)
R1
C1*
SENSE1–
(SENSE2+)
Inductor DCR Sensing
DCR
BG
SENSE1+
(SENSE2–)
When using the buck controller in very low dropout conditions, the maximum output current level will be reduced
due to the internal compensation required to meet stability
criteria for buck regulators operating at greater than 50%
duty factor. A curve is provided in the Typical Performance
Characteristics section to estimate this reduction in peak
inductor current depending upon the operating duty factor.
CAP
PLACED NEAR SENSE PINS
SENSE1–
(SENSE2+)
A typical sensing circuit using a discrete resistor is shown
in Figure 2a. RSENSE is chosen based on the required
output current.
RSENSE =
RSENSE
SW
R2
GND
*PLACE C1 NEAR SENSE PINS
(R1||R2) • C1 = L/DCR
RSENSE(EQ) = DCR(R2/(R1+R2))
7813 F02b
(2b) Using the Inductor DCR to Sense Current
Figure 2. Current Sensing Methods
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
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19
LTC7813
Applications Information
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
VSENSE(MAX)
∆I
IMAX + L
2
PLOSS R1=
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for VSENSE(MAX) in the Electrical Characteristics table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD =
RSENSE(EQUIV)
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1|| R2 to around 2k, reducing error that
might have been caused by the SENSE1+/SENSE2– pin’s
±1μA current.
The equivalent resistance R1||R2 is scaled to the temperature inductance and maximum DCR:
L
R1 R2 =
(DCR at 20°C) • C1

R1 R2
R1• RD
R1=
; R2 =
RD
1−RD

20
R1
R1
Inductor Value Calculation
The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current, ∆IL, decreases with higher
inductance or higher frequency. For the buck controllers,
∆IL increases with higher VIN:
⎛ V ⎞
1
VOUT ⎜1− OUT ⎟
VIN ⎠
( f) (L)
⎝
For the boost controller, ∆IL increases with higher VOUT:
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=
( VOUT(MAX) − VIN ) • VIN
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor,
due to the extra switching losses incurred through R1.
However, DCR sensing eliminates a sense resistor, reduces
conduction losses and provides higher efficiency at heavy
loads. Peak efficiency is about the same with either method.
∆IL =
The sense resistor values are:
( VIN(MAX) − VOUT ) • VOUT
For the boost controller, the maximum power loss in R1
will occur in continuous mode at VIN = 1/2 • VOUT:
∆IL =
⎛
1
V ⎞
VIN ⎜1− IN ⎟
( f) (L) ⎝ VOUT ⎠
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.3(IMAX). The maximum
∆IL occurs at the maximum input voltage for the bucks
and VIN = 1/2 • VOUT for the boost.
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LTC7813
Applications Information
The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit (30% for the boost) determined
by RSENSE. Lower inductor values (higher ∆IL) will cause
this to occur at lower load currents, which can cause a dip
in efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET Selection
Two external power MOSFETs must be selected for each
controller in the LTC7813: one N-channel MOSFET for the
top switch (main switch for the buck, synchronous for the
boost), and one N-channel MOSFET for the bottom switch
(main switch for the boost, synchronous for the buck).
The peak-to-peak drive levels are set by the DRVCC voltage. This voltage can range from 5V to 10V depending on
configuration of the DRVSET pin. Therefore, both logic-level
and standard-level threshold MOSFETs can be used in
most applications depending on the programmed DRVCC
voltage. Pay close attention to the BVDSS specification for
the MOSFETs as well.
The LTC7813’s unique ability to adjust the gate drive level
between 5V to 10V (OPTI-DRIVE) allows an application
circuit to be precisely optimized for efficiency. When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and
the input current decreases, then the efficiency has improved. If there is no change in input current, then there
is no change in efficiency.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Buck Main Switch Duty Cycle =
VOUT
VIN
Buck Sync Switch Duty Cycle =
VIN − VOUT
VIN
Boost Main Switch Duty Cycle =
VOUT − VIN
VOUT
Boost Sync Switch Duty Cycle =
VIN
VOUT
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21
LTC7813
Applications Information
The MOSFET power dissipations at maximum output
current are given by:
PMAIN _ BUCK =
VOUT
IOUT(MAX)
VIN
(
)
2
(1+ δ)RDS(ON) +
⎛ IOUT(MAX) ⎞
(VIN )2 ⎜
⎟(RDR )(CMILLER ) •
2
⎝
⎠
⎡
1 ⎤
1
+
⎢
⎥(f)
⎣ VDRVCC − VTHMIN VTHMIN ⎦
V −V
PSYNC _ BUCK = IN OUT IOUT(MAX)
VIN
(
PMAIN _ BOOST =
( VOUT − VIN ) VOUT
VIN2
Boost CIN, COUT Selection
)
2
(1+ δ)RDS(ON)
(IOUT(MAX) )
2
•
⎛ VOUT 3 ⎞⎛ IOUT(MAX) ⎞
⎟•
⎟⎜
2
⎝ VIN ⎠⎝
⎠
⎡
1
1 ⎤
+
(RDR ) (CMILLER ) • ⎢
⎥(f)
⎣ VDRVCC − VTHMIN VTHMIN ⎦
(1+ δ)RDS(ON) + ⎜
PSYNC _ BOOST =
VIN
IOUT(MAX)
VOUT
(
)
2
(1+ δ)RDS(ON)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the main N-channel
equations for the buck and boost controllers include an
additional term for transition losses, which are highest at
high input voltages for the buck and low input voltages
for the boost. For VIN < 20V (higher VIN for the boost)
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V (lower VIN for the boost)
the transition losses rapidly increase to the point that the
use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET
losses for the buck controller are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
22
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The input ripple current in a boost converter is relatively
low (compared with the output ripple current), because
this current is continuous. The boost input capacitor CIN
voltage rating should comfortably exceed the maximum
input voltage. Although ceramic capacitors can be relatively
tolerant of overvoltage conditions, aluminum electrolytic
capacitors are not. Be sure to characterize the input voltage
for any possible overvoltage transients that could apply
excess stress to the input capacitors.
The value of CIN is a function of the source impedance, and
in general, the higher the source impedance, the higher the
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
In a boost converter, the output has a discontinuous current,
so COUT must be capable of reducing the output voltage
ripple. The effects of ESR (equivalent series resistance)
and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage.
The steady ripple due to charging and discharging the
bulk capacitance is given by:
Ripple =
IOUT(MAX) • ( VOUT − VIN(MIN) )
COUT • VOUT • f
V
where COUT is the output filter capacitor.
The steady ripple due to the voltage drop across the ESR
is given by:
∆VESR = IL(MAX) • ESR
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic
and ceramic capacitors are all available in surface mount
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LTC7813
Applications Information
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings such as OS-CON and POSCAP.
where f is the operating frequency, COUT is the output
capacitance and ΔIL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage.
Buck CIN, COUT Selection
Setting Buck Output Voltage
The selection of CIN is usually based off the worst-case RMS
input current. The highest (VOUT)(IOUT) product needs to
be used in the formula shown in Equation 1 to determine
the maximum RMS capacitor current requirement.
The LTC7813 output voltage for the buck controller is set
by an external feedback resistor divider carefully placed
across the output, as shown in Figure 3. The regulated
output voltage is determined by:
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈
IMAX
VIN
⎡⎣( VOUT ) ( VIN – VOUT )⎤⎦1/2 (1)
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC7813, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC7813, is also
suggested. A small (≤10Ω) resistor placed between CIN
(C1) and the VIN pin provides further isolation.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (ΔVOUT) is approximated by:
∆VOUT
⎛
⎞
1
≈ ∆IL ⎜ESR +
⎟
8 • f • COUT ⎠
⎝
⎛ R ⎞
VOUT(BUCK) = 0.8V ⎜1+ B ⎟
⎝ RA ⎠
To improve the frequency response, a feedforward capacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
VOUT1
LTC7813
RB
CFF
VFB1
RA
7813 F03
Figure 3. Setting Buck Output Voltage
Setting Boost Output Voltage (VPRG2 Pin)
Through control of the VPRG2 pin, the boost controller
output voltage can be set by an external feedback resistor divider or programmed to a fixed 10V or 12V output.
Grounding VPRG2 allows the boost output voltage to be
set by an external feedback resistor divider placed across
the output, as shown in Figure 4a. The regulated output
voltage is determined by:
⎛ R ⎞
VOUT(BOOST) = 1.2V ⎜1+ B ⎟
⎝ RA ⎠
Tying the VPRG2 to INTVCC or floating it configures the
boost controller in fixed output voltage mode. Figure
4b shows how the VFB2 pin is used to sense the output
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23
LTC7813
Applications Information
voltage in this mode. Tying VPRG2 to INTVCC programs the
boost output to 12V, whereas floating VPRG2 programs
the output to 10V.
VBIAS
RB
LTC7813
RUN
RA
VOUT2
7813 F05
LTC7813
GND
RB
CFF
VPRG2 VFB2
The rising and falling UVLO thresholds are calculated using
the RUN pin thresholds and pull-up current:
RA
7813 F04a
(4a) Setting Boost Output Using External Resistors
LTC7813
INTVCC /FLOAT
VPRG2 VFB2
COUT
Figure 5. Using the RUN Pins as a UVLO
VOUT2
12V/10V
⎛ R ⎞
VUVLO(RISING) =1.275V ⎜1+ B ⎟ – 150nA •RB
⎝ RA ⎠
⎛ R ⎞
VUVLO(FALLING) =1.20V ⎜1+ B ⎟ – 150nA •RB
⎝ RA ⎠
7813 F04b
(4b) Setting Boost to Fixed 12V/10V Output
Figure 4. Setting Boost Output Voltage
RUN Pins
The LTC7813 is enabled using the RUN1 and RUN2 pins.
The RUN pins have a rising threshold of 1.275V with
75mV of hysteresis. Pulling a RUN pin below 1.2V shuts
down the main control loop for that channel. Pulling all
three RUN pins below 0.7V disables the controllers and
most internal circuits, including the DRVCC and INTVCC
LDOs. In this state, the LTC7813 draws only 3.6µA of
quiescent current.
Releasing a RUN pin allows a small 150nA internal current
to pull up the pin to enable that controller. Because of
condensation or other small board leakage pulling the pin
down, it is recommended the RUN pins be externally pulled
up or driven directly by logic. Each RUN pin can tolerate
up to 65V (absolute maximum), so it can be conveniently
tied to VBIAS in always-on applications where one or more
controllers are enabled continuously and never shut down.
The RUN pins can be implemented as a UVLO by connecting them to the output of an external resistor divider
network off VBIAS, as shown in Figure 5.
24
Tracking and Soft-Start (TRACK/SS1 and SS2 Pins)
The start-up of each VOUT is controlled by the voltage on
the TRACK/SS pin (TRACK/SS1 for channel 1, SS2 for
channel 2). When the voltage on the TRACK/SS pin is
less than the internal 0.8V reference (1.2V reference for
the boost channel), the LTC7813 regulates the VFB pin
voltage to the voltage on the TRACK/SS pin instead of
the internal reference. The TRACK/SS pin can be used to
program an external soft-start function or to allow VOUT
to track another supply during start-up.
Soft-start is enabled by simply connecting a capacitor
from the TRACK/SS pin to ground, as shown in Figure 6.
An internal 10μA current source charges the capacitor,
providing a linear ramping voltage at the TRACK/SS pin.
The LTC7813 will regulate its feedback voltage (and hence
VOUT) according to the voltage on the TRACK/SS pin, allowing VOUT to rise smoothly from 0V (VIN for the boost)
LTC7813
TRACK/SS
CSS
GND
7813 F06
Figure 6. Using the TRACK/SS Pin to Program Soft-Start
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to its final regulated value. The total soft-start time will
be approximately:
VX(MASTER)
tSS _ BOOST = CSS •
OUTPUT (VOUT)
0.8V
10µA
1.2V
10µA
Alternatively, the TRACK/SS1 pin for the buck controller can
be used to track another supply during start-up, as shown
qualitatively in Figures 7a and 7b. To do this, a resistor divider should be connected from the master supply (VX) to the
TRACK/SS pin of the slave supply (VOUT), as shown in
Figure 8. During start-up VOUT will track VX according to
the ratio set by the resistor divider:
R
+RTRACKB
VX
RA
=
• TRACKA
VOUT RTRACKA
RA +RB
VOUT(SLAVE)
TIME
7813 F07a
(7a) Coincident Tracking
VX(MASTER)
OUTPUT (VOUT)
tSS _ BUCK = CSS •
VOUT(SLAVE)
For coincident tracking (VOUT = VX during start-up),
RA = RTRACKA
TIME
RB = RTRACKB
(7b) Ratiometric Tracking
DRVCC and INTVCC Regulators (OPTI-DRIVE)
The LTC7813 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power
at the DRVCC pin from either the VBIAS supply pin or the
EXTVCC pin depending on the connections of the EXTVCC
and DRVSET pins. A third P-channel LDO supplies power
at the INTVCC pin from the DRVCC pin. DRVCC powers the
gate drivers whereas INTVCC powers much of the LTC7813’s
internal circuitry. The VBIAS LDO and the EXTVCC LDO
regulate DRVCC between 5V to 10V, depending on how
the DRVSET pin is set. Each of these LDOs can supply a
peak current of at least 50mA and must be bypassed to
ground with a minimum of 4.7μF ceramic capacitor. Good
bypassing is needed to supply the high transient currents
required by the MOSFET gate drivers and to prevent interaction between the channels. The INTVCC supply must
be bypassed with a 0.1μF ceramic capacitor.
7813 F07b
Figure 7. Two Different Modes of Output Voltage Tracking
VOUT
RB
VFB1
RA
VX
LTC7813
RTRACKB
TRACK/SS1
RTRACKA
3899 F09
Figure 8. Using the TRACK/SS1 Pin for Tracking
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LTC7813
Applications Information
The DRVSET pin programs the DRVCC supply voltage and
the DRVUV pin selects different DRVCC UVLO and EXTVCC
switchover threshold voltages. Table 1a summarizes the
different DRVSET pin configurations along with the voltage settings that go with each configuration. Table 1b
summarizes the different DRVUV pin settings. Tying the
DRVSET pin to INTVCC programs DRVCC to 10V. Tying the
DRVSET pin to GND programs DRVCC to 6V. By placing
a 50k to 100k resistor between DRVSET and GND the
DRVCC voltage can be programmed between 5V to 10V,
as shown in Figure 8.
Table 1a
DRVSET PIN
DRVCC VOLTAGE
GND
6V
INTVCC
10V
Resistor to GND 50k to 100k
5V to 10V
Table 1b
DRVUV PIN
DRVCC UVLO
RISING / FALLING
THRESHOLDS
EXTVCC SWITCHOVER
RISING/FALLING
THRESHOLD
0V
4.0V / 3.8V
4.7V / 4.45V
INTVCC
7.5V / 6.7V
7.7V / 7.45V
11
DRVCC VOLTAGE (V)
10
9
8
7
6
5
4
50 55 60 65 70 75 80 85 90 95 100
DRVSET PIN RESISTOR (kΩ)
7813 F09
Figure 9. Relationship Between DRVCC Voltage
and Resistor Value at DRVSET Pin
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maximum junction temperature rating for the LTC7813 to be
exceeded. The DRVCC current, which is dominated by the
gate charge current, may be supplied by either the VBIAS
26
LDO or the EXTVCC LDO. When the voltage on the EXTVCC
pin is less than its switchover threshold (4.7V or 7.7V as
determined by the DRVSET pin described above), the VBIAS
LDO is enabled. Power dissipation for the IC in this case
is highest and is equal to VBIAS • IDRVCC. The gate charge
current is dependent on operating frequency as discussed
in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given
in Note 2 of the Electrical Characteristics. For example,
using the LTC7813 in the QFN package, the DRVCC current
is limited to less than 21mA from a 60V supply when not
using the EXTVCC supply at a 70°C ambient temperature:
TJ = 70°C + (21mA)(60V)(44°C/W) = 125°C
To prevent the maximum junction temperature from being exceeded, the VBIAS supply current must be checked
while operating in forced continuous mode (PLLIN/MODE
= INTVCC) at maximum VBIAS.
When the voltage applied to EXTVCC rises above its
switch­over threshold, the VBIAS LDO is turned off and the
EXTVCC LDO is enabled. The EXTVCC LDO remains on as
long as the voltage applied to EXTVCC remains above the
switchover threshold minus the comparator hysteresis.
The EXTVCC LDO attempts to regulate the DRVCC voltage
to the voltage as programmed by the DRVSET pin, so while
EXTVCC is less than this voltage, the LDO is in dropout
and the DRVCC voltage is approximately equal to EXTVCC.
When EXTVCC is greater than the programmed voltage,
up to an absolute maximum of 14V, DRVCC is regulated
to the programmed voltage.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from the LTC7813’s buck
output (4.7V/7.7V ≤ VOUT ≤ 14V) during normal operation and from the VBIAS LDO when the output is out of
regulation (e.g., start-up, short circuit). If more current
is required through the EXTVCC LDO than is specified, an
external Schottky diode can be added between the EXTVCC
and DRVCC pins. In this case, do not apply more than 10V
to the EXTVCC pin and make sure that EXTVCC ≤ VBIAS.
Significant efficiency and thermal gains can be realized
by powering DRVCC from the output, since the VIN current resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
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For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (21mA)(8.5V)(44°C/W) = 78°C
However, for 3.3V and other low voltage outputs, additional
circuitry is required to derive DRVCC power from the output.
The following list summarizes the four possible connections for EXTVCC:
1. EXTVCC grounded. This will cause DRVCC to be powered
from the internal VBIAS regulator resulting in increased
power dissipation in the LTC7813 at high input voltages.
2. EXTVCC connected directly to the output of the buck
regulator. This is the normal connection for a 5V to
14V regulator and provides the highest efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements. Ensure that
EXTVCC ≤ VBIAS.
VBOOST = VIN + VDRVCC (VBOOST = VOUT + VDRVCC for the
boost controller). The value of the boost capacitor, CB,
needs to be 100 times that of the total input capacitance
of the topside MOSFET(s).
Fault Conditions: Buck Current Limit and
Current Foldback
The LTC7813 includes current foldback for the buck channel to help limit load current when the output is shorted to
ground. If the buck output voltage falls below 70% of its
nominal output level, then the maximum sense voltage is
progressively lowered from 100% to 40% of its maximum
selected value. Under short-circuit conditions with very
low duty cycles, the buck channel will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time, tON(MIN), of
the LTC7813 (≈80ns), the input voltage and inductor value:
⎛V ⎞
∆IL(SC) = tON(MIN) ⎜ IN ⎟
⎝ L ⎠
4. EXTVCC connected to an output-derived boost network
off of the buck regulator. For 3.3V and other low voltage regulators, efficiency gains can still be realized by
connecting EXTVCC to an output-derived voltage that
has been boosted to greater than 4.7V/7.7V. Ensure
that EXTVCC ≤ VBIAS.
The resulting average short-circuit current is:
Topside MOSFET Driver Supply (CB)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the buck regulator rises much higher than nominal levels. The crowbar
causes huge currents to flow, that blow the fuse to protect
against a shorted top MOSFET if the short occurs while
the controller is operating.
External bootstrap capacitors, CB, connected to the BOOST
pins supply the gate drive voltage for the topside MOSFET.
The LTC7813 features an internal switch between DRVCC
and the BOOST pin for each controller. These internal
switches eliminate the need for external bootstrap diodes
between DRVCC and BOOST. Capacitor CB in the Functional
Diagram is charged through this internal switch from DRVCC
when the SW pin is low. When the topside MOSFET is to
be turned on, the driver places the CB voltage across the
gate-source of the MOSFET. This enhances the top MOSFET switch and turns it on. The switch node voltage, SW,
rises to VIN and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
1
ISC = 40% •ILIM(MAX) − ∆IL(SC)
2
Fault Conditions: Buck Overvoltage Protection
(Crowbar)
A comparator monitors the buck output for overvoltage
conditions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if VOUT returns
to a safe level, normal operation automatically resumes.
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LTC7813
Applications Information
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip
(such as DRVCC short to ground), the overtemperature
shutdown circuitry will shut down the LTC7813. When the
junction temperature exceeds approximately 175°C, the
overtemperature circuitry disables the DRVCC LDO, causing
the DRVCC supply to collapse and effectively shutting down
the entire LTC7813 chip. Once the junction temperature
drops back to the approximately 155°C, the DRVCC LDO
turns back on. Long-term overstress (TJ > 125°C) should
be avoided as it can degrade the performance or shorten
the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC7813 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of TG1 and BG2 to be locked to the rising edge of
an external clock signal applied to the PLLIN/MODE pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
holds the voltage at the VCO input.
Note that the LTC7813 can only be synchronized to an
external clock whose frequency is within range of the
LTC7813’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Typically, the external clock (on the PLLIN/MODE pin)
input high threshold is 1.6V, while the input low threshold
is 1.1V. The LTC7813 is guaranteed to synchronize to an
external clock that swings up to at least 2.5V and down
to 0.5V or less.
Rapid phase locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the freerunning frequency be near the external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
1000
900
800
FREQUENCY (kHz)
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (kΩ)
7813 F10
Figure 10. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
28
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Applications Information
Table 2 summarizes the different states in which the FREQ
pin can be used.
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
Table 2
FREQ PIN
0V
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
INTVCC
DC Voltage
535kHz
Resistor to GND
DC Voltage
50kHz to 900kHz
Any of the Above
External Clock
75kHz to 850kHz
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest time duration
that the LTC7813 is capable of turning on the top MOSFET
(bottom MOSFET for the boost controller). It is determined
by internal timing delays and the gate charge required to
turn on the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
tON(MIN)_ BUCK <
VOUT
VIN (f)
tON(MIN)_ BOOST <
VOUT − VIN
VOUT (f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC7813 is approximately
80ns for the buck and 120ns for the boost. However, for
the buck channels as the peak sense voltage decreases
the minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC7813 circuits: 1) IC VBIAS current, 2) DRVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VBIAS current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
2. DRVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
from DRVCC to ground. The resulting dQ/dt is a current out of DRVCC that is typically much larger than the
control circuit current. In continuous mode, IGATECHG
= f(QT + QB), where QT and QB are the gate charges of
the topside and bottom side MOSFETs.
Supplying DRVCC from an output-derived source power
through EXTVCC will scale the VIN current required for
the driver and control circuits by a factor of (Duty Cycle)/
(Efficiency). For example, in a 20V to 5V application,
10mA of DRVCC current results in approximately 2.5mA
of VIN current. This reduces the midcurrent loss from
10% or more (if the driver was powered directly from
VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs
have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the
resistances of L, RSENSE and ESR to obtain I2R losses.
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LTC7813
Applications Information
For example, if each RDS(ON) = 30mΩ, RL = 50mΩ,
RSENSE = 10mΩ and RESR = 40mΩ (sum of both input
and output capacitance losses), then the total resistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
Efficiency varies as the inverse square of VOUT for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the top MOSFET(s) (bottom MOSFET for the boost), and become significant
only when operating at high input (output for the boost)
voltages (typically 20V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) • VIN 2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5%
to 10% efficiency degradation in portable systems. It
is very important to include these system level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at
the switching frequency. A 25W supply will typically
require a minimum of 20μF to 40μF of capacitance
having a maximum of 20mΩ to 50mΩ of ESR. Other
losses including Schottky conduction losses during
dead-time and inductor core losses generally account
for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot
30
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response to
be optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC-coupled and AC-filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin. The
ITH external components shown in Figure 12 circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
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A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise-time
should be controlled so that the load rise-time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
As a design example for the buck channel, assume VIN =
12V (nominal), VIN = 22V (maximum), VOUT = 3.3V, IMAX
= 5A, VSENSE(MAX) = 75mV and f = 350kHz. The inductance value is chosen first based on a 30% ripple current
assumption. The highest value of ripple current occurs
at the maximum input voltage. Tie the FREQ pin to GND,
generating 350kHz operation. The minimum inductance
for 30% ripple current is:
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 80ns is not violated. The minimum on-time occurs at
maximum VIN:
VIN(MAX) ( f)
=
3.3V
= 429ns
22V (350kHz )
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (65mV):
RSENSE ≤
3.3V
(5A )2 ⎡⎣1+ (0.005) (50°C − 25°C)⎤⎦
22V
5A
(0.035Ω) + (22V )2 (2.5Ω) (215pF ) •
2
⎡
⎤
1
1
⎢⎣ 6V − 2.3V + 2.3V ⎥⎦(350kHz ) = 308mW
ISC =
34mV 1 ⎛ 80ns (22V ) ⎞
− ⎜
⎟ = 3.21A
0.01Ω 2 ⎝ 4.7µH ⎠
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC = (3.21A)2 (1.125) (0.022Ω) = 255mW
which is less than under full-load conditions.
VOUT ⎛
VOUT ⎞
⎜
⎟
∆IL =
1−
( f) (L) ⎜⎝ VIN(NOM) ⎟⎠
VOUT
PMAIN =
A short-circuit to ground will result in a folded back current of:
Buck Design Example
tON(MIN) =
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF.
At maximum input voltage with T(estimated) = 50°C:
65mV
≈ 0.01Ω
5.73A
Choosing 1% resistors: RA = 25k and RB = 78.7k yields
an output voltage of 3.32V.
CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
VO(RIPPLE) = RESR (∆IL) = 0.02Ω (1.45A) = 29mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. Figure 11 illustrates the current waveforms present in
the various branches of the synchronous boost and buck
regulators operating in the continuous mode. Check the
following in your layout:
1. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
CDRVCC must return to the combined COUT (–) terminals.
The path formed by the top N-channel MOSFET, bottom
N-channel MOSFET, and the CIN capacitor should have
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LTC7813
Applications Information
short leads and PC trace lengths. The output capacitor
(–) terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
MOSFET loop described above.
2. Does the LTC7813 VFB pins’ resistive divider connect to
the (+) terminal of COUT? The resistive divider must be
connected between the (+) terminal of COUT and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
3. Are the SENSE– and SENSE+ leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE+ and SENSE– should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the SENSE resistor.
4. Is the DRVCC and decoupling capacitor connected close
to the IC, between the DRVCC and the ground pin? This
capacitor carries the MOSFET drivers’ current peaks.
5. Keep the switching nodes (SW1, SW2), top gate (TG1,
TG2), and boost nodes (BOOST1, BOOST2) away from
sensitive small-signal nodes, especially from the other
channel’s voltage and current sensing feedback pins. All
of these nodes have very large and fast moving signals
and therefore should be kept on the output side of the
LTC7813 and occupy minimum PC trace area.
6. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the DRVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
PC Board Layout Debugging
Start with one controller at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output voltage
as well. Check for proper performance over the operating
voltage and current range expected in the application. The
frequency of operation should be maintained over the input
voltage range down to dropout and until the output load
32
drops below the low current operation threshold—typically 25% of the maximum designed current level in Burst
Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Only after
each controller is checked for its individual performance
should both should multiple controllers be turned on at
the same time.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher output currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, Schottky and the top
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
For more information www.linear.com/LTC7813
7813f
LTC7813
Applications Information
RSENSE2
VIN
L2
SW2
VOUT2
RIN
COUT2
RL2
V
7813 F11a
BOLD LINES INDICATE HIGH SWITCHING CURRENT.
KEEP LINES TO A MINIMUM LENGTH.
(a) Boost Regulator
SW1
VIN
RIN
L1
CIN
RSENSE1
VOUT1
COUT1
RL1
7813 F11b
BOLD LINES INDICATE HIGH SWITCHING
CURRENT. KEEP LINES TO A MINIMUM LENGTH.
(b) Buck Regulator
Figure 11. Branch Current Waveforms
7813f
For more information www.linear.com/LTC7813
33
LTC7813
Applications Information
Compensation and VMID Capacitance in a Cascaded
Boost+Buck Regulator
Choosing the VMID Voltage in Cascaded Boost+Buck
Regulator
When using the LTC7813 as a cascaded Boost+Buck
regulator, the boost and buck regulator control loops are
compensated individually. While this may seem more
complicated, this is actually advantageous, as the inherently fast buck loop can be designed to handle the output
load transient, while the boost loop is less important and
can be slower.
There are many performance trade-offs when considering
where to set the VMID (boost output) regulation voltage
(VMID_REG) relative to the input voltage (VIN) range and
output (buck) regulation voltage (VOUT_REG). These tradeoffs include efficiency, quiescent current, switching noise/
EMI, and voltage ripple.
The amount of capacitance needed on the intermediate VMID
node (boost output) and the buck output VOUT depends on
a number of factors, including the input voltage, output
voltage, load current and the nature of any transients,
and the mode of operation (Burst Mode operation, forced
continuous mode, or pulse-skipping mode).
In general, the buck regulator should be designed to
handle any output load transients and provide sufficiently
low output ripple.
The boost regulator does not need to respond as fast, as
the VMID node can tolerate relatively high ripple and/or
transient dips and therefore does not necessarily need a
lot of capacitance. The VMID node capacitance needs to
be able to handle the input ripple current from the buck
regulator. It also needs to be large enough that the boost
regulator’s voltage ripple and/or transient dips do not appear as significant input line steps to the buck regulator
and feed through to the buck regulator’s output.
The ripple on the VMID node is higher in Burst Mode operation and pulse-skipping mode than in forced continuous
mode, especially at light loads and/or if the input voltage
is slightly below the regulated boost output (VMID) voltage.
Thus, Burst Mode operation and pulse-skipping mode
generally require more VMID capacitance than in forced
continuous mode to maintain a similar amount of ripple.
The capacitance on the VMID node can be all ceramic, or
some combination of ceramic and polarized (tantalum,
electrolytic, etc.) capacitors.
34
Remember that VMID will follow VIN if VIN > VMID_REG
(see the Boost Controller Operation When VIN > VOUT
section in the Operation section). If VIN < VMID_REG, VMID
is regulated to VMID_REG.
Consider as an example an automotive application that
requires a regulated 12V output voltage generated from a
vehicle battery. The battery spends most of its operating
lifetime in a normal range of 10V to 16V, but may dip to
as low as 2.5V during engine start and rise as high as 38V
during high voltage transients.
We can designate the minimum normal operating voltage
as VIN_MIN_OP = 10V, and the maximum normal operating
voltage as VIN_MAX_OP = 16V. So what voltage should we
choose for VMID_REG?
REGULATED OUTPUT VOLTAGE
In this example, note that we want a tightly regulated output
(VOUT_REG =12V), which is within our normal operating
range (VIN_MIN_OP < VOUT_REG < VIN_MAX_OP). We want
VMID_REG > VOUT_REG to provide headroom for the buck
regulator, but we have a choice of whether to set VMID_REG
above or below VIN_MAX_OP.
OPTION A: V MID_REG > VOUT_REG and VMID_REG >
VIN_MAX_OP
In this option, we set VMID_REG > VIN_MAX_OP (e.g.,
VMID_REG =18V). Both the boost regulator and the buck
regulator are switching (at full, constant frequency if in
forced continuous mode) over the full 10V to 16V normal operating range. Since the boost regulator is always
switching, the efficiency is lower and the input ripple and
EMI, while predictable and still low, are higher than other
potential options.
7813f
For more information www.linear.com/LTC7813
LTC7813
Applications Information
OPTION B: VIN_MIN_OP < VOUT_REG < VMID_REG < VIN_MAX_OP
This is similar to option A, but VMID_REG is set within
the normal operating input voltage range (e.g., VMID_REG
=14V). When VIN is well below VMID_REG, this option is
like Option A. But as VIN approaches VMID_REG, the boost
controller will gradually begin skipping cycles (even in
forced continuous mode) once it reaches minimum-ontime. If VIN > VMID_REG, then VMID follows VIN. In this
region, OPTION B is more efficient than OPTION A since
the boost is not switching. But this is at the expense of
the cycle-skipping (non-constant frequency ripple) when
VIN is slightly below VMID_REG.
LOOSELY REGULATED OUTPUT (Pass-Through Regulator)
In some applications, it is not critical that VOUT be tightly
regulated, but rather that it remains within a certain voltage
range. Suppose, in our example, that it is only important
that VOUT be maintained within the normal battery operating
voltage range of 10V to 16V. We can consider a third option:
OPTION C: VMID_REG = VIN_MIN_OP and VOUT_REG =
VIN_MAX_OP
Here we set VMID_REG = VIN_MIN_OP =10V and VOUT_REG
= VIN_MAX_OP =16V. So the boost regulator only boosts
when VIN < 10V and the buck regulator only bucks when
VIN >16V. When VIN is between 10V to 16V, the circuit is
in a “pass-through” or “wire” mode where there is very
little switching. The boost regulator is not boosting (TG2
is on 100% in forced continuous mode) and the buck
regulator is operating in dropout (with TG1 on at an effec-
tive 99%duty cycle). This makes the circuit very efficient,
especially at heavy loads, with extremely low input and
output ripple and EMI. Note that in this pass-through mode,
the circuit does not benefit from the LTC7813’s ultralow
quiescent current of 33µA in Burst Mode operation since
the buck regulator does not go to sleep because VOUT <
VOUT_REG =16V.
REGULATED OUTPUT VOLTAGE BELOW NORMAL INPUT
VOLTAGE OPERATING RANGE
In some applications, the desired output voltage might
be less than the minimum normal operating voltage, but
still higher than the worst case minimum input voltage.
Consider our previous example, but instead suppose we
want VOUT = 5V. In this case, we can set our VMID_REG
such that:
OPTION D: VIN_MIN_OP > VMID_REG > VOUT_REG
So we might set VMID_REG just below 10V, so that the
boost regulator never switches within the normal operating
range and only needs to boost during the input voltage
dips below 10V.
The buck controller always regulates the VOUT to 5V, and
the boost regulator’s inductor and VMID capacitance create a filter that substantially reduces any input ripple and
results in very little conducted EMI on the input.
Table 3 summarizes some of the performance trade-offs
of these four potential ways to set the VMID regulation
voltage in an LTC7813 cascaded Boost+Buck regulator.
7813f
For more information www.linear.com/LTC7813
35
LTC7813
Applications Information
Table 3. Summary of Trade-Offs in Choosing the VMID Regulation Voltage in a Cascaded Boost+Buck Regulator
A
B
C
D
Option
VMID_REG > VOUT_REG and
VMID_REG > VIN_MAX_OP
VIN_MIN_OP < VOUT_REG <
VMID_REG < VIN_MAX_OP
Example for Normal Input Operating
Range of 10V to 16V (VIN_MIN_OP =
10V, VIN_MAX_OP = 16V) with a Full
Range of 2.5V to 38V
VMID_REG =18V
VOUT = VOUT_REG = 12V
VMID_REG = 14V
VOUT = VOUT_REG = 12V
VMID_REG =10V
VOUT_REG = 16V
VOUT = 10V to 16V
VMID_REG =10V
VOUT = VOUT_REG = 5V
Boost Boosting in Normal Operating
Range?
Yes, Over Full Range
Yes, When VIN < VMID_REG
No
No
Buck Bucking in Normal Operating
Range?
Yes, Over Full Range
Yes, Over Full Range
No, in Dropout
Yes, Over Full Range
LTC7813 No Load Quiescent Current in
Burst Mode
34µA
34µA
~3mA
34µA
Heavy Load Efficiency
Slightly Lower
High When Not Boosting;
Slightly Lower When
Boosting
Highest
High
Input Ripple
Low
Low When Boosting; Very
Low When Not Boosting;
Some Cycle-Skipping
During Transition
Extremely Low
Very Low
VMID_REG = VIN_MIN_OP and VIN_MIN_OP > VMID_REG >
VOUT_REG = VIN_MAX_OP
VOUT_REG
(Pass-Through/Wire Mode)
Output Ripple
Low
Low
Extremely Low
Low
EMI in Normal Operating Range
Low
Very Low When Not
Boosting; Low When
Boosting
Extremely Low
Very Low
Example for Normal Operating Range:
VIN_MIN_OP = 10V – VIN_MAX_OP = 16V
VMID_REG =18V
VOUT = VOUT_REG = 12V
VMID_REG =14V
VOUT = VOUT_REG = 12V
VMID_REG =10V
VOUT_REG = 16V
VOUT = 10V to 16V
VMID_REG =10V
VOUT = VOUT_REG = 5V
36
7813f
For more information www.linear.com/LTC7813
CIN1
33µF
VIN
1000pF
L2
11µH
For more information www.linear.com/LTC7813
100pF
6.8nF
1.86k
ITH2
TG2
CB2
0.1µF
SW2 BOOST2
MBOT2
CMID1,2,3
6.8µF
CSS1
0.1µF
VFB2
CMID4
33µF
VBIAS
RA2
46.4k
RB2
499k
TG1
MTOP1
BOOST1
CSS2
0.1µF
4.7µF
ILIM
RSENSE1
3m
EXTVCC
VFB1
7813 F12
RA1
35.7k
RB1
499k
COUT1
22µF
VOUT
12V
COUT2,3 8A*
47µF
* WHEN VIN <8V MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
**VMID = 14V WHEN VIN < 14V
VMID FOLLOWS VIN WHEN VIN > 14V
0.1µF
INTVCC DRVUV DRVSET
SENSE1+ SENSE1–
L1
4.7µH
SW1 BG1
CB1
0.1µF
MBOT1
FREQ PLLIN/MODE GND VPRG2 DRVCC
LTC7813
VMID, 14V**
TRACK/SS1 SS2
820pF
MTOP2
Figure 12. Wide Input Range to 12V/8A Low IQ Cascaded Boost+Buck Regulator (VMID = 14V)
4.7nF
15k
RUN1 RUN2 ITH1
SENSE2+ SENSE2– BG2
CIN2,3,4
6.8µF
RSENSE2
2m
MTOP1, MTOP2, MBOT1, MBOT2: INFINEON BSC027N04LS
L1: WÜRTH 7443320100
L2: WÜRTH 7443320470
CIN1, CMID5: KEMET T521X336M050ATE075
COUT3: KEMET T521V476M020ATE055
VIN
8V TO 38V
DOWN TO
2.2V AFTER
START-UP
LTC7813
Typical Applications
7813f
37
38
CIN1,2
33µF
VIN
1000pF
L2
15µH
For more information www.linear.com/LTC7813
100pF
10nF
3.6k
ITH2
TG2
CB2
0.1µF
SW2 BOOST2
MBOT2
CSS1
0.1µF
VBIAS
TG1
MTOP1
BOOST1
CSS2
0.1µF
37.4k
4.7µF
RSENSE1
6m
EXTVCC
VFB1
0.1µF
INTVCC ILIM DRVUV DRVSET
SENSE1+ SENSE1–
L1
3.3µH
SW1 BG1
CB1
0.1µF
MBOT1
FREQ PLLIN/MODE GND VPRG2 DRVCC
LTC7813
VFB2
CMID7
33µF
CMID1,2,3,4,5,6
2.2µF
VMID, 10V*
TRACK/SS1 SS2
820pF
MTOP2
RA1
68.1k
RB1
357k
COUT1,2
47µF
COUT3
220µF
*VMID = 10V WHEN VIN < 10V
VMID FOLLOWS VIN WHEN VIN > 10V
7813 F13
Figure 13. Wide Input Range to 5V/8A Low IQ Cascaded Boost+Buck Regulator (VMID Boosted to 10V)
2.2nF
12.7k
RUN1 RUN2 ITH1
SENSE2+ SENSE2– BG2
CIN3,4
2.2µF
RSENSE2
3m
MTOP1: INFINEON BSC057N08NS3
MBOT1: INFINEON BSC036NE7NS3
MTOP2, MBOT2: INFINEON BSC042NE7NS3
L1: WÜRTH 744325330
L2: WÜRTH 744325120
CIN1,2, CMID7: SUNCON 63HVP33M
COUT3: SANYO 6TPB220ML
VIN
8V TO 60V
DOWN TO
2.2V AFTER
START-UP
VOUT
5V
8A
LTC7813
Typical Applications
7813f
LTC7813
Typical Applications
Figure 14. High Efficiency 12V to 60V VIN to 24V/5A and 3.3V/8A DC/DC Regulator
VIN
C14
1500pF
RUN1
TG2
R6
10k
C13
100pF
RUN2
CB2
0.1µF
BOOST2
ITH1
L2
15µH
SW2
LTC7813
C16
4.7nF
R7
4.3k
C15
220pF
ITH2
CSS2
0.1µF
RB2
232k
VFB2
RA2
12.1k
V BIAS
MTOP1
TG1
CB1
0.1µF
PLLIN/MODE
GND
BOOST1
L1
22µH
SW1
C19
4.7µF
CIN1
33µF
C1
1000pF
TRACK/SS1
FREQ
CIN2,3,4
2.2µF
VIN
12V TO 60V
SENSE2–
SENSE2–
SS2
COUT10
33µF
RSENSE2
6m
MBOT2
BG2
CSS1
0.1µF
C8
0.1µF
COUT4,5,6,7,8,9
2.2µF
MTOP2
VOUT2
24V*
5A
RSENSE1
8m
VPRG2
BG1
MBOT1
COUT1,2
47µF
COUT3
220µF
VOUT1
3.3V
8A
DRVCC
SENSE1+
INTVCC
SENSE1–
ILIM
RB1
215k
DRVUV
VFB1
DRVSET
EXTVCC
RA1
68.1k
*VOUT2 = 24V WHEN VIN < 24V
VOUT2 FOLLOWS VIN WHEN VIN > 24V
MTOP1: INFINEON BSC057N08NS3
MBOT1: INFINEON BSC036NE7NS3
MTOP2, MBOT2: INFINEON BSC042NE7NS3
L1: WÜRTH 744325240
L2: WÜRTH 7443551370
CIN1, COUT10: SUNCON 63HVP33M
COUT3: SANYO 6TPB220ML
7813 F14
7813f
For more information www.linear.com/LTC7813
39
VIN
4V TO 56V
DOWN TO
2.2V AFTER
START-UP
40
VIN
1000pF
L2
15µH
For more information www.linear.com/LTC7813
68pF
27nF
3.6k
ITH2
TG2
CB2
0.1µF
SW2 BOOST2
MBOT2
CMID1,2,3
4.7µF
CSS1
0.22µF
VBIAS
RA2
14.7k
RB2
332k
TG1
MTOP1
BOOST1
CSS2
0.1µF
37.4k
L1
22µH
4.7µF
RSENSE1
8m
90.9k
VFB1
7813 F15
33pF
RA1
11.5k
RB1
332k
COUT1
10µF
COUT2,3
68µF
VOUT
24V
5A*
* WHEN VIN <12V MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED
**VMID = 28V WHEN VIN < 28V
VMID FOLLOWS VIN WHEN VIN > 28V
0.1µF
INTVCC ILIM DRVUV
SENSE1+ SENSE1–
DRVSET
SW1 BG1
CB1
0.1µF
MBOT1
FREQ PLLIN/MODE GND VPRG2 DRVCC
LTC7813
VFB2
CMID4,5
33µF
VMID, 28V**
TRACK/SS1 SS2
820pF
MTOP2
Figure 15. Wide Input Range to 24V/5A Low IQ Cascaded Boost + Buck Regulator (VMID = 28V)
4.7nF
26.1k
RUN1 RUN2 ITH1
SENSE2+ SENSE2– BG2
CIN2,3,4
4.7µF
MTOP1: INFINEON BSC123N08NS3
MBOT1: INFINEON BSC042NE7NS3
MTOP2: INFINEON BSC026N08NS3
MBOT2: INFINEON BSC072N08NS3
L1: COILCRAFT SER1390-473
L2: COILCRAFT XAL1510-153
CIN1, CMID4,5: SUNCON 63HVH33M
COUT2,3: SUNCON 35CE68LX
CIN1
33µF
RSENSE2
6m
LTC7813
Typical Applications
7813f
LTC7813
Package Description
Please refer to http://www.linear.com/product/LTC7813#packaging for the most recent package drawings.
UH Package
32-Lead Plastic
QFN (5mm × 5mm)
UH Package
(Reference
LTC DWG
# 05-08-1693
Rev D)
32-Lead Plastic
QFN
(5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 ±0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.50 REF
(4-SIDES)
3.45 ±0.10
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ±0.05
0.50 BSC
7813f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC7813
41
LTC7813
Typical Application
Low EMI, Wide Input Range Pass-Through Cascaded Boost+Buck Regulator
L2
4.7µH
VIN
4V TO 56V
DOWN TO
2.2V AFTER
START-UP
CIN1
47µF
MTOP2
CIN2,3,4
2.2µF
CMID4
47µF
MBOT2
2.05k
3.01k
L1
7.3µH
MTOP1
VMID, 20V**
RB2
499k
COUT1
6.7µF
MBOT1
3.01k
RA2
31.6k
CMID1,2,3
2.2µF
1000pF
SENSE2+ SENSE2– BG2
SW2 BOOST2
RA1
12.7k
CB1
0.1µF
TG2
VFB2
VBIAS
TG1
BOOST1
SW1 BG1
VOUT
20V TO 32V
5A*
RB1
499k
1000pF
CB2
0.1µF
COUT2,3
56µF
SENSE1+ SENSE1–
VFB1
LTC7813
RUN1 RUN2 ITH1
ITH2
TRACK/SS1 SS2
VIN
26.1k
MTOP1: INFINEON BSC123N08NS3
MTOP2, MBOT1, MBOT2: INFINEON BSC047N08NS3
L1: WÜRTH 7443551470
L2: WÜRTH 7443551730
CIN1, CMID4: SUNCON 63HVH47M
COUT3: SUNCON 50HVH56M
CSS1
0.1µF
2.94k
820pF
100pF
2200pF
FREQ PLLIN/MODE GND VPRG2 DRVCC
10nF
4.7µF
CSS2
0.1µF
INTVCC ILIM DRVUV DRVSET
0.1µF
7813 TA02
* WHEN VIN < 12V MAXIMUM LOAD CURRENT
AVAILABLE IS REDUCED
** VMID = 20V WHEN VIN < 20V
VMID FOLLOWS VIN WHEN VIN > 20V
VOUT = 20V WHEN VIN < 20V
VOUT = 32V WHEN VIN > 32V
VOUT FOLLOWS VIN WHEN VIN IS 20V TO 32V
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC7812
38V Synchronous Boost+Buck Controller with Low EMI
and Low Input/Output Ripple
4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, Boost VOUT Up to 60V,
0.8V ≤ Buck VOUT ≤ 24V, IQ = 33µA, 5mm × 5mm QFN-32
LTM®4609
36VIN, 34VOUT, Buck-Boost µModule Regulator
4.5V≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 34V, Up to 4A 15mm × 15mm LGA and
BGA Packages
LTM8056
58VIN, 48VOUT, Buck-Boost µModule Regulator
5V≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V, Up to 5.4A 15mm × 15mm × 4.92mm
BGA Package
LTC3789
High Efficiency (Up to 98%) Synchronous 4-Switch
Buck-Boost DC/DC Controller
4V≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm × 5mm QFN-28
LT®3790
60V 4-Switch Synchronous Buck-Boost Controller
4.7V ≤ VIN ≤ 60V, 1.2V ≤ VOUT ≤ 60V, TSSOP-38
LT8705
80V VIN and VOUT Synchronous 4-Switch Buck-Boost
DC/DC Controller
2.8V ≤ VIN ≤ 80V, 1.3V ≤ VOUT ≤ 80V, Regulates VOUT, IOUT, VIN, IIN,
5mm × 7mm QFN-38, Modified TSSOP Package for High Voltage
LTC3769
Low IQ, 60V Synchronous Step-Up DC/DC Controller
4.5V (Down to 2.3V After Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, IQ = 28µA
PLL Fixed Frequency 50kHz to 900kHz, 4mm × 4mm QFN-24, TSSOP-20E
LTC3891
Low IQ, 60V Synchronous Step-Down Controller with
99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V,
IQ = 50µA
LTC3859AL
38V Low IQ Triple Output, Buck/Buck/Boost Synchronous
Controller with 28μA Burst Mode IQ
4.5V(Down to 2.5V after Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V,
Buck VOUT Range: 0.8V to 24V
LTC3899
60V, Triple Output, Buck/Buck/Boost Synchronous
Controller with 29µA Burst Mode IQ
4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V,
Buck VOUT Range: 0.8V to 60V
LTC3892/
LTC3892-1/
LTC3892-2
60V Low IQ, Dual, 2-Phase Synchronous Step-Down
DC/DC Controller with 29µA Burst Mode IQ
4.5V≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 0.99VIN, 5mm × 5mm QFN-32,
TSSOP-28 Packages
42 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC7813
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC7813
7813f
LT 0316 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2016