[AKD4114-B] AKD4114-B AK4114 Evaluation Board Rev.0 GENERAL DESCRIPTION AKD4114-B is the evaluation board for AK4114, 192kHz digital audio transceiver. This board has optical and BNC connector to interface with other digital audio equipment. Ordering guide AKD4114-B --- Evaluation board for AK4114 (A cable for connecting with printer port of IBM-AT compatible PC and a control software are packed with this. The control software does not operate on Windows NT.) FUNCTION Digital interface -S/PDIF : 8 channel input (optical or BNC) 2 channel output (optical or BNC ) - Serial audio data I/F : 1 input/output (for DIR deta output/DIT data input. 10-pin port) -B,C,U,V bit : 1 input/output port (10-pin port) -Serial control data I/F 1 input/output port (10-pin port) 5V GND REG Control 3.3V Opt RX0 RX1 RX7 TX0 AK4114 Opt TX1 B,C,U,V Serial Data out (For DIR) Figure 1. AKD4114-B Block Diagram *Circuit diagram and PCB layout are attached at the end of this manual. [KM076604] -1- 2009/08 [AKD4114-B] Evaluation Board Manual Operating sequence (1) Set up the power supply lines. [+ 5V] (Red) = 5V [GND] (Black) = 0V Each supply line should be distributed from the power supply unit. (2) Set up the evaluation mode and jumper pins. (Refer to the following item.) (3) Connect cables. (Refer to the following item.) (4) Power on. The AK4114 should be reset once bringing PDN(SW2) “L” upon power-up. Evaluation modes (1) Evaluation for DIR (Default) S/PDIF in (optical or BNC) – AK4114 – Serial Data out (10pin port) S/PDIF Optical, XLR or BNC connector AK4114 (DIR) MCLK BICK LRCK SDTO PORT2 (10pin Header) MCLK BICK LRCK SDTO DAC AKD4114-B The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector(PORT1: TORX176) or BNC connector. The AKD4114-B can be connected with the AKM’s DAC evaluation board via 10-line cable. a. Set-up of Bi-phase Input RX0 and RX1-7 should not select BNC at the same time. a-1. RX0 Connector Optical (PORT1) BNC (J2) JP2(RXP0) JP3(RXN0) OPT BNC BNC BNC Table 1. Set-up of RX0 a-2. RX1, 2, 3, 4, 5, 6, and 7 can be inputted from a BNC (J2) connector only. Only RX1, RX2 and RX 3 can be used in parallel mode. The jumper which selects the Rx channel should be Short. Input JP [KM076604] RX1 JP4 Short RX2 JP5 Short RX3 JP6 Short Table 2. Set-up of RX4 RX5 RX6 JP7 JP8 JP9 RX4 RX5 RX6 RX1, 2, 3, 4, 5, 6 and 7 -2- RX7 JP10 RX7 2009/08 [AKD4114-B] a-3. Set-up of AK4114 input path It sets up by SW 1_1 and SW 1_5 in parallel mode. Please set up IPS2-0 bits in serial mode. IPS1 pin IPS0 pin (SW1_5) (SW1_1) INPUT Data IPS2 bit IPS1 bit IPS0 bit 0 0 0 RX0 0 0 1 RX1 0 1 0 RX2 0 1 1 RX3 1 0 0 RX4 1 0 1 RX5 1 1 0 RX6 1 1 1 RX7 (In parallel mode, IPS2 is fixed to “0”) Table 3. Recovery Data Select - b. Default Set-up of clock input and output SDTO DAUX GND GND BICK LRCK GND 10 GND 1 GND PORT2 DIR MCLK The signal level outputted/inputted from PORT2 is 3.3V. 5 6 Figure 2. PORT2 pin layout b-1. MCKO1/MCKO2 The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2 is selected by OCKS 1-0. Output JP12 signal Default MCKO1 MCKO1 MCKO2 MCKO2 Table 4. Set-up of MCKO1/MCKO2 OCKS1 pin (SW3_2) OCKS1 bit 0 0 1 1 [KM076604] OCKS0 pin (SW3_3) OCKS0 bit (X’tal) MCKO1 0 256fs 256fs 1 256fs 256fs 0 512fs 512fs 1 128fs 128fs Table 5. Master Clock Frequency Select -3- MCKO2 fs (max) 256fs 128fs 256fs 64fs 96 kHz 96 kHz 48 kHz 192 kHz Default 2009/08 [AKD4114-B] b-2. Set-up of input/output of BICK and LRCK Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4114 (Refer to Table 7). Audio format SW3_7 (DIR_I/O) Slave mode 0 Master mode 1 Table 6. Set-up of DIR_I/O c. Default Set-up of Audio format It sets up by SW 1_2, SW 1_3 and SW1_4 in parallel mode. Please set up DIF2-0 bit in serial mode. DIF2 pin (SW1_4) DIF2 bit DIF1 pin (SW1_3) DIF1 bit 0 0 0 1 0 0 2 0 1 3 0 1 4 1 0 5 1 0 6 1 1 7 1 1 Mode d. DIF0 pin (SW1_2) DIF0 bit DAUX LRCK SDTO BICK I/O 24bit, Left justified 24bit, Left 1 justified 24bit, Left 0 justified 24bit, Left 1 justified 24bit, Left 0 justified 1 24bit, I2S 24bit, Left 0 justified 1 24bit, I2S Table 7. Audio format 0 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, I2S 24bit, Left justified 24bit, I2S I/O H/L O 64fs O H/L O 64fs O H/L O 64fs O H/L O 64fs O H/L O 64fs O L/H O 64fs O H/L I 64-128fs I L/H I 64-128fs I Default Set-up of CM1 and CM0 The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_1 and JP18. In serial mode, it can be selected by CM1-0 bits. CM1 pin (SW3_1) CM1 bit CM0 pin (JP18) (UNLOCK) PLL X'tal Clock source SDTO source 0 1 ON OFF ON ON ON(Note) ON ON ON PLL(RX) X'tal PLL(RX) X'tal RX DAUX RX DAUX CM0 bit 0 0 0 (CM0) 1 (CDTO/CM0=H) 1 0 (CM0) Default 1 1 (CDTO/CM0=H) ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF. Table 8. Clock Operation Mode Select [KM076604] -4- 2009/08 [AKD4114-B] (2) Evaluation for DIT Serial Data in(10pin port) – AK4114 – S/PDIF out(optical or BNC) MCLK BICK LRCK ADC DAUX * PORT2 (10pin Header) MCLK BICK LRCK DAUX Optical, XLR or BNC connector AK4114 (DIT) S/PDIF * Input to the fifth pin. AKD4114-B MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT2: DIR). a. Set-up of a Bi-phase output signal TX0 and TX1 should not select an optical connector or a BNC connector at the same time. a-1. The data outputted from TX1 can be selected by OPS12-10 bit. Connector JP19 (TX1) Optical (PORT4) OPT BNC (J4) BNC Table 9. Set-up of TX1 JP14 (TX1) BNC BNC a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In serial mode, it can be selected by OPS02-00 bits. Connector Optical (PORT4) BNC (J4) JP13 (TX0) JP19 (TXP1) OPT Open BNC Open Table 10. Set-up of TX0 JP14 (TXN1) BNC BNC b.Set-up of clock input and output SDTO DAUX GND GND BICK LRCK GND 10 GND 1 GND PORT2 DIR MCLK The used signals are MCLK, LRCK, BICK, and DAUX. The signal level outputted and inputted from PORT2 is 3.3V. 5 6 Figure 3. PORT2 pin layout Clock MCLK BICK LRCK DAUX [KM076604] PORT I/O PORT2 OUT PORT2 IN / OUT PORT2 IN / OUT PORT2 IN Table 11. Clock input/output -5- 2009/08 [AKD4114-B] b-1. MCKO1/MCKO2 The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2 sets up by OCKS 1-0. Output signal MCKO1 MCKO2 JP12 Default MCKO1 MCKO2 Table 12. Selection of MCKO1/MCKO2 OCKS1 pin (SW3_2) OCKS1 bit OCKS0 pin (SW3_3) OCKS0 bit 0 0 1 1 (X’tal) MCKO1 MCKO2 0 256fs 256fs 1 256fs 256fs 0 512fs 512fs 1 128fs 128fs Table 13. Master Clock Frequency Select 256fs 128fs 256fs 64fs fs (max) 96 kHz 96 kHz 48 kHz 192 kHz Default b-2. Set-up of input/output of BICK and LRCK Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4114 (Refer to Table 20). JP16 and 17 should be fixed to the “DC” side. Audio format SW3_8 (DIT_I/O) Slave mode 0 Master mode 1 Table 14. Set-up of DIT_I/O c. Default Set-up of audio data format Please refer to Table 7. d. Set-up of CM1 and CM0 CM1 pin (SW3_1) CM1 bit CM0 pin (JP18) CM0 bit 0 0 0 1 1 0 1 1 (UNLOCK) PLL X'tal Clock source SDTO source 0 1 ON OFF ON ON ON(Note) ON ON ON PLL(RX) X'tal PLL(RX) X'tal RX DAUX RX DAUX Default ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-Down) Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF. Table 15. Clock Operation Mode Select [KM076604] -6- 2009/08 [AKD4114-B] B, C, U, V Inputs and output VOUT VIN GND GND U GND GND 1 B 10 GND PORT3 BCUV C B(block start), C(channel status), U(user data) and V(validity) are inputted/outputted via 10pin header (PORT3: BCUV). Pin arrangement of PORT3 has become like Figure 3. 6 5 Figure 4. PORT3 pin layout Serial control The AK4114 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT6 (uP-I/F) with PC by 10-line flat cable packed with the AKD4114-B. Take care of the direction of connector. There is a mark at pin#1. The pin layout of PORT6 is as Figure 5. GND GND CCLK CSN GND CDTI 1 GND 2 CDTO PORT6 uP I/F GND SW1_6 JP18 CDTO/CM0=“H” L SDA and CM0=“L”(Note) H Note: In IIC mode, the chip address is fixed to “01”. Table 16. Set-up of Parallel mode and Serial mode NC Mode 4 wire Serial IIC 10 9 Figure 5. PORT6 pin layout This evaluation board encloses control software. A software operation procedure is included in an evaluation board manual. [KM076604] -7- 2009/08 [AKD4114-B] Toggle switch set-up SW2 PDN LED indication LE1 INT0 LE2 INT1 Reset switch for AK4114. Set to “H” during normal operation. Bring to “L” once after the power is supplied. Bright when INT0 pin goes to “H”. Bright when INT1 pin goes to “H”. DIP switch (SW1) set-up: -off- means “L” No. Switch Name Function 1 IPS0 Set-up of IPS0 pin. (in parallel mode) 2 DIF0 Set-up of DIF0 pin. (in parallel mode) 3 DIF1 Set-up of DIF1 pin. (in parallel mode) 4 DIF2 Set-up of DIF2 pin. (in parallel mode) Set-up of IPS1 pin. (in parallel mode) 5 IPS1/IIC Set-up of IIC pin. (in serial mode) “L”: 4 wire Serial, “H”: IIC Set-up of P/SN pin. “L”: Serial mode, “H”: Parallel mode 6 P/SN 7 TEST Don’t care 8 ACKS Don’t care DIP switch (SW3) set-up: -off- means “L” No. Switch Name Function 1 CM1 Set-up of CM1 pin. (in parallel mode) 2 OCKS1 Set-up of OCKS1 pin. (in parallel mode) 3 OCKS0 Set-up of OCKS0 pin. (in parallel mode) 4 PSEL Don’t care 5 XTL0 See Table 17 6 XTL1 Set-up of the transmission direction of 74AC245 DIR_I/O 7 “L”: When inputting from PORT2, “H”: When outputting from PORT2 8 DIT_I/O Don’t care Set-up of XTL1 and XTL0 SW3_6 SW3_5 X’tal Frequency XTL1 XTL0 X’tal 0 0 11.2896MHz 0 1 12.288MHz 1 0 24.576MHz 1 1 (Use channel status) Table 17. Set-up of XTL1 and XTL0 [KM076604] Default OFF OFF ON ON OFF OFF OFF OFF Default OFF OFF OFF OFF OFF OFF ON OFF Default -8- 2009/08 [AKD4114-B] Jumper set up. No. Jumper Name 1 D3V/VD 2 RXP0 4,5,6 RX1-3 7,8,9,10 RX4-7 11,12 DIR MCLK , DIT MCLK 13 TX0 18 SDA/CDTO 19 TXP1 [KM076604] Function Set-up of Power supply source for 74AC245. D3V : D3V (default) VD : VD Set-up of RXP0 input circuit. OPT : Optical (default) BNC : BNC Set-up of RX1-3 input circuit. RX4-7 set-up depending serial/parallel mode RX4-7 : Serial mode (default) DIF2-0,IPS0 : Parallel mode MCKO set-up for PORT5(DIT) and PORT2(DIR) MCKO1 : MCKO1 of AK4114 (default) MCKO2 : MCKO2 of AK4114 Set-up of TX0 output circuit. OPT : Optical BNC : BNC (default) Set-up of SDA/CDTO pin. 4 wire Serial : CDTO/CM0=“H”. (default) IIC : SDA Set-up of TXP1 input circuit. OPT : Optical (default) BNC : BNC -9- 2009/08 [AKD4114-B] Control Soft Manual Evaluation Board and Control Soft Settings 1. Set an evaluation board properly. 2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft does not support the Windows NT. 3. Proceed evaluation by following the process below. [KM076604] - 10 - 2009/08 [AKD4114-B] ■Operation Overview Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs. Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting. 1. [Port Reset] 2. [Write Default] 3. [All Write] 4. [All Read] 5. [Save] 6. [Load] 7. [All Req Write] 8. [Data R/W] 9. [Sequence] 10. [Sequence(File)] 11. [Read] : For when connecting to USB I/F board (AKDUSBIF-A) Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A). : Register Initializing When the device is reset by a hardware reset, use this button to initialize the registers. : Executing write commands for all registers displayed. : Executing read commands for all registers displayed. : Saving current register settings to a file. : Executing data write from a saved file. : “All Req Write” dialog box is popped up. : “Data R/W” dialog box is popped up. : “Sequence” dialog box is popped up. : “Sequence(File)” dialog box is popped up. : Reading current register settings and display on to the Register area (on the right of the main window). This is different from [All Read] button, it does not reflect to a register map, only displaying hexadecimal. Figure 6. Window of [ FUNCTION] [KM076604] - 11 - 2009/08 [AKD4114-B] ■Dialog Boxes [All Req Write] Click [All Reg Write] button in the main window to open register setting files. Register setting files saved by [SAVE] button can be applied. Figure 7. Window of [ All Reg Write] [Open (left)] [Write] [Write All] [Help] [Save] [Open (right)] [Close] : Selecting a register setting file (*.akr). : Executing register writing. : Executing all register writings. Writings are executed in descending order. : Help window is popped up. : Saving the register setting file assignment. The file name is “*.mar”. : Opening a saved register setting file assignment “*. mar”. : Closing the dialog box and finish the process. *Operating Suggestions (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be stored in the same folder. (2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new register settings. [KM076604] - 12 - 2009/08 [AKD4114-B] [Data R/W] Click the [Data R/W] button in the main window for data read/write dialog box. Data write is available to specified address. Figure 8. Window of [ Data R/W ] Address Box : Input data address in hexadecimal numbers for data writing. Data Box : Input data in hexadecimal numbers. Mask Box : Input mask data in hexadecimal numbers. This is “AND” processed input data. [Write] [Close] : Writing to the address specified by “Address” box. : Closing the dialog box and finish the process. Data writing can be cancelled by this button instead of [Write] button. *The register map will be updated after executing [Write] or [Read] commands. [KM076604] - 13 - 2009/08 [AKD4114-B] [Sequence] Click [Sequence] button to open register sequence setting dialog box. Register sequence can be set in this dialog box. Figure 9. Window of [ Sequence ] Sequence Setting Set register sequence by following process bellow. (1)Select a command Use [Select] pull-down box to choose commands. Corresponding boxes will be valid. < Select Pull-down menu > · No_use : Not using this address · Register : Register writing · Reg(Mask) : Register writing (Masked) · Interval : Taking an interval · Stop : Pausing the sequence · End : Finishing the sequence (2)Input sequence [Address] [Data] [Mask] [ Interval ] [KM076604] : Data address : Writing data : Mask [Data] box data is ANDed with [Mask] box data. This is the actual writing data. When Mask = 0x00, current setting is hold. When Mask = 0xFF, the 8bit data which is set in the [Data] box is written. When Mask =0x0F, lower 4bit data which is set in the [Data] box is written. Upper 4bit is hold to current setting. : Interval time - 14 - 2009/08 [AKD4114-B] Valid boxes for each process command are shown bellow. · No_use · Register · Reg(Mask) · Interval · Stop · End : None : [Address], [Data], [Interval] : [Address], [Data], [Mask], [Interval] : [Interval] : None : None Control Buttons The function of Control Button is shown bellow. [Start] [Help] [Save] [Open] [Close] : Executing the sequence : Opening a help window : Saving sequence settings as a file. The file name is “*.aks”. : Opening a sequence setting file “*.aks”. : Closing the dialog box and finish the process. Stop of the sequence When “Stop” is selected in the sequence, processing is paused and it starts again when [Start] button is clicked. Restarting step number is shown in the “Start Step” box. When finishing the process until the end of sequence, “Start Step” will return to “1”. The sequence can be started from any step by writing the step number to the “Start Step” box. Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning. [KM076604] - 15 - 2009/08 [AKD4114-B] [Sequence(File)] Click [Sequence(File)] button to open sequence setting file dialog box. Those files saved in the “Sequence setting dialog” can be applied in this dialog. Figure 10. Window of [ Sequence(File) ] [Open (left)] : Opening a sequence setting file (*.aks). [Start] : Executing the sequence setting. [Start All] : Executing all sequence settings. Sequences are executed in descending order. [Help] : Pop up the help window. [Save] : Saving sequence setting file assignment. The file name is “*.mas”. [Open(right)] : Opening a saved sequence setting file assignment “*. mas”. [Close] : Closing the dialog box and finish the process. *Operating Suggestions (1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be stored in the same folder. (2) When “Stop” is selected in the sequence the process will be paused and a pop-up message will appear. Click “OK” to continue the process. Figure 11. Window of [ Sequence Pause ] [KM076604] - 16 - 2009/08 [AKD4114-B] 1. [REG]: Register Map This tab is for a register writing and reading. Each bit on the register map is a push-button switch. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Grayout registers are Read Only registers. They can not be controlled. The registers which is not defined in the datasheet are indicated as “---”. Figure 12. Window of [ REG] [KM076604] - 17 - 2009/08 [AKD4114-B] [Write]: Data Writing Dialog It is for when changing two or more bits on the same address at the same time. Click [Write] button located on the right of the each corresponded address for a pop-up dialog box. When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”. Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting. Figure 13. Window of [ Register Set ] [Read]: Data Read Click [Read] button located on the right of the each corresponded address to execute register reading. After register reading, the display will be updated regarding to the register status. Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red). Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray) Please be aware that button statuses will be changed by Read command. [KM076604] - 18 - 2009/08 [AKD4114-B] REVISION HISTORY Date (yy/mm/dd) 04/11/22 05/06/21 05/12/22 07/12/19 09/08/05 Manual Revision KM076600 KN076601 KM076602 KM076603 KM076604 Board Revision 0 0 0 0 0 Reason Page First edition Change Addition Modification Change 13-15 2,5 5 10-18 Contents Circuit diagram was changed Block diagram at DIR/DIT Evaluation was added. DIT Evaluation item was modified. “Control Soft Manual” was changed. IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. [KM076604] - 19 - 2009/08 5 4 3 2 1 D 49 50 51 52 P/SN AVDD 53 54 55 56 RX0 57 58 RX1 59 60 61 62 RX2 IPS0/RX4 RX3 63 64 C N4 D P/SN + 2C19 1 10u C20 0.1u 2 C N1 R61 18k C21 0.47u 1 + C 5 PDN P DN DIF2/RX7 6 7 8 VIN DAUX DAUX 1 IPS0/RX4 2 3 AVDD 37 INT1 38 39 40 R AVSS VCOM 41 42 RX0 43 AVSS 44 RX1 45 TEST1 RX2 46 47 36 AVSS OCKS0/CSN/CAD0 35 DIF0/RX5 OCKS1/CCLK/SCL 34 CM1/CDTI/SDA 33 43 CM0/CDTO/CAD1 32 42 PDN 31 XTI 30 TEST2 5 DIF1/RX6 6 AVSS AK4114 DIF2/RX7 XTL0 IP S1/IIC MCKO1 8 IP S1/IIC IPS1/IIC XTO 29 MCKO2 MCKO2 12 44 C 41 OCKS0/CSN/CAD C22 40 5p OCKS1/CCLK/SCL C23 11.2896MHz 11 IPS1/IIC P DN 1 MCKO1 46 45 X1 10 XTL0 47 INT0 4 7 9 XTL1 XTL1 2 4 DIF1/RX6 AVSS RX3 2 3 C N3 48 U7 48 1 DIF0/RX5 P/SN 9 P/SN DAUX 28 DAUX XTL0 10 XTL0 MCKO2 27 MCKO2 XTL1 11 XTL1 BICK 26 B ICK 12 VIN SDTO 25 SDTO 39 5p CM1/CDTI/SDA CM0/CDTO/CAD1 38 37 + LRCK 33 MCKO1 C27 2 10u 32 31 30 28 27 26 25 24 OVDD A Title C N2 Size A3 D ate: 5 4 35 24 MCKO1 INT0 36 LRCK TX1 23 22 VOUT TX0 1 INT1 34 C25 0.1u C26 2 10u 20 UOUT 19 18 17 BOUT A COUT 1 23 22 DVSS DVDD 21 20 VOUT UOUT 19 COUT 18 BOUT 17 C24 0.1u 29 LRCK 21 LRCK + 16 16 SDTO NC SDTO 15 B ICK 13 15 BICK TVDD 14 14 13 TX1 B TX0 B 3 2 AKD4114 Document Number R ev SUB Monday, November 22, 2004 A Sheet 1 3 of 3 5 4 3 2 1 CN1 JP1 For U6 For U1, U2, U5 VD PORT1 D3V D3V For U3, U4 6 D3V 6 D3V/VD VD VD 5 5 L1 4 3 2 1 GND VCC GND OUT VD C7 TORX176 C1 C2 C3 C4 C5 0.1u 0.1u0.1u0.1u 0.1u 0.1u 49 10u C6 50 C8 + 0.1u R1 10u 51 JP2 OPT XLR BNC 470 D 1 3 5 2 4 6 AVDD P/SN/ANS T2 LP2950A ACKS +5V L2 1 short + OUT C11 47u IN RXP0 R4 RX1 R5 0.1u GND AVDD AVDD + C14 47u RX2 C15 47u IPS0 DIF0 DIF1 DIF2/XSEL IPS1/IIC P/SN/ANS TEST ACKS R8 short 16 15 14 13 12 11 10 9 JP7 D3V RX4 RX3 IPS0 AVDD AVDD IPS0/RX4 JP8 RX6 TEST TEST DIF1/RX6 DIF1 PDN DIF2/XSEL R9 1A 1B 2A 2B 3A 3B 4A 4B 15 1 G A/B U2A 4 2Y 7 3Y 9 100 R11 4Y 12 100 R12 H U2B 2 3 DAUX2 4 L 74HC14 EMCK2 VIN R10 1 1Y DAUX2 PDN R22 100k 100k R23 100k DAUX 5 6 7 8 9 MCKO1 MCKO1 10 MCKO DIT_MCLK 100 MCKO2 U3 B0 B1 B2 B3 B4 B5 B6 B7 MCKO2 MCKO2 JP12 MCKO1 DIR 4 JP11 0.1u DIR_MCLK A VIN C16 SW2 3 100 74HC14 74LVC157 18 17 16 15 14 13 12 11 DVDD 2 B D1 1S1588 U1 2 3 5 6 11 10 14 13 DVDD 10k D3V B 1 JP9 DIF2/XSEL/RX7 R15 R16 R18 R20 64 CN2 DIF0/RX5 JP10 RX7 100 100 100 100 C 63 DIF0 IPS1/IIC P/SN/ANS TEST ACKS 47k MCLK BICK LRCK SDTO DAUX 62 RX5 1 2 3 4 5 6 7 8 9 EMCK1 60 61 SW1 1 2 3 4 5 6 7 8 RP1 1 2 3 4 5 59 JP6 D3V PORT2 10 9 8 7 6 58 JP5 short GND GND GND GND GND 56 JP4 IN OVDD C 55 C13 RX0 75 OUT + 54 57 J2 R6 R7 D 53 VD short short ACKS 52 TVDD/VDD T3 TA48M33F DVDD P/SN/ANS RXN0 10u 3 2 AVDD GND R3 AVDD A0 A1 A2 A3 A4 A5 A6 A7 2 3 4 5 6 7 8 9 DIR OE 1 19 R13 DVDD OVDD 100 R14 100 100 R17 R19 BICK 100 R21 SDTO 11 12 13 LRCK 14 15 A 16 DIR_I/O 74AC245 Title Size A3 Date: 5 4 3 2 AKD4114-B Document Number Rev MAIN Friday, November 19, 2004 0 Sheet 1 1 of 2 5 4 3 2 1 CN3 PORT3 JP19 OPT XLR BNC 1 3 5 1 2 3 4 5 TXP1 2 4 6 10 9 8 7 6 R24 R25 R26 R27 R28 B C U VOUT VIN B 100 100 100 100 100 C VIN U BCUV R29 R30 R31 R32 D JP13 PORT4 5 6 5 6 47k 47k 47k 47k VOUT TX0 IN VCC IF GND TX0 VD TXP1 C17 R33 1k 0.1u TXN1 J4 TX0 18 19 20 D 21 OPT 4 3 2 1 TOTX176 TVDD TVDD/VDD 17 T5 22 23 24 R36 DA02-F 25 R37 240 26 150 1:1 27 28 29 OVDD OVDD C 30 C 31 EBICK 32 CN4 U2C LE1 6 INT0 EMCK EMCK2 R45 5 ELRCK 1k U2D 8 INT1 9 1k U5 R48 74HC14 10k R49 470 R51 10k R52 470 R54 10k R55 470 VD B PORT6 10 8 6 4 2 9 7 5 3 1 CSN R56 SCL/CCLK SDA/CDTI 51 SDA(ACK)/CDTO P/SN/ANS 15 1 G A/B 1Y 4 2Y 7 3Y 9 4Y 12 37 R50 CM1/CDTI/SDA 100 R53 1 38 B 100 U6A OCKS1/CCLK/SCL 2 OCKS0/CSN/CAD0 D3V R57 DVDD DVDD 10k R59 R60 39 40 41 42 100 43 SDA/CDTO 100 D3V IPS1/IIC IPS1/IIC PSEL D3V/VD XTL0 XTL1 RP2 1 2 3 4 5 6 7 8 9 36 74LS07 SDA CDTO/CM0=H CM0=L SW3 16 15 14 13 12 11 10 9 1A 1B 2A 2B 3A 3B 4A 4B JP18 10k 1 2 3 4 5 6 7 8 2 3 5 6 11 10 14 13 R58 D3V CM1/FS1 OCKS1/FS2 OCKS0/FS0 PSEL XTL0/CKS1 XTL1/TRANS DIR_I/O DIT_I/O CM0/CDTO/CAD1 74LVC157 uP-I/F A 35 R47 D3V INT1 34 74HC14 INT0 LE2 33 44 45 46 47 A 48 DIR_I/O DIT_I/O Title 47k Size A3 Date: 5 4 3 2 AKD4114-B Document Number Rev MAIN Tuesday, June 21, 2005 0 Sheet 1 2 of 2 AKD4115-A L1 AKD4115-A L1_SILK