NCP458R, NCP459 4 A Single Load Switch for Low Voltage Rail The NCP458R and NCP459 are power load switch with very low Ron NMOSFET controlled by external logic pin, allowing optimization of battery life, and portable device autonomy. Indeed, thanks to a best in class current consumption optimization with NMOS structure, leakage currents are drastically decreased. Offering optimized leakages isolation on the ICs connected on the battery. Output discharge path is proposed, in the NCP459 version , to eliminate residual voltages on the external components connected on output pin. Reverse voltage protection, from OUT to IN is offered in the NCP458R version. Proposed in wide input voltage range from 0.75 V to 5.5 V, and a very small CSP8 1 x 2 mm2. http://onsemi.com MARKING DIAGRAM A Y WW G = Assembly Location = Year = Work Week = Pb−Free Package PINOUT Features • • • • • • • • XXXX AYWWG WLCSP8 CASE 567HD 0.75 V − 5.5 V Operating Range 11 mW N−MOSFET Vbias Rail Input DC Current up to 4 A Output Auto−Discharge Option Reverse Blocking Option Active High EN Pin CSP8, 1 x 2 mm2, Pitch 0.5 mm 1 2 A EN GATE B IN OUT C IN OUT D VBIAS GND Typical Applications • • • • • Notebooks Tablets Wireless Mobile Phones Digital Cameras (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 12 of this data sheet. Vcc V+ LS NCP458−459 SMPS DCDC Converter B1 OUT C1 IN OUT A2 IN D1 Gate EN Vbias GND or LDO B2 C2 A1 D2 Platform IC’n ENx EN 0 Figure 1. Typical Application Schematic © Semiconductor Components Industries, LLC, 2014 June, 2014 − Rev. 1 1 Publication Order Number: NCP458R/D NCP458R, NCP459 LS NCP458−459 DCDC Converter B1 C1 A2 D1 or LDO IN OUT IN OUT Gate EN Vbias GND B2 C2 A1 D2 Platform IC’n ENx EN 0 Figure 2. Application Schematic with Vbias Connected to IN and No Gate Delay PIN FUNCTION DESCRIPTION Pin Name Pin Number Type Description EN A1 INPUT IN B1, C1 POWER Enable input, logic high turns on power switch . Load−switch input pin. VBIAS D1 POWER External supply voltage input. GATE A2 INPUT OUT B2, C2 POWER Load−switch output pin. GND D2 POWER Ground connection. OUT pin slew rate control (trise). http://onsemi.com 2 NCP458R, NCP459 BLOCK DIAGRAMS IN: B1, C1 OUT : B2, C 2 GATE : A2 Gate driver Control logic & Charge Pump EN: A1 GND : D2 VBIAS : D1 Figure 3. NCP458R Block Diagram IN: B1, C1 OUT : B2 , C 2 GATE : A2 Control logic & Charge Pump Gate driver GND : D 2 VBIAS : D 1 EN : A1 Figure 4. NCP459 Block Diagram http://onsemi.com 3 NCP458R, NCP459 MAXIMUM RATINGS Rating Symbol Value Unit VEN, VIN , VOUT, VBIAS, VGATE −0.3 to +6.5 V From IN to OUT Pins: Input/Output (Note 1) NCP459 VIN , VOUT 0 to + 6.5 V From IN to OUT Pins: Input/Output (Note 1) NCP458R VIN , VOUT ±6.5 V Human Body Model (HBM) ESD Rating are (Note 2) ESD HBM 2000 V Machine Model (MM) ESD Rating are (Note 2) ESD MM 200 V LU 100 mA TJ −40 to + 125 °C Storage Temperature Range TSTG −40 to + 150 °C Moisture Sensitivity (Note 4) MSL Level 1 IN, OUT, EN, VBIAS, GATE Pins: (Note 1) Latch−up protection (Note 3) − Pins IN, OUT, EN, VBIAS and GATE Maximum Junction Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. According to JEDEC standard JESD22−A108. 2. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114 for all pins. Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins. 3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II. 4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020. OPERATING CONDITIONS Symbol Parameter Max Unit 0.75 5.5 V 0 5.5 V Bias voltage (VBIAS ≥ best of VIN, VOUT) 1.2 5.5 V TA Ambient Temperature Range − 40 + 85 °C CIN Decoupling input capacitor 100 nF COUT Decoupling output capacitor 100 nF RqJA Thermal Resistance Junction to Air VIN Operational Power Supply VEN Enable Voltage VBIAS Conditions Min CSP8 (Note 5) PD 25 °C/W 90 DC current IOUT Typ 4 4.5 A AC current 1 ms @ 217 Hz 5 A AC current 100 ms spike 15 A Power Dissipation Rating (Note 6) 0.315 W Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. The RqJA is dependent of the PCB heat dissipation and thermal via. 6. The maximum power dissipation (PD) is given by the following formula: PD + http://onsemi.com 4 T JMAX * T A R qJA NCP458R, NCP459 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN between 0.75 V and 5.5 V, and VBIAS between 1.2 V and 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C, VIN = 3.3 V and VBIAS = 5 V (Unless otherwise noted). Parameter Symbol Conditions Min Typ Max 11 20 Unit POWER SWITCH TA = 25°C VIN = VBIAS = 5.5 V TJ = 125°C TA = 25°C VIN = VBIAS = 3.3 V TJ = 125°C TA = 25°C VIN = VBIAS = 1.8 V RDS(on) Static drain−source on−state resistance for each rail TA = 25°C VIN = VBIAS = 1.5 V 13 TA = 25°C 13 VIN = 0.8 V VBIAS = 1.2 V 14 20 24 30 17 30 EN = low, NCP459 230 300 No cap on GATE pin 0.26 Gate capacitor = 1 nF 1.5 Gate capacitor = 10 nF 15 Without Cgate 10 ms With 1 nF on Gate 60 ms 50 ms From EN to 90% Vout 75 ms No cap on GATE pin 0.25 TJ = 125°C Output discharge path mW 24 TJ = 125°C TA = 25°C 20 24 TJ = 125°C VIN = 1.0 V VBIAS = 1.2 V 20 24 TJ = 125°C TA = 25°C 20 24 12 TJ = 125°C VIN = VBIAS = 1.2 V RDIS 24 11 35 W TIMINGS TR Output rise time From 10% to 90% of VOUT Ten Enable time From En Vih to 10% of VOUT TF Fall Time. From 90% to 10% of VOUT Tdis TR Ten VIN = 5 V CLOAD = 1 mF, RLOAD = 25 W Disable time Output rise time From 10% to 90% of VOUT Enable time From En Vih to 10% of VOUT TF Output fall time From 90% to 10% of VOUT TR Output rise time From 10% to 90% of VOUT Ten Enable time From En Vih to 10% of VOUT TF Output fall time From 90% to 10% of VOUT VIN = 3.3 V CLOAD = 1 mF, RLOAD = 25 W Gate capacitor = 1 nF 1 Gate capacitor = 10 nF 10 ms 0.5 ms Without Cgate, NCP459 20 50 ms Without Cgate, NCP458R 90 150 ms With 1 nF on Gate 114 60 VIN = 1.8 V CLOAD = 1 mF, RLOAD = 25 W ms 120 ms No cap on GATE pin 0.12 Gate capacitor = 1 nF 0.6 Gate capacitor = 10 nF 5.5 Without Cgate 15 ms With 1 nF on Gate 85 ms 35 ms ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground http://onsemi.com 5 NCP458R, NCP459 ELECTRICAL CHARACTERISTICS Min & Max Limits apply for TA between −40°C to +85°C for VIN between 0.75 V and 5.5 V, and VBIAS between 1.2 V and 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C, VIN = 3.3 V and VBIAS = 5 V (Unless otherwise noted). Symbol Parameter Conditions Min Typ Max Unit TIMINGS Output rise time From 10% to 90% of VOUT VIN = 1 V CLOAD = 1 mF, RLOAD = 25 W Ten Enable time From En Vih to 10% of VOUT TF Output fall time VIN = 1 V CLOAD = 1 mF, RLOAD = 25 W TR No cap on GATE pin 0.01 Gate capacitor = 1 nF 1 Gate capacitor = 10 nF 13 ms Without Cgate 10 ms With 1 nF on Gate 0.4 ms 20 ms Logic VIH High−level input voltage VIL Low−level input voltage REN Pull down resistor 0.9 V 3 0.4 V 7 MW REVERSE CURRENT BLOCKING Vrev_thr Reverse threshold Vrev_hyst Reverse threshold hysteresis Trev Reverse comparator response time VOUT − VIN 45 mV 60 mV VOUT − Vin > Vrev_thr 2.5 ms VBIAS = 3.3 V, EN = high 1.5 6 mA EN = high 0.01 0.3 mA EN = low, IN standby current, VIN = 3.3 V, without discharge path. 0.01 0.3 mA QUIESCENT CURRENT− NCP458R IVBIAS IINQ ISTBIN VBIAS Quiescent current IN Quiescent current Standby current IN ISTDVbias Standby current VBIAS VBIAS = 3.3 V EN = low 0.4 1.5 mA Iout_leak Output leakage current IN connected to GND, VOUT = 5 V 0.01 0.5 mA VBIAS = 3.3 V, EN = high 1.3 5 mA EN = high 0.01 0.3 mA EN = low, IN standby current, VIN = 3.3 V, with discharge path. NCP459. 0.01 0.3 mA VBIAS = 3.3 V EN = low 0.4 1.5 mA QUIESCENT CURRENT − NCP459 IVBIAS IINQ ISTBIN ISTDVbias VBIAS Quiescent current IN Quiescent current Standby current IN Standby current VBIAS Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 7. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground http://onsemi.com 6 NCP458R, NCP459 TIMINGS VIN EN VOUT T EN T R T DIS T ON TF T OFF Figure 5. Enable, Rise and Fall Time http://onsemi.com 7 NCP458R, NCP459 TYPICAL CHARACTERISTICS 25 6.0 5.8 5.6 5.4 125°C 15 REN (MW) RDS(on) (mW) 20 85°C 25°C 10 −40°C −40°C 5.0 25°C 4.8 85°C 4.6 125°C 4.4 5 4.2 0 0.8 1.3 1.8 2.3 2.8 3.3 VIN (V) 3.8 4.3 4.8 4.0 0.5 5.3 0.60 300 0.50 ISTDVBIAS (mA) 250 200 150 100 −40°C 25°C 50 85°C 125°C 0 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 VIN (V) 5.5 0.30 0.20 −40°C 25°C 85°C 125°C 0.10 0 1 2 3 4 VBIAS (V) 5 Figure 9. NCP458R Standby Current (mA) vs VBIAS (V), Over Temperature Range 0.50 4.0 0.45 3.5 0.40 3.0 0.35 IVBIAS (mA) ISTDVBIAS (mA) 4.5 0.40 Figure 8. Discharge Resistor (W) vs VIN (V), Over Temperature Range 0.30 0.25 0.20 0.15 0.05 3.5 Figure 7. Pull Down Resistor (MW) vs VEN (V), Over Temperature Range 350 0.10 2.5 VEN (V) Figure 6. RDS(on) (mW) vs VIN (V), Over Temperature Range RDIS (W) 1.5 2.5 2.0 1.5 −40°C 25°C 85°C 125°C 1.0 −40°C 25°C 85°C 125°C 0.5 0 0 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 VBIAS (V) 1 Figure 10. NCP459 Standby Current (mA) vs VBIAS (V), Over Temperature Range 2 3 4 VBIAS (V) 5 Figure 11. NCP458R Quiescent Current (mA) vs VBIAS (V), Over Temperature Range http://onsemi.com 8 NCP458R, NCP459 TYPICAL CHARACTERISTICS 3.0 10k −40°C 25°C 85°C 125°C 2.5 TEN (ms) I_VBIAS (mA) 1k 2.0 1.5 100 1.0 −40°C 25°C 85°C 125°C 0.5 10 1 0.8 0 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 5.25 VBIAS (V) Figure 12. NCP459 Quiescent Current (mA) vs VBIAS (V), Over Temperature Range TDIS (ms) 2.3 2.8 3.3 VIN (V) 3.8 4.3 4.8 1 0.8 5.3 1.3 1.8 2.3 10 2.3 5.3 2.8 3.3 VIN (V) 3.8 4.3 4.8 5.3 Figure 15. Disable Time (ms) vs VIN (V), Over Temperature Range VBIAS and VIN Tied Together 100 1.8 4.8 −40°C 25°C 85°C 125°C 1k 1.3 4.3 100 Figure 14. Rise Time (ms) vs VIN (V), Over Temperature Range (without Cgate) 1 0.8 3.8 1k 10 1.8 2.8 3.3 VIN (V) 10k −40°C 25°C 85°C 125°C 1.3 2.3 Figure 13. Enable Time (ms) vs VIN (V) , Over Temperature Range (without Cgate) 1.0 0.1 0.8 1.8 TF (ms) TR (ms) 10 1.3 2.8 3.3 VIN (V) 3.8 4.3 4.8 Figure 16. Fall Time (ms) vs VIN (V), Over Temperature Range VBIAS and VIN Tied Together Rload 25 W http://onsemi.com 9 5.3 NCP458R, NCP459 FUNCTIONAL DESCRIPTION Overview If Vbias rail is not available or used, Vbias pin and Vin pin can be connected together as close as possible the DUT. A minimum of 1.2 V is necessary to control the IC. The NCP458R and NCP459 are high side N channel MOSFET power distribution switch designed to isolate ICs connected on the battery or DCDC supplies in order to save energy. The part can be used with a wide range of supply from 0.75 V to 5.5 V. Output rise time − Gate control The NMOS is control with internal charge pump and driver. A minimum gate slew rate is internally set to avoid huge inrush current when EN is set from low to high. The default gate slew rate depends on Vin level. The higher Vin level, the longer rise time. In addition, an external capacitor can be connected between Gate pin and GND in order to slow down the gate rising. See electrical table for more details. Enable Input Enable pin is an active high. The path is opened when EN pin is tied low (disable), forcing NMOS switch off. The IN/OUT path is activated with a minimum of VBIAS min, Vin min and EN forced to high level. Auto Discharge (Optional − NCP459) NMOS FET is placed between the output pin and GND, in order to discharge the application capacitor connected on OUT pin. The auto−discharge is activated when EN pin is set to low level (disable state). The discharge path ( Pull down NMOS) stays activated as long as EN pin is set at low level. In order to limit the current across the internal discharge Nmosfet, the typical value is set at RDIS value. Cin and Cout Capacitors 100 nF external capacitors must be connected as close as possible the DUT for noise immunity and better stability. In case of input hot plug (input voltage connected with fast slew rate − few ms − it’s strongly recommended to avoid big capacitor connected on the input. That allows to avoid input over voltage transients. Reverse Blocking Control (Optional NCP458R) A reverse blocking control circuitry is embedded to eliminate leakages from OUT to IN in case of Vout > Vin. A comparator measures the dropout voltage on the switch between OUT and IN and turn off the NMOS if this voltage exceeds specified reverse voltage. Vbias Rail The core of the IC is supplied thanks to Vbias supply rail (common +5 V, 3.3 V, 1.8 V, 1.2 V). Indeed, no current consumption is used on IN pin, allowing to improve power saving of the rail that must be isolated by the power switch. http://onsemi.com 10 NCP458R, NCP459 APPLICATION INFORMATION Power Dissipation Demoboard Main contributor in term of junction temperature is the power dissipation of the power MOSFET. Assuming this, the power dissipation and the junction temperature in normal mode can be calculated with the following equations: The NCP458R and NCP459 integrate a 4 A rated NMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The package is a CSP and due to the low thermal resistance of the silicon, all the balls can be used to improved power dissipation. Indeed, even if the power crosses the IN / OUT pins only, all the balls around this power area should be connected to the larger PCB area. In the below PCB example (application demonstration board), all the PCB areas connected to 6 balls are enlarged. In addition vias are connected to bottom side with exactly same form factor of the other PCB side. Additional improvements can be done also by using more copper thickness and the thinner epoxy as possible. P D + R DS(on) PD RDS(on) IOUT 2 (eq. 1) = Power dissipation (W) = Power MOSFET on resistance (W) = Output current (A) TJ + PD TJ RqJA TA ǒIOUTǓ R qJA ) T A (eq. 2) = Junction temperature (°C = Package thermal resistance (°C/W) = Ambient temperature (°C) Figure 18. Demonstration Board (bottom view) Figure 17. Demonstration Board (top view) http://onsemi.com 11 NCP458R, NCP459 C1 1μF C3 1nF IN OUT IN OUT Gate EN Vbias GND 1 GND C2 1μF D2 DIODE ZENER1 GND NCP458−9 1 2 Bat B2 C2 A1 D2 2 B1 C1 A2 D1 D1 DIODE ZENER1 J9 OUT_2 1 OUT U1 2 IN IN_2 VBIAS 100 k 1μF R1 C4 EN R2 100 k Figure 19. Demonstration Board Schematic BILL OF MATERIAL TABLE Quantity Reference schem 2 IN, OUT 4 IN_2, OUT_2, VBIAS, EN 1 J9 (Bat) 3 C1, C2, C4 1 C3 1 D1, D2 2 GND2,GND 2 R2, R3 1 U1 Part description Socket, 4mm, metal, PK5 HEADER200 HEADER200-2 1uF 1nF, Not mounted TVS GND JUMPER Resistor 100k 0603 Load switch Part number B010 2.54 mm, 77313-101-06LF 2.54 mm, 77313-101-06LF GRM155R70J105KA12# GRM188R60J102ME47# ESD9x D3082F05 MC 0.063 0603 1% 100K NCP458 - 459 Manufacturer HIRSCHMANN FC FC Murata Murata ON Semiconductor Harvin MULTICOMP ON Semiconductor ORDERING INFORMATION Device Options Marking Package Shipping† NCP458RFCT2G Reverse Voltage Protection 458RdYWW WLCSP 1 x 2 mm (Pb−Free) 3000 Tape / Reel NCP458RFCCT2G Reverse Voltage Protection, Die Coating 458RCdYWW WLCSP 1 x 2 mm (Pb−Free) 3000 Tape / Reel NCP459FCT2G Discharge Path 459dYWW WLCSP 1 x 2 mm (Pb−Free) 3000 Tape / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 12 NCP458R, NCP459 PACKAGE DIMENSIONS WLCSP8, 2.0x1.0 CASE 567HD ISSUE O D PIN A1 REFERENCE 0.25 C 2X ÈÈ 0.25 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF THE SOLDER BALLS. A B E DIM A A1 A2 b D E e TOP VIEW A A2 0.10 C MILLIMETERS MIN MAX 0.66 −−− 0.21 0.27 0.36 REF 0.29 0.34 2.00 BSC 1.00 BSC 0.50 BSC A1 RECOMMENDED SOLDERING FOOTPRINT* 0.05 C NOTE 3 C SIDE VIEW e/2 8X e b 0.05 C A B SEATING PLANE PACKAGE OUTLINE 0.50 PITCH e/2 e A1 0.50 PITCH 1 0.03 C 2 A B C 8X 0.25 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. D BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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