Cirrus CS5016 16,14 & 12-bit self calibrating a/d converter Datasheet

CS5012A CS5014 CS5016
16-, 14-, & 12-bit Self-calibrating A/D Converters
Features
z
Description
Monolithic CMOS A/D Converters
The CS5012A/14/16 are 12-, 14-, and 16-bit monolithic analog to digital converters with conversion
times of 7.2 µs, 14.25 µs and 16.25 µs. Unique selfcalibration circuitry ensures excellent linearity and
differential nonlinearity, with no missing codes. Offset and full-scale errors are kept within 1/2 LSB
(CS5012A/14) and 1 LSB (CS5016), eliminating the
need for calibration. Unipolar and bipolar input
ranges are digitally selectable.
– Microprocessor Compatible
– Parallel & Serial Output
– Inherent Track/Hold Input
z
True 12-bit, 14-bit, and 16-bit Precision
z
Conversion Times
– CS5016: 16.25 µs
– CS5014: 14.25 µs
– CS5012A: 7.20 µs
z
The pin compatible CS5012A/14/16 consist of a
DAC, conversion and calibration microcontroller,
oscillator, comparator, microprocessor-compatible
3-state I/O, and calibration circuitry. The input
track-and-hold, inherent to the devices’ sampling
architecture, acquires the input signal after each
conversion using a fast-slewing, on-chip buffer amplifier. This allows throughput rates up to
100 kSps(CS5012A), 56 kSps (CS5014), and
50 kSps (CS5016).
Linearity Error: ±0.001% FS
– Guaranteed No Missing Codes
z
Self-calibration Maintains Accuracy
– Accurate Over Time & Temperature
z
Low Power Consumption
– 150 mW
z
ORDERING INFORMATION
Low Distortion
See “Ordering Information” on page39.
I
HOLD CS
1
CLKIN
REFBUF
VREF
AIN
AGND
23
RD
24
25
A0 BP/UP RST BW INTRLV CAL
26
27
Clock
Generator
31
29
+
30
+
28
VA+
http://www.cirrus.com
37
38
39
41
42
43
44
Control
32
+
36
EOT EOC SCLK SDATA
Calibration
Memory
Microcontroller
Charge
Redistribution
DAC
+
Comparator
Status Register
34
VA-
12
VD+
40
VD-
11
DGND
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
35
2
3
4
5
6
7
8
10
14
16
17
18
19
20
21
22
D0 (LSB) CS5016
D1
D2 (LSB) CS5014
D3
D4 (LSB) CS5012A
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MSB)
TST
AUG ‘05
DS14F9
CS5012A CS5014 CS5016
CS5012A
CS5012A ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 2.5V to 4.5V; fclk = 6.4 MHz for -7, 4 MHz for -12; Analog Source Impedance = 200Ω)
CS5012A
Parameter*
Min
Specified Temperature Range
Typ
Max
Units
-40 to +85
°C
Accuracy
Linearity Error
Drift
(Note 1)
(Note 2)
±1/4
±1/8
±1/2
LSB12
∆LSB12
Differential Linearity
Drift
(Note 1)
(Note 2)
±1/4 ±1/2
±1/32
LSB12
∆LSB12
Full Scale Error
Drift
(Note 1)
(Note 2)
±1/4 ±1/2
±1/16
LSB12
∆LSB12
Unipolar Offset
Drift
(Note 1)
(Note 2)
±1/4 ±1/2
±1/16
LSB12
∆LSB12
Bipolar Offset
Drift
(Note 1)
(Note 2)
±1/4 ±1/2
±1/16
LSB12
∆LSB12
Bipolar Negative Full-Scale Error(Note 1)
Drift
(Note 2)
±1/4 ±1/2
±1/16
LSB12
∆LSB12
Total Unadjusted Error
Drift
±1/4
±1/4
LSB12
∆LSB12
92
88
dB
dB
0.008
%
73
13
dB
dB
45
90
µVrms
µVrms
(Note 1)
(Note 2)
Dynamic Performance (Bipolar Mode)
Peak Harmonic or
Spurious Noise
Full Scale, 1 kHz Input
Full Scale, 12 kHz Input
(Note 1)
84
84
Total Harmonic Distortion
Signal-to-Noise Ratio
1 kHz, 0 dB Input
1 kHz, -60 dB Input
(Note 1)
Noise
Unipolar Mode
Bipolar Mode
(Note 3)
72
Notes: 1. Applies after calibration at any temperature within the specified temperature range.
2. Total drift over specified temperature range since calibration at power-up at 25 °C
3. Wideband noise aliased into the baseband. Referred to the input.
* Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
22-8
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A
CS5012A ANALOG CHARACTERISTICS (continued)
CS5012A
Parameter*
Min
Specified Temperature Range
Typ
Max
Units
-40 to +85
°C
Aperture Time
25
ns
Aperture Jitter
100
ps
Analog Input
Input Capacitance
Unipolar Mode
(Note 4)
CS5012A
103
137
CS5012A
72
96
pF
pF
pF
pF
7.2
µs
2.8
µs
Bipolar Mode
Conversion & Throughput
Conversion Time
(Notes 5 and 6)
Acquisition Time
(Note 6)
Throughput
(Note 6)
2.5
100
kSps
Power Supplies
DC Power Supply Currents
IA+
IAD+
(CS5012A)
ID+
IDPower Dissipation
Power Supply Rejection
Positive Supplies
Negative Supplies
(Note 7)
(Note 7)
12
-12
3
6
-3
19
-19
6
7.5
-6
mA
mA
mA
mA
mA
150
250
mW
(Note 8)
84
84
dB
dB
Notes: 4. Applies only in track mode. When converting or calibrating, input capacitance will not exceed 15 pF.
5. Measured from falling transition on HOLD to falling transition on EOC.
6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions.
The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s
conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock.
Refer to the section Conversion Time/Throughput for a detailed discussion of conversion timing.
7. All outputs unloaded. All inputs CMOS levels.
8. With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply
rejection versus frequency.
DS14F9
DS14F8
2-93
CS5012A CS5014 CS5016
CS5014
CS5014 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -14, 2 MHz for -28; Analog Source Impedance = 200Ω)
CS5014-B
Parameter*
Min
Specified Temperature Range
Typ
Max
Units
-40 to +85
°C
Accuracy
(Note 1)
±1/4 ±1/2
(Note 2)
±1/8
LSB14
LSB14
∆LSB14
Differential Linearity
Drift
(Note 1)
(Note 2)
±1/4 ±1/2
±1/32
LSB14
∆LSB14
Full Scale Error
Drift
(Note 1)
(Note 2)
±1/2
±1/4
±1
LSB14
∆LSB14
Unipolar Offset
(Note 1)
±1/4
±3/4
(Note 2)
±1/4
LSB14
LSB14
∆LSB14
(Note 1)
±1/4
±3/4
(Note 2)
±1/2
LSB14
LSB14
∆LSB14
±1
Linearity Error
Drift
Drift
Bipolar Offset
Drift
Bipolar Negative Full-Scale Error(Note 1)
(Note 2)
±1/4
LSB14
LSB14
∆LSB14
(Note 1)
(Note 2)
±1
±1
LSB14
∆LSB14
94
98
84
87
dB
dB
dB
dB
±1/2
Drift
Total Unadjusted Error
Drift
Dynamic Performance (Bipolar Mode)
Peak Harmonic or
Spurious Noise
Full Scale, 1 kHz Input
(Note 1)
Full Scale, 12 kHz Input
Total Harmonic Distortion
Signal-to-Noise Ratio
1 kHz, 0 dB Input
%
84
23
dB
dB
dB
45
90
µVrms
µVrms
(Notes 1 and 9)
82
1 kHz, -60 dB Input
Noise
Unipolar Mode
Bipolar Mode
0.003
(Note 3)
Notes: 9. A detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28
for the CS5016.
* Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
42-10
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5014
CS5014 ANALOG CHARACTERISTICS (continued)
CS5014
Parameter*
Min
Specified Temperature Range
Typ
Max
Units
-40 to +85
°C
Aperture Time
25
ns
Aperture Jitter
100
ps
Analog Input
Input Capacitance
Unipolar Mode
Bipolar Mode
(Note 4)
275
165
375
220
pF
pF
14.25
µs
3.75
µs
Conversion & Throughput
Conversion Time
-14 (Notes 5 and 6)
Acquisition Time
-14
(Note 6)
Throughput
-14
(Note 6)
3.0
55.6
kSps
Power Supplies
DC Power Supply Currents
IA+
IAID+
ID-
(Note 7)
Power Dissipation
(Note 7)
Power Supply Rejection
Positive Supplies
Negative Supplies
(Note 8)
DS14F9
DS14F8
9
-9
3
-3
19
-19
6
-6
mA
mA
mA
mA
120
250
mW
84
84
dB
dB
2-115
CS5012A CS5014 CS5016
CS5016
CS5016 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 4.5V; CLKIN = 4 MHz for -16, 2 MHz for -32; Analog Source Impedance = 200Ω;
Synchronous Sampling.)
CS5016
Parameter*
Min
Specified Temperature Range
Typ
Max
Min
0 to +70
Typ
Max
-40 to +85
Min
Typ
Max
Units
-55 to +125
°C
Accuracy
Linearity Error
Drift
J, A, S
Differential Linearity
(Note 1)
(Note 2)
(Note 10)
0.001 0.0015
±1/4
16
16
%FS
∆LSB16
16
Bits
Full Scale Error
Drift
J, A, S
(Note 1)
(Note 2)
±2
±1
±3
LSB16
∆LSB16
Unipolar Offset
Drift
J, A, S
(Note 1)
(Note 2)
±1
±1
±3
LSB16
∆LSB16
(Note 1)
(Note 2)
±1
±2
±2
LSB16
∆LSB16
Bipolar Negative Full-Scale Error(Note 1)
Drift
(Note 2)
±2
±2
±3
LSB16
∆LSB16
Bipolar Offset
Drift
Dynamic Performance (Bipolar Mode)
Peak Harmonic or
Spurious Noise
(Note 1)
Full Scale, 1 kHz Input
100
104
dB
Full Scale, 12 kHz Input
85
91
dB
0.001
%
92
dB
32
dB
35
70
µVrms
µVrms
Total Harmonic Distortion
Full Scale, 1 kHz Input
Signal-to-Noise Ratio
(Notes 1 and 9)
1 kHz, 0 dB Input
90
1 kHz, -60 dB Input
Noise
Unipolar Mode
Bipolar Mode
(Note 3)
Notes: 10. Minimum resolution for which no missing codes is guaranteed
* Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet).
Specifications are subject to change without notice.
62-12
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5016
CS5016 ANALOG CHARACTERISTICS (continued)
CS5016-J, K
Parameter*
Min
Specified Temperature Range
Typ
Max
CS5016-A, B
Min
Typ
Max
CS5016-S, T
Min
Typ
Max
Units
0 to +70
-40 to +85
-55 to +125
°C
Aperture Time
25
25
25
ns
Aperture Jitter
100
100
100
ps
Analog Input
Input Capacitance
Unipolar Mode
Bipolar Mode
(Note 4)
275
165
375
220
pF
pF
16.25
µs
3.75
µs
Conversion & Throughput
Conversion Time
-16 (Notes 5 and 6)
-32
Acquisition Time
-16
-32
(Note 6)
Throughput
-16
-32
(Note 6)
3.0
50
kSps
Power Supplies
DC Power Supply Currents
IA+
IAID+
ID-
(Note 7)
Power Dissipation
(Note 7)
Power Supply Rejection
Positive Supplies
Negative Supplies
(Note 8)
DS14F9
DS14F8
120
250
9
-9
3
-3
19
-19
6
-6
120
250
84
84
mA
mA
mA
mA
120
250
mW
dB
dB
2-137
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%;
VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF, BW = VD+)
Parameter
Symbol
CS5012A CLKIN Frequency:
Internally Generated:
Externally Supplied:
CS5014/5016 CLKIN Frequency:
Internally Generated:
Externally Supplied:
fCLK
-7
-14,
-14,
-14,
-14,
-16
-32
-16
-32
fCLK
CLKIN Duty Cycle
Min
Typ
Max
Units
1.75
100 kHz
-
6.4
MHz
MHz
1.75
1
100 kHz
100 kHz
-
4
2
MHz
MHz
MHz
MHz
40
-
60
%
Rise Times:
Any Digital Input
Any Digital Output
trise
-
20
1.0
-
µs
ns
Fall Times:
Any Digital Input
Any Digital Output
tfall
-
20
1.0
-
µs
ns
thpw
1/fCLK+50
-
tc
ns
tc
49/fCLK+50
57/fCLK
65/fCLK
-
53/fCLK+235
61/fCLK+235
69/fCLK+235
ns
ns
ns
tdd
-
40
100
ns
tepw
4/fCLK-20
-
-
ns
HOLD Pulse Width
Conversion Time:
CS5012A
CS5014
CS5016
Data Delay Time
EOC Pulse Width
(Note 11)
Set Up Times:
CAL, INTRLV to CS Low
A0 to CS and RD Low
tcs
tas
20
20
10
10
-
ns
ns
Hold Times:
CS or RD High to A0 Invalid
CS High to CAL, INTRLV Invalid
tah
tch
50
50
30
30
-
ns
ns
Access Times:
CS Low to Data Valid
tca
-
90
120
ns
RD Low to Data Valid
tra
-
90
120
ns
tfd
-
90
110
ns
tpwl
tpwh
-
2/fCLK
2/fCLK
-
ns
ns
Output Float Delay:
CS or RD High to Output Hi-Z
Serial Clock
Pulse Width Low
Pulse Width High
Set Up Times:
SDATA to SCLK Rising
tss
2/fCLK-50
2/fCLK
-
ns
Hold Times:
SCLK Rising to SDATA
tsh
2/fCLK-100
2/fCLK
-
ns
Notes: 11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high
within 4 CLKIN cycles from the start of a data read operation or a conversion cycle.
82-14
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
t rise
t fall
90%
90%
10%
10%
Rise and Fall Times
t pwl
t pwh
SCLK
t sh
t ss
SDATA
Serial Output Timing
t ca
CS
t ra
RD
t ah
t as
A0
t fd
D0-D15
Hi-Z
Hi-Z
t cs
t ch
CAL, INTRLV
Read and Calibration Control Timing
t hpw
HOLD
t epw
tc
EOC
t dd
Output Data
LAST CONVERSION DATA VALID
NEW DATA VALID
Conversion Timing
DS14F9
DS14F8
2-159
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%)
Parameter
Symbol
Min
Typ
Max
Units
High-Level Input Voltage
VIH
2.0
-
-
V
Low-Level Input Voltage
VIL
-
-
0.8
V
High-Level Output Voltage
(Note 12)
VOH
(VD+) - 1.0V
-
-
V
Low-Level Output Voltage
Iout = 1.6mA
VOL
-
-
0.4
V
Input Leakage Current
Iin
-
-
10
µA
3-State Leakage Current
IOZ
-
-
±10
µA
Digital Output Pin Capacitance
Cout
-
9
-
pF
Notes: 12. Iout = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA).
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 13)
Parameter
DC Power Supplies:
Positive Digital
Negative Digital
Positive Analog
Negative Analog
Analog Reference Voltage
Symbol
Min
Typ
Max
Units
VD+
VDVA+
VA-
4.5
-4.5
4.5
-4.5
5.0
-5.0
5.0
-5.0
VA+
-5.5
5.5
-5.5
V
V
V
V
VREF
2.5
4.5
(VA+) - 0.5
V
Analog Input Voltage:
(Note 14)
AGND
VREF
Unipolar
VAIN
VAIN
-VREF
VREF
Bipolar
Notes: 13. All voltages with respect to ground.
14. The CS5012A/14/16 can accept input voltages up to the analog supplies (VA+ and VA-).
It will output all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode
and -VREF in bipolar mode.
V
V
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with repect to ground.)
WARNING: Operation at or beyond these limits may reult in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter
DC Power Supplies:
Positive Digital
Negative Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supplies
Analog Input Voltage
Symbol
Min
Max
Units
(Note 15)
VD+
VDVA+
VA-
-0.3
0.3
-0.3
0.3
6.0
-6.0
6.0
-6.0
V
V
V
V
(Note 16)
Iin
-
±10
mA
VINA
(VA-) - 0.3
(VA+) + 0.3
V
VIND
-0.3
(VA+) + 0.3
V
TA
-55
125
°C
-65
150
°C
(AIN and VREF pins)
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
Tstg
Notes: 15. In addition, VD+ should not be greater than (VA+) + 0.3V.
16. Transient currents of up to 100 mA will not cause SCR latch-up.
10
2-16
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
AIN
VREF
AGND
C
C/2
CS5012A: Bit 11
CS5014: Bit 13
CS5016: Bit 15
MSB
Bit 10
Bit 12
Bit 14
C/4
C/8
Bit 9
Bit 11
Bit 13
Bit 8
Bit 10
Bit 12
C
tot
S1
C/X
CS5012A X = 2048 C/X
CS5014 X = 8192
CS5016 X = 32768
Bit 0
LSB
Dummy
= C + C/2 + C/4 + ... + C/X
Figure 1. Charge Redistribution DAC
THEORY OF OPERATION
The CS5012A/14/16 family utilize a successive
approximation conversion technique. The analog
input is successively compared to the output of a
D/A converter controlled by the conversion algorithm. Successive approximation begins by
comparing the analog input to the DAC output
which is set to half-scale (MSB on, all other bits
off). If the input is found to be below half-scale,
the MSB is reset to zero and the input is compared to one-quarter scale (next MSB on, all
others off). If the input were above half-scale, the
MSB would remain high and the next comparison would be at three-quarters of full scale. This
procedure continues until all bits have been exercised.
A unique charge redistribution architecture is
used to implement the successive approximation
When the conversion command is issued, switch
S1 opens as shown in Figure 2b. This traps
charge Qin on the comparator side of the capacitor array and creates a floating node at the
comparator’s input. The conversion algorithm operates on this fixed charge, and the signal at the
analog input pin is ignored. In effect, the entire
DAC capacitor array serves as analog memory
D . C tot
S1
AIN
algorithm. Instead of the traditional resistor network, the DAC is an array of binary-weighted
capacitors. All capacitors in the array share a
common node at the comparator’s input. Their
other terminals are capable of being connected to
AIN, AGND, or VREF (Figure 1). When the device is not calibrating or converting, all capacitors
are tied to AIN forming Ctot. Switch S1 is closed
and the charge on the array, Qin, tracks the input
signal Vin (Figure 2a).
Qin
Qin
+
Vin
-
C tot
S1
VREF
To MCU
AGND
+
Vfn
-
To MCU
(1-D) C tot
-Q in = Vin C tot
Figure 2a. Tracking Mode
DS14F9
DS14F8
V in
D = VREF for V fn = 0V
Figure 2b. Convert Mode
11
2-17
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
during conversion much like a hold capacitor in a
sample/hold amplifier.
Auto-zeroing enhances power supply rejection at
frequencies well below the conversion rate.
The conversion consists of manipulating the free
plates of the capacitor array to VREF and AGND
to form a capacitive divider. Since the charge at
the floating node remains fixed, the voltage at
that point depends on the proportion of capacitance tied to VREF versus AGND. The
successive-approximation algorithm is used to
find the proportion of capacitance, termed D in
Figure 2b, which when connected to the reference will drive the voltage at the floating node
(Vfn) to zero. That binary fraction of capacitance
represents the converter’s digital output.
To achieve complete accuracy from the DAC, the
CS5012A/14/16 use a novel self-calibration
scheme. Each bit capacitor, shown in Figure 1,
actually consists of several capacitors which can
be manipulated to adjust the overall bit weight.
An on-chip microcontroller adjusts the subarrays
to precisely ratio the bits. Each bit is adjusted to
just balance the sum of all less significant bits
plus one dummy LSB (for example, 16C = 8C +
4C + 2C + C + C). Calibration resolution for the
array is a small fraction of an LSB resulting in
nearly ideal differential and integral linearity.
This charge redistribution architecture easily supports bipolar input ranges. If half the capacitor
array (the MSB capacitor) is tied to VREF rather
than AIN in the track mode, the input range is
doubled and is offset half-scale. The magnitude
of the reference voltage thus defines both positive
and negative full-scale (-VREF to +VREF), and
the digital code is an offset binary representation
of the input.
DIGITAL CIRCUIT CONNECTIONS
Calibration
Master Clock
The ability of the CS5012A/14/16 to convert accurately clearly depends on the accuracy of their
comparator and DAC. The CS5012A/14/16 utilize an "auto-zeroing" scheme to null errors
introduced by the comparator. All offsets are
stored on the capacitor array while in the track
mode and are effectively subtracted from the input signal when a conversion is initiated.
Sampling
Clock
The CS5012A/14/16 can be applied in a wide variety of master clock, sampling, and calibration
conditions which directly affect the devices’ conversion time and throughput. The devices also
feature on-chip 3-state output buffers and a complete interface for connecting to 8-bit and 16-bit
digital systems. Output data is also available in
serial format.
The CS5012A/14/16 operate from a master clock
(CLKIN) which can be externally supplied or internally generated. The internal oscillator is
activated by externally tying the CLKIN input
low. Alternatively, the CS5012A/14/16 can be
synchronized to the external system by driving
the CLKIN pin with a TTL or CMOS clock signal.
HOLD
HOLD
EOT
CS5012A/14/16
Master Clock
(Optional)
CLKIN
Figure 3a. Asynchronous Sampling
12
2-18
CS5012A/14/16
Master Clock
(Optional)
CLKIN
Figure 3b. Synchronous Sampling
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
All calibration, conversion, and throughput times
directly scale to CLKIN frequency. Thus,
throughput can be precisely controlled and/or
maximized using an external CLKIN signal. In
contrast, the CS5012A/14/16’s internal oscillator
will vary from unit-to-unit and over temperature.
The CS5012A/14/16 can typically convert with
CLKIN as low as 10 kHz at room temperature.
Initiating Conversions
A falling transition on the HOLD pin places the
input in the hold mode and initiates a conversion
cycle. Upon completion of the conversion cycle,
the CS5012A/14/16 automatically return to the
track mode. In contrast to systems with separate
track-and-holds and A/D converters, a sampling
clock can simply be connected to the HOLD input (Figure 3a). The duty cycle of this clock is
not critical. It need only remain low at least one
CLKIN cycle plus 50 ns, but no longer than the
minimum conversion time or an additional conversion cycle will be initiated with inadequate
time for acquisition.
Microprocessor-Controlled Operation
Sampling and conversion can be placed under
microprocessor control (Figure 4) by simply gating the devices’ decoded address with the write
strobe for the HOLD input. Thus, a write cycle to
the CS5012A/14/16’s base address will initiate a
conversion. However, the write cycle must be to
RD
Upon completing a conversion cycle and returning to the track mode, the CS5012A/14/16
require time to acquire the analog input signal
before another conversion can be initiated. The
acquisition time is specified as six CLKIN cycles
plus 2.25 µs (1.32 µs for the CS5012A -7 version
only). This adds to the conversion time to define
the converter’s maximum throughput. The conversion time of the CS5012A/14/16, in turn,
depends on the sampling, calibration, and CLKIN
conditions.
RD
RD
WR
HOLD
ADDR VALID
AN
Addr
Dec
CS
CS5012A/14/16
A2
CAL
A1
INTRLV
A0
A0
Figure 4a. Conversions Asynchronous to CLKIN
DS14F9
DS14F8
Conversion Time/Throughput
HOLD
ADDR VALID
A3
The calibration control inputs, CAL, and
INTRLV are inputs to a set of transparent latches.
These signals are internally latched by CS returning high. They must be in the appropriate state
whenever the chip is selected during a read or
write cycle. Address lines A1 and A2 are shown
connected to CAL and INTRLV in Figure 4 placing calibration under microprocessor control as
well. Thus, any read or write cycle to the
CS5012A/14/16’s base address will initiate or terminate calibration. Alternatively, A0, INTRLV,
and CAL may be connected to the microprocessor data bus.
RD
CONCLK
Address
Bus
the odd address (A0 high) to avoid initiating a
software controlled reset (see Reset below).
AN
Addr
Dec
Address
Bus
A3
CS
CS5012A/14/16
A2
CAL
A1
INTRLV
A0
A0
Figure 4b. Conversions under Microprocessor Control
13
2-19
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
1 / Throughput
HOLD
Input
HOLD
Input
Conversion
EOC
Output
1 / Throughput
(64 + N cycles)
Conversion
(49 + N cycles)
EOC
Output
Acquisition
*
Acquisition
(15 cycles)
EOT
Output
EOT
Output
* Dashed line: CS & RD = 0
Solid line: See Figure 9
Synchronization Uncertainty (4 cycles)
CS5012A N = 0
CS5014 N = 8
CS5016 N = 16
Figure 5b. Synchronous (Loopback Mode)
Figure 5a. Asynchronous Sampling (External Clock)
Asynchronous Sampling
Synchronous Sampling
The CS5012A/14/16 internally operate from a
clock which is delayed and divided down from
CLKIN (fCLK/4). If sampling is not synchronized
to this internal clock, the conversion cycle may
not begin until up to four clock cycles after
HOLD goes low even though the charge is
trapped immediately. In this asynchronous mode
(Figure 3a), the four clock cycles add to the minimum 49, 57 and 65 clock cycles (for the
CS5012A/14/16 respectively) to define the maximum conversion time (see Figure 5a and
Table 1).
To achieve maximum throughput, sampling can
be synchronized with the internal conversion
clock by connecting the End-of-Track (EOT) output to HOLD (Figure 3b). The EOT output falls
15 CLKIN cycles after EOC indicating the analog input has been acquired to the
CS5012A/14/16’s specified accuracy. The EOT
output is synchronized to the internal conversion
clock, so the four clock cycle synchronization uncertainty is removed yielding throughput at
[1/64]fCLK for the CS5012A, [1/72]fCLK for
CS5014 and [1/80]fCLK for CS5016 where fCLK
is the CLKIN frequency (see Figure 5b and Table 1).
Conversion Time
Min
Sampling Mode
Throughput Time
Max
Min
Max
CS5012A
Synchronous (Loopback)
49 t clk
-7
49 t clk
49 t clk
Asynchronous
-12,-24
49 t clk
53 t clk +
53 t clk +
64 t clk
235 ns
N/A
235 ns
N/A
64 t clk
59 t clk +
59 t clk +
1.32 µs
2.25 µs
CS5014
Synchronous (Loopback)
57 t clk
Asynchronous
57 t clk
57 t clk
61 t clk +
235 ns
72 t clk
72 t clk
N/A
67 t clk +
2.25 µs
CS5016
Synchronous (Loopback)
65 t clk
Asynchronous
65 t clk
65 t clk
69 t clk +
235 ns
80 t clk
80 t clk
N/A
75 t clk +
2.25 µs
Table 1. Conversion and Throughput Times (tclk = Master Clock Period)
14
2-20
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
Also, the CS5012A/14/16’s internal RC oscillator
exhibits jitter (typically ± 0.05% of its period),
which is high compared to crystal oscillators. If
the CS5012A/14/16 is configured for synchronous sampling while operating from its internal
oscillator, this jitter will directly affect sampling
purity. The user can obtain best sampling purity
while synchronously sampling by using an external crystal-based clock.
Reset
Upon power up, the CS5012A/14/16 must be reset to guarantee a consistent starting condition
and initially calibrate the devices. Due to the
CS5012A/14/16’s low power dissipation and low
temperature drift, no warm-up time is required
before reset to accommodate any self-heating effects. However, the voltage reference input
should have stabilized to within 5%, 1% or
0.25% of its final value, for the CS5012A/14/16
respectively, before RST falls to guarantee an accurate calibration. Later, the CS5012A/14/16 may
be reset at any time to initiate a single full calibration. Reset overrides all other functions. If
reset, the CS5012A/14/16 will clear and initiate a
new calibration cycle mid-conversion or mid-calibration.
+5V
R
RST
C
CS5012A/14/16
Figure 6. Power-on Reset Circuit
eliminate the possibility of inadvertent software
reset. The EOC output remains high throughout
the calibration operation and will fall upon its
completion. It can thus be used to generate an
interrupt indicating the CS5012A/14/16 is ready
for operation. While calibrating, the HOLD input
is ignored until EOC falls. After EOC falls, six
CLKIN cycles plus 2.25 µs (1.32 µs for the
CS5012A -7 version only) must be allowed for
signal acquisition before HOLD is activated. Under microprocessor-independent operation (CS,
RD low; A0 high) the CS5014’s and CS5016’s
EOC output will not fall at the completion of the
calibration cycle, but EOT will fall 15 CLKIN
cycles later.
Initiating Calibration
Resets can be initiated in hardware or software.
The simplest method of resetting the
CS5012A/14/16 involves strobing the RST pin
high for at least 100 ns. When RST is brought
high all internal logic clears. When it returns low,
a full calibration begins which takes 58,280
CLKIN cycles for the CS5012A (approximately
9.1 ms with a 6.4 MHz clock) and 1,441,020
CLKIN cycles for the CS5016 and CS5014.
(approximately 360 ms with a 4 MHz
CLKIN). A simple power-on reset circuit can be
built using a resistor and capacitor, and a
Schmitt-trigger inverter to prevent oscillation (see
Figure 6). The CS5012A/14/16 can also be reset
in software when under microprocessor control.
The CS5012A/14/16 will reset whenever CS, A0,
and HOLD are taken low simultaneously. See the
Microprocessor Interface section (below) to
DS14F9
DS14F8
All modes of calibration can be controlled in
hardware or software. Accuracy can thereby be
insured at any time or temperature throughout operating life. After initial calibration at power-up,
the CS5012A/14/16’s charge-redistribution design
yields better temperature drift and more graceful
aging than resistor-based technologies, so calibration is normally only required once, after
power-up.
The first mode of calibration, reset, results in a
single full calibration cycle. The second type of
calibration, "burst" cal, allows control of partial
calibration cycles. Due to an unforeseen condidtion inside the part, asynchronous termination
of calibration may result in a sub-optimal result.
Burst cal should not be used.
15
2-21
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
The reset calibration always works perfectly, and
should be used instead of burst mode. The
CS5012A/14/16’s very low drift
over temperature means that, under most circumstances, calibration will only need to be
performed at power-up, using reset.
The CS5012A/14/16 feature a background calibration mode called "interleave." Interleave
appends a single calibration experiment to each
conversion cycle and thus requires no dead time
for calibration. The CS5012A/14/16 gathers data
between conversions and will adjust its transfer
function once it completes the entire sequence of
experiments (one calibration cycle per 2,014 conversions in the CS5012A and one calibration per
72,051 conversions in the CS5014 and CS5016).
This is initiated by bringing both the INTRLV
input and CS low (or hard-wiring INTRLV low),
interleave extends the CS5012A/14/16’s effective
conversion time by 20 CLKIN cycles. Other than
reduced throughput, interleave is totally transparent to the user. Interleave calibration should not
be used intermittently.
The fact that the CS5012A/14/16 offer several
calibration modes is not to imply that the devices
need to be recalibrated often. The devices are
very stable in the presence of large temperature
changes. Tests have indicated that after using a
single reset calibration at 25 °C most devices exhibit very little change in offset or gain when
exposed to temperatures from -55 to +125 °C.
The data indicated 30 ppm as the typical worst
case total change in offset or gain over this temperature range. Differential linearity remained
virtually unchanged. System error sources outside
of the A/D converter, whether due to changes in
16
2-22
temperature or to long-term aging, will generally
dominate total system error.
Microprocessor Interface
The CS5012A/14/16 feature an intelligent microprocessor interface which offers detailed status
information and allows software control of the
self-calibration functions. Output data is available
in either 8-bit or 16-bit formats for easy interfacing to industry-standard microprocessors.
Strobing both CS and RD low enables the
CS5012A/14/16’s 3-state output buffers with
either output data or status information depending
on the status of A0. An address bit can be connected to A0 as shown in Figure 4b thereby
memory mapping the status register and output
data. Conversion status can be polled in software
by reading the status register (CS and RD strobed
low with A0 low), and masking status bits S0-S5
and S7 (by logically AND’ing the status word
with 01000000) to determine the value of S6.
Similarly, the software routine can determine
calibration status using other status bits (see Table 2). Care must be taken not to read the status
register (A0 low) while HOLD is low, or a software reset will result (see Reset above).
Alternatively, the End-of-Convert (EOC) output
can be used to generate an interrupt or drive a
DMA controller to dump the output directly into
memory after each conversion. The EOC pin falls
as each conversion cycle is completed and data is
valid at the output. It returns high within four
CLKIN cycles of the first subsequent data read
operation or after the start of a new conversion
cycle.
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
PIN
D0
STATUS BIT
S0
STATUS
END OF CONVERSION
D1
D2
S1
S2
RESERVED
LOW BYTE/HIGH BYTE
D3
S3
END OF TRACK
D4
D5
D6
D7
S4
S5
S6
S7
RESERVED
TRACKING
CONVERTING
CALIBRATING
DEFINITION
Falls upon completion of a conversion,
and returns high on the first subsequent read.
Reserved for factory use.
When data is to be read in an 8-bit format (BW=0),
indicates which byte will appear at the output next.
When low, indicates the input has been acquired to
the devices specified accuracy.
Reserved for factory use.
High when the device is tracking the input.
High when the device is converting the held input.
High when the device is calibrating.
Table 2. Status Pin Definitions
version finishes. Status bit S2 indicates which
byte will appear on the next data read operation.
To interface with a 16-bit data bus, the BW input
to the CS5012A/14/16 should be held high and
all data bits (12, 14 and 16 for the CS5012A,
CS5014 and CS5016 respectively) read in parallel on pins D4-D15 (CS5012A), D2-D15
(CS5014), or D0-D15 (CS5016). With an 8-bit
bus, the converter’s result must be read in two
portions. In this instance, BW should be held low
and the 8 MSB’s obtained on the first read cycle
following a conversion. The second read cycle
will yield the remaining LSB’s (4, 6 or 8 for the
CS5012A/14/16 respectively) with 4, 2 or 0 trailing zeros. Both bytes appear on pins D0-D7. The
upper/lower bytes of the same data will continue
to toggle on subsequent reads until the next con-
Status
(A0=0)
CS5012A
Data
(A0=1)
D15 D14 D13 D12 D11 D10
X
X
The CS5012A/14/16 internally buffer their output
data, so data can be read while the devices are
tracking or converting the next sample. Therefore,
retrieving the converters’ digital output requires
no reduction in ADC throughput. Enabling the 3state outputs while the CS5012A/14/16 is
converting will not introduce conversion errors.
Connecting CMOS logic to the digital outputs is
recommended.
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
S7
S6
S5
S4
S3
S2
S1
S0
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
B11 B10
B9
CS5014
B13
B12
B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
CS5016
B15 B14
B13 B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
CS5012A
X
X
X
X
X
X
X
X
B11
B3
B10
B2
B9
B1
CS5014
X
X
X
X
X
X
X
X
B13
B5
B12
B4
CS5016
X
X
X
X
X
X
X
X
B15
B7
B14
B6
"X" Denotes High Impedance Output
B8
B0
B7
0
B6
0
B5
0
B4
0
B11 B10
B3 B2
B9
B1
B8
B0
B7
0
B6
0
B13 B12
B5 B4
B11 B10
B3 B2
B9
B1
B8
B0
8- or 16-Bit
Data Bus
16-Bit Bus
(BW=1)
8-Bit Bus
(BW=0)
Figure 7. CS5012A/14/16 Data Format
DS14F9
DS14F8
17
2-23
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
Microprocessor Independent Operation
The CS5012A/14/16 can be operated in a standalone mode independent of intelligent control. In
this mode, CS and RD are hard-wired low. This
permanently enables the 3-state output buffers
and allows transparent latch inputs (CAL and
INTRLV) to be active. A free-running condition
is established when BW is tied high, CAL is tied
low, and HOLD is continually strobed low or tied
to EOT. The CS5012A/14/16’s EOC output can
be used to externally latch the output data if desired. With CS and RD hard-wired low, EOC will
strobe low for four CLKIN cycles after each conversion. Data will be unstable up to 100 ns after
EOC falls, so it should be latched on the rising
edge of EOC.
+5V
INTRLV
BW
A0
Sampling
Clock
RST
Reset
EOC
Latching
Output
D15
HOLD
CS
RD
CAL
CS5012A
CS5014
CS5016
12-Bit
Data
Out
D4
Figure 8. Microprocessor-Independent Connections
Serial Output
All successive-approximation A/D converters derive their digital output serially starting with the
MSB. The CS5012A/14/16 present each bit to the
SDATA pin four CLKIN cycles after it is derived
and can be latched using the serial clock output,
SCLK. Just subsequent to each bit decision
SCLK will fall and return high once the bit information on SDATA has stabilized. Thus, the rising
edge of the SCLK output should be used to clock
the data from the CS5012A/14/16 (See Figure 9).
ANALOG CIRCUIT CONNECTIONS
Most popular successive-approximation A/D converters generate dynamic loads at their analog
18
2-24
connections. The CS5012A/14/16 internally buffer all analog inputs (AIN, VREF, and AGND) to
ease the demands placed on external circuitry.
However, accurate system operation still requires
careful attention to details at the design stage regarding source impedances as well as grounding
and decoupling schemes.
Reference Considerations
An application note titled "Voltage References for
the CS501X Series of A/D Converters" is available for the CS5012A/14/16. In addition to
working through a reference circuit design example, it offers several built-and-tested reference
circuits.
During conversion, each capacitor of the calibrated capacitor array is switched between VREF
and AGND in a manner determined by the successive-approximation algorithm. The charging
and discharging of the array results in a current
load at the reference. The CS5012A/14/16 include an internal buffer amplifier to minimize the
external reference circuit’s drive requirement and
preserve the reference’s integrity. Whenever the
array is switched during conversion, the buffer is
used to pre-charge the array thereby providing
the bulk of the necessary charge. The appropriate
array capacitors are then switched to the unbuffered VREF pin to avoid any errors due to offsets
and/or noise in the buffer.
The external reference circuitry need only provide the residual charge required to fully charge
the array after pre-charging from the buffer. This
creates an ac current load as the CS5012A/14/16
sequence through conversions. The reference circuitry must have a low enough output impedance
to drive the requisite current without changing its
output voltage significantly. As the analog input
signal varies, the switching sequence of the internal capacitor array changes. The current load on
the external reference circuitry thus varies in response with the analog input. Therefore, the
external reference must not exhibit significant
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
peaking in its output impedance characteristic at
signal frequencies or their harmonics.
A large capacitor connected between VREF and
AGND can provide sufficiently low output impedance at the high end of the frequency
spectrum, while almost all precision references
exhibit extremely low output impedance at dc.
The magnitude of the current load on the external
reference circuitry will scale to the CLKIN frequency. At full speed, the reference must supply a
maximum load current of 10 µA peak-to-peak
(1 µA typical). For the CS5012A an output impedance of 15 Ω will therefore yield a maximum
error of 150 mV. With a 2.5V reference and LSB
size of 600 mV, this would insure better than 1/4
LSB accuracy. A 1 µF capacitor exhibits an imCS5016: 60
CS5014: 52
CS5012A: 44
CLKIN
62
54
46
64
56
48
66
58
50
68
60
52
70
62
54
72
64
56
74
66
58
pedance of less than 15 Ω at frequencies greater
than 10 kHz. Similarly, for the CS5014 with a
4.5V reference (275µV/LSB), better than
1/4 LSB accuracy can be insured with an output
impedance of 4Ω or less (maximum error of
40 µV). A 2.2 µF capacitor exhibits an impedance of less than 4Ω at frequencies greater than
5kHz. For the CS5016 with a 4.5V reference
(69µV/LSB), better than 1/4 LSB accuracy can
be insured with an output impedance of less than
2Ω (maximum error of 20 µV). A 20 µF capacitor exhibits an impedance of less than 2Ω at
frequencies greater than 16 kHz. A high-quality
tantalum capacitor in parallel with a smaller ceramic capacitor is recommended.
76
68
60
78
70
62
80/0
72/0
64/0
2
2
2
4
4
4
6
6
6
8
8
8
10
10
10
12
12
12
EOC
Status
LSB
Determined
Coarse Charge
EOT
MSB - 1
MSB - 2
MSB
Determined Determined Determined
Fine Charge
t
HOLD
t
d
d
SCLK
SDATA
LSB+2
LSB+1
LSB
MSB
MSB - 1
Notes: 1. Synchronous (loopback) mode is illustrated. After EOC falls the converter goes into coarse charge mode for
6 CLKIN cycles, then to fine charge mode for 9 cycles, then EOT falls. In loopback mode, EOT trips HOLD
which captures the analog sample. Conversion begins on the next rising edge of CLKIN. If operated asynchronously, EOT will remain low until after HOLD is taken low. When HOLD occurs the analog sample is captured
immediately, but conversion may not begin until four CLKIN cycles later. EOT will return high
when conversion begins.
2. Timing delay td (relative to CLKIN) can vary between 135 ns to 235 ns over the military temperature range
and over ± 10% supply variation
3. EOC returns high in 4 CLKIN cycles if A0 = 1 and CS = RD = 0 (Microprocessor Independent Mode);
within 4 CLKIN cycles after a data read (Microprocessor Mode); or 4 CLKIN cycles after HOLD = 0
is recognized on a rising edge of CLKIN/4.
Figure 9. Serial Output Timing
DS14F9
DS14F8
19
2-25
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
+V ee
Peaking in the reference’s output impedance can
occur because of capacitive loading at its output.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capacitors (Figure 10). The equation in Figure 10 can
be used to help calculate the optimum value of R
for a particular reference. The term "fpeak" is the
frequency of the peak in the output impedance of
the reference before the resistor is added.
Vref
C1
1.0
µF
0.1 µF
Internal Charge Error (LSB's)
CS5014
+200
+50
+12.5
0
0
0
VREF
32
REFBUF
34
VA-
R
CS5012A
CS5014
CS5016
-5V
The CS5012A/14/16 can operate with a wide
range of reference voltages, but signal-to-noise
performance is maximized by using as wide a
signal range as possible. The recommended reference voltage is between 2.5 and 4.5 V for the
CS5012A and 4.5 V for the CS5014/16. The
CS5012A/14/16 can actually accept reference
voltages up to the positive analog supply. However, the buffer’s offset may increase as the
reference voltage approaches VA+ thereby increasing external drive requirements at VREF. A
4.5V reference is the maximum reference voltage
recommended. This allows 0.5V headroom for
the internal reference buffer. Also, the buffer enlists the aid of an external 0.1 µF ceramic
capacitor which must be tied between its output,
REFBUF, and the negative analog supply, VA-. For
more information on references, consult the applicaCS5016
C2
0.01
µF
31
1
2π (C1 + C2) fpeak
Figure 10. Reference Connections
R =
tion note: Voltage References for the CS501X Series of A/D Converters. For an example of using
the CS5012A/14/16 with a 5 volt reference, see
the application note: A Collection of Application
Hints for the CS501X Series of A/D Converters.
Analog Input Connection
The analog input terminal functions similarly to
the VREF input after each conversion when
switching into the track mode. During the first
six CLKIN cycles in the track mode, the buffered
version of the analog input is used for pre-charging the capacitor array. An additional period is
required for fine-charging directly from AIN to
CS5012A
Pre-Charge
-200
-50
-12.5
-400
-100
-25.0
0.5
1.0
Fine-Charge
1.5
2.0
2.5
Acquisition Time (us)
(Delay from EOC)
Figure 11. Internal Acquisition Time
20
2-26
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
obtain the specified accuracy. Figure 11 illustrates
this operation. During pre-charge the charge on
the capacitor array first settles to the buffered version of the analog input. This voltage is offset
from the actual input voltage. During fine-charge,
the charge then settles to the accurate unbuffered
version.
The acquisition time of the CS5012A/14/16 depends on the CLKIN frequency. This is due to a
fixed pre-charge period. For instance, operating
the CS5012A, CS5014, or CS5016 -16
version with an external 4 MHz CLKIN results in
a 3.75 µs acquisition time: 1.5 µs for pre-charging
(6 clock cycles) and 2.25 µs for fine-charging.
Fine-charge settling is specified as a maximum of
2.25 µs for an analog source impedance of less
than 200 Ω. (For the CS5012A -7 version it is
specified as 1.32 µs.) In addition, the comparator
requires a source impedance of less than 400 Ω
around 2 MHz for stability, which is met by practically all bipolar op amps. Large dc source
impedances can be accommodated by adding capacitance from AIN to ground (typically 200 pF)
to decrease source impedance at high frequencies.
However, high dc source resistances will increase
the input’s RC time constant and extend the nec-
CS5012A/14/16
HOLD
Input
Convert Channel N
essary acquisition time. For more information on
input applications, consult the application note:
Input Buffer Amplifiers for the CS501X Family of
A/D Converters.
During the first six clock cycles following a conversion (pre-charge) in unipolar mode, the
CS5012A is capable of slewing at 20V/µs and the
CS5014/16 can slew at 5V/µs. In bipolar mode,
only half the capacitor array is connected to the
analog input so the CS5012A can slew at 40V/µs,
and the CS5014/16 can slew at 10V/µs. After the
first six CLKIN cycles, the CS5012A will slew at
1.25V/µs in unipolar mode and 3.0V/µs in bipolar
mode, and the CS5014/16 will slew at 0.25V/µs
in unipolar mode and 0.5V/µs in bipolar mode.
Acquisition of fast slewing signals (step functions) can be hastened if the step occurs during or
immediately following the conversion cycle. For
instance, channel selection in multiplexed applications should occur while the CS5012A/14/16 is
converting (see Figure 12). Multiplexer settling is
thereby removed from the overall throughput
equation, and the CS5012A/14/16 can convert at
full speed.
Convert Channel N+1
CS5012A/14/16
EOC
Output
MUX
Address
Address N
CS5012A/14/16
Analog
Input
Address N + 1
MUX Settling
to Channel N + 1
Address N + 2
Address N + 3
MUX Settling
to Channel N + 2
Figure 12. Pipelined MUX Input Channels
DS14F9
DS14F8
21
2-27
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
Analog Input Range/Coding Format
The reference voltage directly defines the input
voltage range in both the unipolar and bipolar
configurations. In the unipolar configuration
(BP/UP low), the first code transition occurs
0.5 LSB above AGND, and the final code transition occurs 1.5 LSB’s below VREF. Coding is in
straight binary format. In the bipolar configuration (BP/UP high), the first code transition occurs
0.5 LSB above -VREF and the last transition occurs 1.5 LSB’s below +VREF. Coding is in an
offset-binary format. Positive full scale gives a
digital output of all ones, and negative full scale
gives a digital output of all zeros.
The BP/UP mode pin may be switched after calibration without having to recalibrate the
converter. However, the BP/UP mode should be
changed during the previous conversion cycle,
that is, between HOLD falling and EOC falling.
If BP/UP is changed at any other time, one
dummy conversion cycle must be allowed for
proper acquisition of the input.
Grounding and Power Supply Decoupling
The digital and analog supplies to the
CS5012A/14/16 are pinned out separately to
minimize coupling between the analog and digital
sections of the chip. All four supplies should be
decoupled to their respective grounds using
0.1 µF ceramic capacitors. If significant low-frequency noise is present on the supplies, 1 µF
tantalum capacitors are recommended in parallel
with the 0.1 µF capacitors.
The positive digital power supply of the
CS5012A/14/16 must never exceed the positive
analog supply by more than a diode drop or the
device could experience permanent damage. If
the two supplies are derived from separate
sources, care must be taken that the analog supply comes up first at power-up. The system
connection diagram in Figure 36 shows a decoupling scheme which allows the CS5012A/14/16
to be powered from a single set of ± 5V rails.
As with any high-precision A/D converter, the
CS5012A/14/16 require careful attention to
grounding and layout arrangements. However, no
unique layout issues must be addressed to properly apply the device.
The CS5012A/14/16 use the analog ground connection, AGND, only as a reference voltage. No
dc power currents flow through the AGND connection, and it is completely independent of
DGND. However, any noise riding on the AGND
input relative to the system’s analog ground will
induce conversion errors. Therefore, both the analog input and reference voltage should be referred
to the AGND pin, which should be used as the
entire system’s analog ground reference point.
22
2-28
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
CS5012A/14/16 PERFORMANCE
Power Supply Rejection
The CS5012A/14/16’s power supply rejection
performance is enhanced by the on-chip self-calibration and an "auto-zero" process. Drifts in
power supply voltages at frequencies less than the
calibration rate have negligible effect on the
CS5012A/14/16’s accuracy. This is because the
CS5012A/14/16 adjust their offset to within a
small fraction of an LSB during calibration.
Above the calibration frequency the excellent
power supply rejection of the internal amplifiers
is augmented by an auto-zero process. Any
offsets are stored on the capacitor array and are
effectively subtracted once conversion is initiated.
Figure 13 shows power supply rejection of the
CS5012A/14/16 in the bipolar mode with the
analog input grounded and a 300 mVp-p ripple
applied to each supply. Power supply rejection
improves by 6 dB in the unipolar mode.
The plot in Figure 13 shows worst-case rejection
for all combinations of conversion rates and input
conditions in the bipolar mode.
90
Power Supply Rejection (dB)
80
Differential Nonlinearity
One source of nonlinearity in A/D converters is
bit weight errors. These errors arise from the deviation of bits from their ideal binary-weighted
ratios, and lead to nonideal widths for each code.
If DNL errors are large, and code widths shrink
to zero, it is possible for one or more codes to be
entirely missing. The CS5012A/14/16 calibrate
all bits in the capacitor array to a small fraction
of an LSB resulting in nearly ideal DNL. Histogram plots of typical DNL of the CS5012A/14/16
can be seen in Figures 14, 15, 16.
A histogram test is a statistical method of deriving an A/D converter’s differential nonlinearity. A
ramp is input to the A/D and a large number of
samples are taken to insure a high confidence
level in the test’s result. The number of occurrences for each code is monitored and stored. A
perfect A/D converter would have all codes of
equal size and therefore equal numbers of occurrences. In the histogram test a code with the
average number of occurrences will be considered ideal (DNL = 0). A code with more or less
occurrences than average will appear as a DNL
of greater or less than zero LSB. A missing code
has zero occurrences, and will appear as a DNL
of -1 LSB.
70
Integral Nonlinearity
60
Integral Nonlinearity (INL; also termed Relative
Accuracy or just Nonlinearity) is defined as the
deviation of the transfer function from an ideal
straight line. Bows in the transfer curve generate
harmonic distortion. The worst-case condition of
bit-weight errors (DNL) has traditionally also defined the point of maximum INL.
50
40
30
20
1 kHz
10 kHz
100 kHz
1 MHz
Power Supply Ripple Frequency
Figure 13. Power Supply Rejection
DS14F9
DS14F8
Bit-weight errors have a drastic effect on a converter’s ac performance. They can be analyzed as
step functions superimposed on the input signal.
23
2-29
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
+1
DNL (LSB)
+1/2
0
-1/2
-1
0
2,048
4,095
Codes
F igur e 14. C S5012A Differ ential Nonlinear ity Plot
+1
DNL (LSB)
+1/2
0
-1/2
-1
0
8,192
16,383
Codes
F igur e 15. C S5014 Differ ential Nonlinear ity Plot
+1
DNL (LSB)
+1/2
0
-1/2
-1
0
32,768
65,535
Codes
F igur e 16. C S5016 Differ ential Nonlinear ity Plot
24
2-30
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
Since bits (and their errors) switch in and out
throughout the transfer curve, their effect is signal dependent. That is, harmonic and
intermodulation distortion, as well as noise, can
vary with different input conditions. Designing a
system around characterization data is risky since
transfer curves can differ drastically unit-to-unit
and lot-to-lot.
The CS5012A/14/16 achieves repeatable signalto-noise and harmonic distortion performance
using an on-chip self-calibration scheme. The
CS5012A calibrates its bit weight errors to a
small fraction of an LSB at 12-bits yielding peak
distortion below the noise floor (see Figure 18).
The CS5014 calibrates its bit weights to within
±1/16 LSB at 14-bits (±0.0004% FS) yielding
peak distortion as low as -105 dB (see Figure 21). The CS5016 calibrates its bit weights to
within ±1/4 LSB at 16-bits (±0.0004% FS) yielding peak distortion as low as -105 dB (see
Figure 23). Unlike traditional ADC’s, the linearity of the CS5012A/14/16 are not limited by
bit-weight errors; their performance is therefore
extremely repeatable and independent of input
signal conditions.
Quantization Noise
The error due to quantization of the analog input
ultimately dictates the accuracy of any A/D converter. The continuous analog input must be
represented by one of a finite number of digital
codes, so the best accuracy to which an analog
input can be known from its digital code is
±1/2 LSB. Under circumstances commonly encountered in signal processing applications, this
quantization error can be treated as a random
variable. The magnitude of the error is limited to
±1/2 LSB, but any value within this range has
equal probability of occurrence. Such a probability distribution leads to an error "signal" with
an rms value of 1 LSB/√12. Using an rms signal
value of FS/√8 (amplitude = FS/2), this relates to
ideal 12-, 14-, and 16-bit signal-to-noise ratios
of 74, 86, and 98 dB respectively.
DS14F9
DS14F8
Equally important is the spectral content of this
error signal. It can be shown to be approximately
white, with its energy spread uniformly over the
band from dc to one-half the sampling rate. Advantage of this characteristic can be made by
judicious use of filtering. If the signal is bandlimited, much of the quantization error can be
filtered out, and improved system performance
can be attained.
FFT Tests and Windowing
In the factory, the CS5012A/14/16 are tested using Fast Fourier Transform (FFT) techniques to
analyze the converter’s dynamic performance. A
pure sinewave is applied to the CS5012A/14/16,
and a "time record" of 1024 samples is captured
and processed. The FFT algorithm analyzes the
spectral content of the digital waveform and distributes its energy among 512 "frequency bins."
Assuming an ideal sinewave, distribution of energy in bins outside of the fundamental and dc
can only be due to quantization effects and errors
in the CS5012A/14/16.
If sampling is not synchronized to the input sinewave, it is highly unlikely that the time record
will contain an integer number of periods of the
input signal. However, the FFT assumes that the
signal is periodic, and will calculate the spectrum
of a signal that appears to have large discontinuities, thereby yielding a severely distorted
spectrum. To avoid this problem, the time record
is multiplied by a window function prior to performing the FFT. The window function smoothly
forces the endpoints of the time record to zero,
thereby removing the discontinuities. The effect
of the window in the frequency-domain is to convolute the spectrum of the window with that of
the actual input.
Figure 17 shows an FFT computed from an ideal
12-bit sinewave. The quality of the window used
for harmonic analysis is typically judged by its
highest side-lobe level. The Blackman-Harris
window used for testing the CS5014 and CS5016
has a maximum side-lobe level of -92 dB. Fig25
2-31
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
0.0
0.0
Sampling Rate: 100kHz
Full Scale: 9Vp-p
S/N+D: 73.6dB
S/N+D: 73.9 dB
-20.0
-20.0
-40.0
Signal
Amplitude
Relative to
Full Scale -60.0
(dB)
-40.0
Signal
Amplitude
Relative to
-60.0
Full Scale
(dB)
-80.0
-80.0
-100.0
-100.0
-120.0
-120.0
dc
Input Frequency
fs /2
dc
Figure 17. Plot of Ideal 12-bit ADC
Signal
Amplitude
Relative to
Full Scale
(dB)
Sampling Rate: 100kHz
Full Scale: 9Vp-p
S/N+D: 72.9dB
-40.0
-60.0
-80.0
-100.0
-120.0
12.0
dc
Input Frequency (kHz)
50.0
Figure 19. FFT Plot of CS5012A with 12 kHz
Full-Scale Input
ures 20 and 22 show FFT plots computed from
an ideal 14 and 16-bit sinewave multiplied by a
Blackman-Harris window. Artifacts of windowing are discarded from the signal-to-noise
calculation using the assumption that quantization
noise is white. All FFT plots in this data sheet
were derived by averaging the FFT results from
ten 1024 point time records. This filters the spectral variability that can arise from capturing finite
time records without disturbing the total energy
outside the fundamental. All harmonics which exist above the noise floor and the -92 dB
side-lobes from the Blackman-Harris window are
therefore clearly visible in the plots. For more information on FFT’s and windowing refer to: F.J.
HARRIS, "On the use of windows for harmonic
0dB
0dB
S/(N+D): 86.1 dB
-20dB
-40dB
-60dB
Signal
Amplitude
Relative to
Full Scale
-80dB
-60dB
-80dB
-100dB
-100dB
-120dB
-120dB
fs /2
dc
Input Frequency
Figure 20. Plot of Ideal 14-bit ADC
26
2-32
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 85.3 dB
-20dB
-40dB
Signal
Amplitude
Relative to
Full Scale
50.0
Input Frequency (kHz)
Figure 18. Plot of CS5012A with 1 kHz
Full Scale Input
0.0
-20.0
1.0
dc
28 kHz
1 kHz
Input Frequency
Figure 21. CS5014 FFT plot with 1 kHz
Full Scale Input
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
0dB
0dB
S/(N+D): 97.5 dB
-20dB
-20dB
-40dB
-40dB
-60dB
-60dB
Signal
Amplitude
Relative to
Full Scale
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 92.4 dB
Signal
Amplitude
Relative to
Full Scale
-80dB
-100dB
-120dB
-80dB
-100dB
-120dB
dc
fs /2
dc
1 kHz
25 kHz
Input Frequency
Input Frequency
Figure 23. CS5016 FFT plot with 1 kHz
Full Scale Input
Figure 22. Plot of Ideal 16-bit ADC
CS5012A High Frequency Performance
analysis with the Discrete Fourier Transform",
Proc. IEEE, Vol. 66, No. 1, Jan 1978, pp.51-83.
This is available on request from Crystal Semiconductor.
The CS5012A performs very well over a wide
range of input frequencies as shown in Figure 24.
The figure depicts the CS5012A-KP7 tested under four different conditions. The conditions
include tests with the voltage reference set at 4.5
and at 2.5 volts with input signals at 0.5 dB down
from full scale and 6.0 dB down from full scale.
The sample rate is at 100 kHz for all cases. The
plots indicate that the part performs very well
even with input frequencies above the Nyquist
rate. Best performance at the higher frequencies
is achieved with a 2.5 volt reference.
Figures 18, 21, and 23 show the performance of
the CS5012A/14/16 with 1kHz full-scale inputs.
Figure 19 shows CS5012A performance with
12kHz full-scale inputs. Notice that the performance CS5012A/14/16 closely approaches that of
the corresponding ideal ADC.
75
fs =100 kSps
CS5012A
1.
2.
3.
4.
1
70
Signal to
Noise +
Distortion
(dB)
VREF
4.5
2.5
4.5
2.5
Signal
FS-0.5dB
FS-0.5dB
FS-6.0dB
FS-6.0dB
2
65
60
4
3
55
0
20
40
f s /2
60
80
100
fs
120
140
160
180
200
Input Frequency (kHz)
Figure 24. CS5012A High Frequency Input Performance
DS14F8
DS14F9
27
2-33
27
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
100 dB
0dB
1 kHz
12 kHz
24 kHz
S(N+D)
80 dB
Input
Frequencies
60 dB
-40dB
Signal
Amplitude
Relative to
Full Scale
40 dB
20 dB
0 dB
-60dB
-80dB
-100dB
-100 dB -80 dB -60 dB -40 dB -20 dB
Analog Input Amplitude
-120dB
0 dB
dc
100 dB
12 kHz
24 kHz
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 9.6 dB
-20dB
-40dB
Input
Frequency
60 dB
Input Frequency
0dB
1 kHz
80 dB
28 kHz
1 kHz
Figure 26. CS5014 FFT plot with 1 kHz
-60 dB Input
Figure 25. CS5014 S/(N+D) vs. Input Amplitude
(9Vp-p Full-Scale Input)
S(N+D)
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 24.1 dB
-20dB
-60dB
Signal
Amplitude
Relative to
Full Scale
40 dB
20 dB
-80dB
-100dB
-120dB
0 dB
-100 dB -80 dB -60 dB -40 dB -20 dB
0 dB
Analog Input Amplitude
Figure 27. CS5016 S/(N+D) vs. Input Amplitude
(9Vp-p Full-Scale Input)
Signal to Noise + Distortion vs Signal Level
As illustrated in Figures 25 - 28, the CS5014/16’s
on-chip self-calibration provides very accurate bit
weights which yield no degradation in quantization noise with low-level input signals. In fact,
quantization noise remains below the noise floor
in the CS5016, which dictates the converter’s signal-to-noise performance.
CS5016 Noise Considerations
All analog circuitry in the CS5016 is wideband in
order to achieve fast conversions and high
throughput. Wideband noise in the CS5016 integrates to 35 µV rms in unipolar mode (70 µV rms
in bipolar mode). This is approximately 1/2 LSB
28
2-34
dc
1 kHz
25 kHz
Input Frequency
Figure 28. CS5016 FFT plot with 1 kHz
-80 dB Input
rms with a 4.5V reference in both modes. Figure
29 shows a histogram plot of output code occurrences obtained from 5000 samples taken from a
CS5016 in the bipolar mode. Hexadecimal code
80CD was arbitrarily selected and the analog input was set close to code center. With a noiseless
converter, code 80CD would always appear. The
histogram plot of the CS5016 has a "bell" shape
with all codes other than 80CD due to internal
noise.
In a sampled data system all information about the
analog input applied to the sample/hold appears in
the baseband from dc to one-half the sampling rate.
This includes high-frequency components which
alias into the baseband. Low-pass (anti-alias) filters
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
Count
5000
Noiseless
Converter
4000
CS5016
3000
formed on the charge trapped on the capacitor array at the moment the HOLD command is given.
The charge on the array is ideally related to the
analog input voltage by Qin = -Vin x Ctot as
shown in Figure 2. Any deviation from this ideal
relationship will result in conversion errors even
if the conversion process proceeds flawlessly.
2000
1000
80CA
80CB
80CC
80CD
80CE
80CF
80D0
Code (Hexadecimal)
Counts:
0
11
911
3470
599
9
0
Figure 29. Histogram Plot of 5000 Conversion
Inputs from the CS5016
are therefore used to remove frequency components in the input signal which are above one-half
the sample rate. However, all wideband noise introduced by the CS5016 still aliases into the
baseband. This "white" noise is evenly spread
from dc to one-half the sampling rate and integrates to 35 µV rms in unipolar mode.
Noise can be reduced by sampling at higher than
the desired word rate and averaging multiple
samples for each word. Oversampling spreads the
CS5016’s noise over a wider band (for lower
noise density), and averaging applies a low-pass
response which filters noise above the desired
signal bandwidth. In general, the CS5016’s noise
performance can be maximized in any application
by always sampling at the maximum specified
rate of 50 kHz (for lowest noise density) and
digitally filtering to the desired signal bandwidth.
CS5014 and CS5016 Sampling Distortion
The ultimate limitation on the CS5014/16’s
linearity (and distortion) arises from nonideal
sampling of the analog input voltage. The calibrated capacitor array used during conversions is
also used to track and hold the analog input signal. The conversion is not performed on the
analog input voltage per se, but is actually perDS14F9
DS14F8
At dc, the DAC capacitor array’s voltage coefficient dictates the converter’s linearity. This
variation in capacitance with respect to applied
signal voltage yields a nonlinear relationship between charge Qin and the analog input voltage
Vin and places a bow or wave in the transfer
function. This is the dominant source of distortion at low input frequencies (Figures 21 and 23).
The ideal relationship between Qin and Vin can
also be distorted at high signal frequencies due to
nonlinearities in the internal MOS switches. Dynamic signals cause ac current to flow through
the switches connecting the capacitor array to the
analog input pin in the track mode. Nonlinear onresistance in the switches causes a nonlinear
voltage drop. This effect worsens with increased
signal frequency as shown in Figures 25 and 27
since the magnitude of the steady state current increases. First noticeable at 1 kHz, this distortion
assumes a linear relationship with input frequency. With signals 20 dB or more below
full-scale, it no longer dominates the converter’s
overall S/(N+D) performance (Figures 30-33).
This distortion is strictly an ac sampling phenomenon. If significant energy exists at high
frequencies, the effect can be eliminated using an
external track-and-hold amplifier to allow the array’s charge current to decay, thereby eliminating
any voltage drop across the switches. Since the
CS5014/16 has a second sampling function onchip, the external track-and-hold can return to the
track mode once the converter’s HOLD input
falls. It need only acquire the analog input by the
time the entire conversion cycle finishes.
29
2-35
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
0dB
0dB
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 81.5 dB
-20dB
-40dB
Signal
Amplitude
Relative to
Full Scale
-40dB
-60dB
Signal
Amplitude
Relative to
Full Scale
-80dB
-100dB
-60dB
-80dB
-100dB
-120dB
-120dB
dc
28 kHz
12 kHz
dc
Input Frequency
Figure 30. CS5014 FFT plot with 12 kHz
Full-scale Input
28 kHz
12 kHz
Input Frequency
Figure 31. CS5014 FFT plot with 12 kHz
-20 dB Input
0dB
0dB
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 84.3 dB
-20dB
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 71.9 dB
-20dB
-40dB
-40dB
Signal
Amplitude
Relative to
Full Scale
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 64.6 dB
-20dB
Signal
Amplitude
Relative to
Full Scale
-60dB
-80dB
-60dB
-80dB
-100dB
-100dB
-120dB
-120dB
dc
12 kHz
25 kHz
dc
Input Frequency
Figure 32. CS5016 FFT plot with 12 kHz
Full-scale Input
25 kHz
12 kHz
Input Frequency
Figure 33. CS5016 FFT plot with 12 kHz
-20 dB Input
Clock Feedthrough in the CS5014 and CS5016
Maintaining the integrity of analog signals in the
presence of digital switching noise is a difficult
problem. The CS5014/16 can be synchronized to
the digital system using the CLKIN input to
avoid conversion errors due to asynchronous interference. However, digital interference will still
affect sampling purity due to coupling between
the CS5014/16’s analog input and master clock.
The effect of clock feedthrough depends on the
sampling conditions. If the sampling signal at the
HOLD input is synchronized to the master clock,
clock feedthrough will appear as a dc offset at the
CS5014/16’s output. The offset could theoretically reach the peak coupling magnitude
30
2-36
(Figure 34), but the probability of this occurring
is small since the peaks are spikes of short duration.
Master Clock
Int/Ext
Freq
Internal 2MHz
External 2MHz
External 4MHz
External 4MHz
External 4MHz
Analog Input
Source Impedance
50
50
50
25
200
Clock Feedthrough
RMS Peak-to-Peak
15uV
70uV
25uV
110uV
40uV
150uV
25uV
110uV
80uV
325uV
Figure 35. Examples of Measured Clock Feedthrough
If sampling is performed asynchronously with the
master clock, clock feedthrough will appear as an
ac error at the CS5014/16’s output. With a fixed
DS14F9
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
sampling rate, a tone will appear as the clock frequency aliases into the baseband. The tone
frequency can be calculated using the equation
below and could be selectively filtered in software using DSP techniques.
ftone = (N fs - fclk)
where N = fclk/fs rounded to the nearest integer
The magnitude of clock feedthrough depends on
the master clock conditions and the source impedance applied to the analog input. When
operating with the CS5014/16’s internally generated clock, the CLKIN input is grounded and the
dominant source of coupling is through the device’s substrate. As shown in Figure 35, a typical
CS5014/16 operating with their internal oscillator
at 2 MHz and 50 Ω of analog input source impedance will exhibit only 15 µV rms of clock
feedthrough. However, if a 2 MHz external clock
is applied to CLKIN under the same conditions,
feedthrough increases to 25 µV rms. Feedthrough
also increases with clock frequency; a 4 MHz
clock yields 40 µV rms.
Clock feedthrough can be reduced by limiting the
source impedance applied at the analog input. As
shown in Figure 35, reducing source impedance
from 50 Ω to 25 Ω yields a 15 µV rms reduction
in feedthrough. Therefore, when operating the
CS5014/16 with high-frequency external master
clocks, it is important to minimize source impedance applied to the CS5014/16’s input.
Also, the overall effect of clock feedthrough can
be minimized by maximizing the input range and
LSB size. The reference voltage applied to VREF
can be maximized, and the CS5014/16 can be operated in bipolar mode which inherently doubles
the LSB size over the unipolar mode.
Differences between the CS5012A and the
CS5012
The differences between the CS5012A and the
CS5012 are tabulated in Table 3. The CS5012 is
a short-cycled version of the CS5016 A/D converter and includes the same 18-bit calibration
circuitry. This calibration circuitry sets the calibration resolution of the CS5012 at 1/64th of an
LSB and achieves the near perfect differential
linearity performance illustrated by the CS5012
DNL plot in Figure 15. The CS5012A calibration
circuitry was modified to provide calibration to
15-bit resolution therefore achieving calibration
to 1/8 of an LSB. This reduction in calibration
resolution for the CS5012A reduces the time required to calibrate the device (see Table 3) and
reduces the size of the total array capacitance.
The reduced array capacitance improves the high
frequency performance by allowing higher slew
rate in the input circuitry.
Table 3 documents some other improvements included in the CS5012A. The burst mode
calibration was made functional, although it
should not be used. The device was also modified
so the EOC signal goes low at the end of a reset
calibration in either microprocessor or microprocessor-independent mode. The CS5012A was
modified to maintain a throughput rate of 64
CLKIN cycles in loopback mode for all frequencies of CLKIN.
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
DS14F9
DS14F8
31
2-37
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
CS
CAL
INTRLV
RD
A0
RST
X
X
X
X
*
0
Function
Hold and Start Convert
X
0
1
X
X
*
0
Initiate Burst Calibration
1
0
0
X
X
*
0
Stop Burst Cal and Begin Track
X
0
X
0
X
*
0
Initiate Interleave Calibration
X
X
1
X
0
0
0
1
X
X
X
X
1
X
X
X
X
0
0
X
*
1
0
*
0
0
0
X
Terminate Interleave Cal
X
X
0
X
X
0
X
X
X
X
X
X
1
X
X
*
X
0
X
1
X
High Impedance Data Bus
Reset
Reset
HOLD
Read Output Data
Read Status Register
High Impedance Data Bus
* The status of A0 is not critical to the operation specified. However, A0 should not be low with
CS and HOLD low, or a software reset will result.
Table 4. CS5012A/14/16 Truth Table
+5V
Analog
Supply
10 Ω
28
VA+
0.1 µF
CS5012A
CS5014
CS5016
Analog
Signal
Source
Signal
Conditioning
200 Ω
29
1000 pF
0
VREF
or
±VREF
31
Voltage
Reference
0.01 µF
10 µF
30
0.1 µF
-5V
Analog
Supply
32
0.1 µF
AIN
12
VD+ 37
BW
BP/UP 27
0.1 µF
Mode
Select *
23
Clock
Source
(optional)
SDATA 44
SCLK 43
Serial
Data
Interface
(optional)
CLKIN
Data
D0-D15 8 or 16 Processor
EOC 42
EOT 41
1
HOLD
39
CAL
Control
38
Logic
INTRLV
24
CS
25
RD
VREF
26
A0
36
RESET
Reset
35
AGND
Generator
TST
11
REFBUF
DGND
VAVD- 0.1 µF
40
34
10 Ω
May be
microprocessor
or discrete logic.
Unused Logic inputs should only
be connected to VD+ or DGND.
* BW and BP/UP should always
be terminated to VD+ or DGND,
or driven by a logic gate.
For best dynamic
S/(N+D) performance.
Figure 36. CS5012A/14/16 System Connection Diagram
32
DS14F8
DS14F9
2-39
CS5012A CS5014 CS5016
DEVICE PINOUT
HOLD
D0
SDATA
D1
SCLK
D2
EOC
D3
EOT
D4
VD-
D5
CAL
D6
NC
D7
DGND
VD+
NC
D8
NC
D9
6 5 4 3 2 1 44
7
8
9
10
11
12
13
14
15
16
17
42
40
CS5012A
CS5014
CS5016
Top View
18 19 20 21 22 23 24 25 26 27 28
39
38
37
36
35
34
33
32
31
30
29
INTRLV
BW
RST
TST
VANC
REFBUF
VREF
AGND
D10
AIN
D11
VA+
D12
BP/UP
D13
A0
D14
RD
D15
CS
CLKIN
DS14F9
33
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
PIN DESCRIPTIONS
Power Supply Connections
VD+ – Positive Digital Power, PIN 12.
Positive digital power supply. Nominally +5 volts.
VD- – Negative Digital Power, PIN 40.
Negative digital power supply. Nominally -5 volts.
DGND – Digital Ground, PIN 11.
Digital ground.
VA+ – Positive Analog Power, PIN 28.
Positive analog power supply. Nominally +5 volts.
VA- – Negative Analog Power, PIN 34.
Negative analog power supply. Nominally -5 volts.
AGND – Analog Ground, PIN 30.
Analog ground.
Oscillator
CLKIN – Clock Input, PIN 23.
All conversions and calibrations are timed from a master clock which can either be supplied by
driving this pin with an external clock signal, or can be internally generated by tying this pin to
DGND.
Digital Inputs
HOLD – Hold, PIN 1.
A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion.
This input must remain low at least one CLKIN cycle plus 50 ns.
CS – Chip Select, PIN 24.
When high, the data bus outputs are held in a high impedance state and the input to CAL and
INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration
(depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and
INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and A0.
RD – Read, PIN 25.
When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data
bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW
and A0.
34
DS14F8
DS14F9
2-41
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
A0 – Read Address, PIN 26.
Determines whether data or status information is placed onto the data bus. When high during the
read operation, converted data is placed onto the data bus; when low, the status register is driven
onto the bus.
BP/UP – Bipolar/Unipolar Input Select, PIN 27.
When high, the device is configured with a bipolar transfer function ranging from -VREF to
+VREF. Encoding is in an offset binary format, with the mid-scale code 100...0000 centered at
AGND. When low, the device is configured for a unipolar transfer function from AGND to VREF.
Unipolar encoding is in straight binary format. Once calibration has been performed, either bipolar
or unipolar mode may be selected without the need to recalibrate.
RST – Reset, PIN 36.
When taken high for at least 100 ns, all internal digital logic is reset. Upon being taken low, a full
calibration sequence is initiated.
BW – Bus Width Select, PIN 37.
When hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read
cycle. When low, the bus is in a byte wide format. On the first read following a conversion, the
eight MSB’s are driven onto D0-D7. A second read cycle places the four LSB’s with four trailing
zeros on D0-D7. Subsequent reads will toggle the higher/lower order byte. Regardless of BW’s
status, a read cycle with A0 low yields the status information on D0-D7.
INTRLV – Interleave, PIN 38.
When latched low using CS, the device goes into interleave calibration mode. A full calibration
will complete every 2,014 conversions in the CS5012A, and every 72,051 conversions in the
CS5014/16. The effective conversion time extends by 20 clock cycles.
CAL – Calibrate, PIN 39.
When latched high using CS, burst calibration results. The device cannot perform conversions
during the calibration period which will terminate only once CAL is latched low again.
Calibration picks up where the previous calibration left off, and calibration cycles complete every
58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/16 . If
the device is converting when a calibration is signaled, it will wait until that conversion completes
before beginning.
Analog Inputs
AIN – Analog Input, PIN 29.
Input range in the unipolar mode is zero volts to VREF. Input range in bipolar mode is -VREF to
+VREF. The output impedance of buffer driving this input should be less than or equal to 200 Ω.
DS14F9
2-42
35
DS14F8
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
VREF – Voltage Reference, PIN 31.
The analog reference voltage which sets the analog input range. It represents positive full scale for
both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode.
Digital Outputs
D0 through D15 – Data Bus Outputs, PINS 2 thru 8, 10, 14, 16 thru 22.
3-state output pins. Enabled by CS and RD, they offer the converter’s output in a format
consistent with the state of BW if A0 is high. If A0 is low, bits D0-D7 offer status register data.
EOT – End Of Track, PIN 41.
If low, indicates that enough time has elapsed since the last conversion for the device to acquire
the analog input signal.
EOC – End Of Conversion, PIN 42.
This output indicates the end of a conversion or calibration cycle. It is high during a conversion
and will fall to a low state upon completion of the conversion cycle indicating valid data is
available at the output. Returns high on the first subsequent read or the start of a new conversion
cycle.
SDATA – Serial Output, PIN 44.
Presents each output data bit after it is determined by the successive approximation algorithm.
Valid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid
until the next bit appears.
SCLK – Serial Clock Output, PIN 43.
Used to clock converted output data serially from the CS5012A/14/16. Serial data is stable on the
rising edge of SCLK.
Analog Outputs
REFBUF – Reference Buffer Output, PIN 32.
Reference buffer output. A 0.1 µF ceramic capacitor must be tied between this pin and VA-.
Miscellaneous
TST – Test, PIN 35.
Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be
tied to DGND.
36
DS14F8
DS14F9
2-43
CS5012A CS5014 CS5016
CS5012A, CS5014, CS5016
PARAMETER DEFINITIONS
Linearity Error
The deviation of a code from a straight line passing through the endpoints of the transfer
function after zero- and full-scale errors have been accounted for. "Zero-scale" is a point 1/2 LSB
below the first code transition and "full-scale" is a point 1/2 LSB beyond the code transition to
all ones. The deviation is measured from the middle of each particular code. Units in %
Full-Scale.
Differential Linearity
Minimum resolution for which no missing codes is guaranteed. Units in bits.
Full Scale Error
The deviation of the last code transition from the ideal (VREF-3/2 LSB’s).
Units in LSB’s.
Unipolar Offset
The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in
unipolar mode (BP/UP low). Units in LSB’s.
Bipolar Offset
The deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 LSB below
AGND) when in bipolar mode (BP/UP high). Units in LSB’s.
Bipolar Negative Full-Scale Error
The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The
ideal is defined as lying on a straight line which passes through the final and mid-scale code
transitions. Units in LSB’s.
Peak Harmonic or Spurious Noise (More accurately, Signal to Peak Harmonic or Spurious Noise)
The ratio of the rms value of the signal to the rms value of the next largest spectral component
below the Nyquist rate (excepting dc). This component is often an aliased harmonic when the
signal frequency is a significant proportion of the sampling rate. Expressed in decibels.
Total Harmonic Distortion
The ratio of the rms sum of all harmonics to the rms value of the signal. Units in percent.
Signal-to-Noise Ratio
The ratio of the rms value of the signal to the rms sum of all other spectral components below
the Nyquist rate (excepting dc), including distortion components. Expressed in decibels.
Aperture Time
The time required after the hold command for the sampling switch to open fully. Effectively a
sampling delay which can be nulled by advancing the sampling signal. Units in nanoseconds.
Aperture Jitter
The range of variation in the aperture time. Effectively the "sampling window" which ultimately
dictates the maximum input signal slew rate acceptable for a given accuracy. Units in
picoseconds.
NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction
temperature of the device.
DS14F9
2-44
37
DS14F8
CS5012A CS5014 CS5016
PACKAGE DIMENSIONS
44 pin
PLCC
NO. OF TERMINALS
MILLIMETERS
INCHES
DIM
MIN NOM MAX
MIN NOM MAX
A
A1
4.20
4.45
4.57 0.165 0.175 0.180
2.29
2.79
3.04 0.090 0.110 0.120
B
0.33
0.41
0.53 0.013 0.016 0.021
E1 E
D/E 17.40 17.53 17.65 0.685 0.690 0.695
D1
D1/E1 16.51 16.59 16.66 0.650 0.653 0.656
D
D2/E2 14.99 15.50 16.00 0.590 0.610 0.630
e
B
1.19
1.27
1.35 0.047 0.050 0.053
e
A1
A
D2/E2
38
DS14F9
CS5012A CS5014 CS5016
4. ORDERING INFORMATION
Model
CS5012A-BL7
CS5012A-BL7Z (lead free)
CS5014-BL14
CS5014-BL14Z (lead free)
Model
CS5016-BL16
CS5016-BL16Z (lead free)
Conversion Time
Throughput
7.2 µs
100 kSps
Linearity
Temperature
Package
±½ LSB
-40 to +85 °C
44-pin PLCC
14.25 µs
56 kSps
Conversion Time
S/N Ratio
Linearity
Temperature
Package
16.25 µs
90 dB
0.0015%
-40 to +85 °C
44-pin PLCC
5. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model
Peak Relfow Temp
CS5012A-BL7
225 °C
CS5012A-BL7Z (lead free)
260 °C
CS5014-BL14
225 °C
CS5014-BL14Z (lead free)
260 °C
CS5016-BL16
225 °C
CS5016-BL16Z (lead free)
260 °C
MSL Rating*
Maximum Floor Life
2
2
365 Days
2
* MSL (Moisture Sensitivity Level) as specified by IPC/JDEC J-STD-020.
DS14F9
39
CS5012A CS5014 CS5016
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
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service marks of their respective owners.
40
DS14F9