ETC2 A23 Neon with simd and vfpv4 support Datasheet

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Allwinner A23
Datasheet
Revision 1.0
August 30, 2013
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Dual Core Mobile Application Processor
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
A23
Declaration
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THIS A23 DATASHEET IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY
(“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.
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THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER
RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR
ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS
USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF
ALLWINNER. THIS DATASHEET NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS
FOR ANY PARTICULAR APPLICATION.
THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL
BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER
SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT
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TO MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE.
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 2
A23
Date
Description
1.0
August 30, 2013
Initial version
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Revision
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Revision History
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 3
A23
Table of Contents
OVERVIEW................. �� 5
CHAPTER 2
FEATURES................................ �� 6
CHAPTER 3
BLOCK DIAGRAM................... �� 16
CHAPTER 4
PIN DESCRIPTION................. �� 17
PIN CHARACTERISTICS......................... �� 17
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4.1.
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CHAPTER 1
4.2. GPIO MULTIPLEXING FUNCTIONS.......................... ��23
4.3. DETAILED PIN/SIGNAL DESCRIPTION....................��25
CHAPTER 5
ELECTRICAL CHARACTERISTICS.... �� 28
ABSOLUTE MAXIMUM RATINGS.............................................................................................��28
5.2.
RECOMMENDED OPERATING CONDITIONS.......................................................................��29
5.3.
DC ELECTRICAL CHARACTERISTICS................................................................................................... ��29
5.4.
OSCILLATOR ELECTRICAL CHARACTERISTICS.........................................................................................��29
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5.1.
5.4.1. 24MHZ OSCILLATOR CHARACTERISTICS ��30
5.4.2. 32768HZ OSCILLATOR CHARACTERISTICS��30
POWER UP/DOWN SEQUENCE��30
CHAPTER 6
6.1.
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5.5.
PIN ASSIGNMENT��33
PIN MAP��33
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6.2. PACKAGE DIMENSION��34
A23 Datasheet (Revision 1.0)
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Page 4
1
OVERVIEW
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Overview
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The Allwinner A23 is a remarkably power-efficient dual-core mobile application processor based on ARM
CortexTM-A7 CPU along with Mali400MP2 GPU architecture. It is also highly competitive in terms of system cost
thanks to its high system integration and is capable of delivering excellent user experience while maintaining low
power consumption.
Main features of A23 include:
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●● CPU architecture: A23 is based on dual-core CortexTM-A7 CPU architecture, the most power efficient CPU core
ARM’s ever developed, to deliver superior system performance as well as optimized battery life experience;
●● Graphic: A23 adopts the extensively implemented and technically mature Mali400MP2 GPU to provide end
users with superior experience in web browsing, video playback and games; OpenGL ES 2.0 and OpenVG 1.1
standards are supported;
●● Video Engine: A23 supports high-definition 1080P video processing and various mainstream video standards
such as H.264, VP8, MPEG 1/2/4, JPEG/MJPEG, etc;
●● Display: A23 supports CPU/RGB/LVDS LCD interface up to 1280x800 resolution. Four-lane MIPI DSI (Display
Serial Interface) is integrated as well, supporting MIPI DSI V1.01 and MIPI D-PHY V1.00;
●● Image: A23 supports a parallel CMOS sensor interface up to 5M resolution
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Thanks to its advanced system design and outstanding software optimization, the A23 is capable of providing topnotch system performance with long-lasting battery life experience: in addition to its energy-efficient CortexTM-A7
CPU architecture, advanced fabrication process, video acceleration hardware, DVFS technology support and high
system integration, A23 also features a unique Talking Standby Mode where the processor can be inactive during
voice calls to provide end users with ultra-long battery life experience. Additionally, Allwinner A23 features high
system integration with a wide range of integrated I/Os like 4-lane MIPI DSI, LVDS, USB OTG/HOST, SD/MMC,
I2S/PCM, thus significantly reducing system components required in design to simplify product design and reduce
total system costs.
A23 Datasheet (Revision 1.0)
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Page 5
Features
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FEATURES
2.1. CPU Architecture
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The A23 platform is based on dual-core CortexTM-A7 CPU architecture.
2.2. GPU
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●● ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
●● NEON with SIMD and VFPv4 support
●● Support hardware virtualization
●● Support LPAE
●● Support 4GB address space
●● Support 128KB L1 cache and shared 256KB L2 cache
●● Support DVFS with independent power domain
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●● Mali400MP2 GPU
●● Support OpenGL ES 2.0 / OpenVG 1.1 standard
A23 Datasheet (Revision 1.0)
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Page 6
Features
2.3. Memory Subsystem
This section consists of:
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●● Boot ROM
●● SDRAM
●● NAND Flash
●● SD/MMC interface
Boot ROM
SDRAM
NAND Flash
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●● Support 1GB address space
●● Support 16-bit bus width
●● Support DDR3 /DDR3L SDRAM
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●● Support system boot from Raw NAND, eMMC NAND, SPI NOR Flash, and SD/TF card
●● Support system code download through USB OTG
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●● Comply to ONFI 2.3 and Toggle 1.0
●● Support 64-bit ECC per 512 bytes or 1024 bytes
●● Support 8-bit Raw NAND flash controller sharing pin with eMMC
●● Support 3.0V IO voltage
●● Support 2 CE and 2 RB signals
●● Support SLC/MLC/TLC NAND and EF-NAND
SD/MMC Interface
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●● Comply to eMMC standard specification V4.41, SD physical layer specification V2.0, SDIO card specification
V2.0
●● Support 4/8-bit bus width
●● Support HS/DS/SDR12/SDR25 bus mode
●● Support 3 SD/MMC controllers
●● Support SDIO interrupt detection
●● Support 3.0V IO voltage
A23 Datasheet (Revision 1.0)
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Page 7
Features
2.4. System Peripheral
This section includes:
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●● Timer
●● High Speed Timer
●● RTC
●● GIC
●● DMA
●● CCU
●● PWM
Timer
High Speed Timer
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●● Support two timers: clock source can be switched over 24MHz and 32768Hz
●● Support two 33-bit AVS counters
●● Support one 64-bit system counter from 24MHz
●● Support a watchdog to generate reset signal or interrupts
RTC
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●● Clock source is fixed to AHB, and the pre-scale ranges from 1 to 16
●● Support a 56-bit counter
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●● Support full clock features: second/minute/hour/day/month/year
●● Support a 32768Hz clock fanout
GIC
●● Support 16 SGIs, 16 PPIs and 128 SPIs
●● Support ARM architecture security extensions
●● Support ARM architecture virtualization extensions
●● Support single processor and multiple processors environment
A23 Datasheet (Revision 1.0)
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Page 8
Features
DMA
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●● 8-channel DMA
●● Support data width of 8/16/32 bits
●● Support linear and IO address modes
CCU
●● 9 PLLs
●● Support a 24MHz oscillator, a 32768Hz oscillator and an on-chip RC oscillator
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●● Support three PWM outputs
●● Support cycle mode and pulse mode
●● Support prescale from 1 to 64
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PWM
A23 Datasheet (Revision 1.0)
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Page 9
Features
2.5. Display Subsystem
This section includes:
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●● Display engine
●● Video output
Display Engine
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●● Four movable layers, each layer size up to 8192x8192 pixels
●● Ultra-Scaling engine
–Support
four-tap scale filter in both horizontal and vertical
–
–Support
source image size from 8x4 to 8192x8192 resolution and destination image size from 8x4 to
–
8192x8192 resolution
Video Output
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●● Support multiple image input formats: mono 1/2/4/8bpp, palette 1/2/4/8bpp, 6/24/32bpp color,
YUV444/420/422/411
●● Support alpha blending / color key / gamma
●● Support output color correction: luminance / hue / saturation, etc
●● Support Color Management Unit (CMU) and Dynamic Range Correction (DRC)
●● Support realtime write back function
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●● Support CPU / Sync RGB / LVDS LCD interface up to 1280x800 resolution
●● Support 1/2/4-lane MIPI DSI interface up to 1280x800 resolution
–Support
MIPI DSI V1.01 and MIPI D-PHY V1.00
–
–Support
command mode and video mode (non-burst mode with sync pulses, non-burst mode with sync event
–
and burst mode)
●● Support RGB666 dither function
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 10
Features
2.6. Video Engine
Video Decoding
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●● Support video playback up to 1920x1080@60fps
●● Support multi-format video playback, including MPEG1/2, MPEG4 SP/ASP GMC, H.263 including Sorenson
Spark, H.264 BP/MP/HP, VP8, WMV9/VC-1, JPEG/MJPEG, etc
Video Encoding
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●● Support H.264 HP video encoding up to 1920x1080@60fps
●● JPEG baseline: picture size up to 4080x4080
●● Support Alpha blending
●● Support thumb generation
●● Support 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer ratio
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 11
Features
2.7. Image Subsystem
●● Support parallel camera sensor
●● Support 8-bit CCIR601/656 interface
●● Support up to 5M pixel camera sensor
●● Support dual outputs for display and encoding
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2.8. Audio Subsystem
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CSI
Audio Codec
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●● Support stereo audio DAC
–Up
– to 100dB SNR
–8KHz
~ 192KHz DAC sample rate
–
●● Support stereo audio ADC
–Up
– to 94dB SNR
–8KHz
~ 48KHz ADC sample rate
–
●● Support four analog audio inputs
–Two
microphone differential inputs for main mic and headphone mic
–
–One
differential phone input for modem
–
–One
stereo line-in input for FM
–
●● Support two analog audio outputs
–One
stereo or differential capless headphone output
–
–One
differential earpiece output
–
●● Support Talking Standby Mode, where the application processor remains inactive during voice call application for
power saving
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 12
Features
2.9. External Peripherals
This section includes:
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●● USB 2.0 OTG
●● USB HOST
●● LRADC
●● Digital Audio Interface
●● UART
●● SPI
●● Open-drain TWI
●● RSBTM
USB 2.0 OTG
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●● Support High-Speed (HS, 480Mbps), Full-Speed (FS, 12Mbps), and Low-Speed (LS, 1.5Mbps) in Host mode
●● Support High-Speed (HS, 480Mbps) and Full-Speed (FS, 12Mbps) in Device mode
●● Support up to five configurable endpoints for bulk, isochronous, control and interrupt
USB Host
LRADC
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●● EHCI/OHCI-compliant host
●● USB2.0 PHY and HSIC
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●● 6-bit resolution
Digital Audio Interface
●● Two I2S/PCM compliant digital audio interfaces for modem and bluetooth
●● I2S supports 2 channels output and 2 channels input
●● PCM supports linear sample(8-bit or 16-bit), 8-bit u-law and A-law companded sample
A23 Datasheet (Revision 1.0)
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Page 13
Features
UART
SPI
●● Support two SPI controllers with one chip select signal
●● Master/Slave configurable
TWI
RSBTM (Reduced Serial Bus)
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●● Support transfer speed up to 20MHz
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●● Support four TWI controllers
●● Support one dedicated TWI controller for CSI
●● Support speed up to 400Kbps
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●● Support six UART controllers
●● Support FIFO size up to 64 bytes
●● Support speed up to 3MHz
A23 Datasheet (Revision 1.0)
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Page 14
Features
2.10. Power Management
2.11. Process and Package
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●● 40nm LP process
●● FBGA 280 balls,0.80mm ball pitch, 14 x 14 x 1.4-mm
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●● Support DVFS for CPU frequency and voltage adjustment
●● Support super standby mode for energy efficiency
●● Support talking standby mode for energy efficiency during voice call application
A23 Datasheet (Revision 1.0)
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Page 15
Block Diagram
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BLOCK DIAGRAM
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A23 Block Diagram
A23 Datasheet (Revision 1.0)
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Page 16
Pin Description
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4.1.
PIN DESCRIPTION
PIN CHARACTERISTICS
BALL#
Pin Name
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Following table describes the A2x pin characteristics from seven aspects: BALL#, Pin Name, Default
Function1, Type2, Reset State3, Default Pull Up/Down4, and Buffer Strength5.
Default
Function
Type
Reset State
Default Pull
Up/Down
Buffer
Strength (mA)
DQ0
DQ1
DRAM
DRAM
I/O
I/O
Z
Z
-
-
L1
DQ2
DRAM
I/O
Z
-
-
L2
J1
J2
H1
H2
U3
U1
U2
T2
R2
P1
P2
N1
M4
R1
T1
T3
K2
K1
N2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DVREF
DQS1
DQS1B
DQM1
DQS0
DQS0B
DQM0
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
I/O
I/O
O
I/O
I/O
O
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
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SDRAM
M1
M2
Note:
1 Default function defines the default function of each pin, especially for pins with multiplexing functions;
2 There are five pin types here: O for output, I for input, I/O for input/output, A for analog,OD for Open-Drain, P for
power and G for ground;
3 Reset state defines the state of the terminal at reset: Z for high-impedance.
4 Default Pull up/down defines the presence of an internal pull up or pull down resistor. Unless otherwise specified, the pin is default to be floating, and can be configured as pull up or pull down;
5 Buffer strength defines the driver strength of the associated output buffer. It is tested in the condition that VCC=
3.0V, strength=MAX;
A23 Datasheet (Revision 1.0)
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Page 17
Pin Description
Default Pull
Up/Down
Buffer
Strength (mA)
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
POWER
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
A
O
P
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
VCC-DRAM
POWER
P
-
-
-
GND-DLL
GROUND
G
-
-
-
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
Z
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
20
20
20
20
20
20
20
20
PC0
PC1
PC2
PC3
PC4
PC5
PC6
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
NO PULL
NO PULL
NO PULL
PULL UP
PULL UP
NO PULL
PULL UP
20
20
20
20
20
20
20
Function
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DCKB
DCK
DCKE
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA14
DA15
DBA0
DBA1
DBA2
DWE
DCAS
DRAS
DCS
DODT
DZQ
DRST
VDD-DLL
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G2
G1
J4
E4
D1
F2
H3
D2
F1
A1
G4
B1
F4
E2
C2
E1
F3
C1
E3
J3
K4
H4
K3
M3
L4
N3
L3
R3
G3
P3
H5,J5,K5,L5,
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Reset State
Pin Name
H6,J6
N4
GPIO B
G17
G16
F17
F16
G14
G15
F14
F15
GPIO C
D12
C12
C11
D11
B11
C10
D10
Default
Type
BALL#
A23 Datasheet (Revision 1.0)
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Page 18
Pin Description
Default Pull
Up/Down
Buffer
Strength (mA)
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
20
20
20
20
20
20
20
20
20
20
PD2
PD3
PD4
PD5
PD6
PD7
PD10
PD11
PD12
PD13
PD14
PD15
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
VCC-PD
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
POWER
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
-
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
-
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
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Function
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PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
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Reset State
Fo
A12
A11
B10
A10
B9
A9
B8
A8
B7
A7
GPIO D
R12
P12
R11
P11
R10
P10
R9
P9
R8
P8
R7
P7
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
M11,N11
GPIO E
C5
D5
C6
D6
A6
B6
A5
B5
A4
B4
A3
B3
A2
B2
C3
Default
Type
Pin Name
rI
BALL#
A23 Datasheet (Revision 1.0)
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Page 19
Pin Description
Default Pull
Up/Down
Buffer
Strength (mA)
GPIO
GPIO
GPIO
I/O
I/O
I/O
Z
Z
Z
NO PULL
NO PULL
NO PULL
20
20
20
PF0
PF1
PF2
PF3
PF4
PF5
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
20
20
20
20
20
20
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
20
20
20
20
20
20
20
20
20
20
20
20
20
20
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
20
20
20
20
20
20
20
20
20
20
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PL8
PL9
PL10
PL11
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
PULL UP
PULL UP
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
NO PULL
20
20
20
20
20
20
20
20
20
20
20
20
NMI
-
I
Z
NO PULL
-
Function
tO
PE15
PE16
PE17
Fo
A23 Datasheet (Revision 1.0)
nly
Reset State
rI
D3
C4
D4
GPIO F
D9
C9
D8
C8
D7
C7
GPIO G
A15
B15
A14
B14
A13
B13
A17
B17
A16
B16
C17
C16
C15
C14
GPIO H
D17
D16
D15
D14
D13
C13
E17
E16
E15
E14
GPIO L
P16
P15
U14
T14
R14
P14
U13
T13
R13
P13
U12
T12
SYSTEM CONTROL
N14
Default
Type
Pin Name
ne
BALL#
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 20
Pin Description
Pin Name
P17
RESET
T16
T17
U16
U17
L12
USB-DM0
USB-DP0
USB-DM1
USB-DP1
VCC-USB
N12
T15
U15
AUDIO CODEC
M16
M17
N16
N17
J15
H15
K16
K17
L16
L17
N15
M15
K15
L15
G14
K14
H13
J16
J17
H14
H16
H17
K13
LRADC
L14
DSI
R4
P4
R5
P5
U6
T6
P6
R6
U5
T5
N6
CLOCK
R17
VCC-HSIC
HSIC-STR
HSIC-DAT
Reset State
Default Pull
Up/Down
Buffer
Strength (mA)
-
I
Z
NO PULL
-
-
A
A
A
A
P
-
-
-
-
-
-
-
-
-
Function
P
A
A
-
A
A
A
A
A
A
A
A
P
A
A
A
A
A
A
A
G
A
A
A
A
P
P
LRADC0
-
A
-
-
-
DSI-D0N
DSI-D0P
DSI-D1N
DSI-D1P
DSI-D2N
DSI-D2P
DSI-D3N
DSI-D3P
DSI-CKN
DSI-CKP
VCC-DSI
-
A
A
A
A
A
A
A
A
A
A
A
-
-
-
X32KIN
-
A
-
-
-
tO
MIC1N
MIC1P
MIC2N
MIC2P
LINEINR
LINEINL
VRA1
VRA2
AVCC
VRP
PHONEOUTN
PHONEOUTP
PHONEINN
PHONEINP
HBIAS
MBIAS
AGND
HPOUTR
HPOUTL
HPCOM
HPCOMFB
HPVCCBP
HPVCCIN
Fo
rI
HSIC
Type
ne
USB
Default
nly
BALL#
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 21
Pin Name
R16
R15
M13
M12
U4
T4
M5
POWER
M14
Type
Reset State
-
A
A
A
P
A
A
P
-
VDD-CPUS
-
P
VDD-CPU
-
P
VDD-SYS
-
P
VCC-IO
-
P
GND
-
G
X32KOUT
X32KFOUT
RTCVIO
VCC-RTC
X24MIN
X24MOUT
VCC-PLL
E5,E6,E7,F5,F6,
F7,G5,G6
Function
E8,E9,E10,K6,
L6,M6,M7,N8
E11,E12,F11
F12,G12
F8,F9,F10,
G7,G8,G9,G10,
G11,H7,H8,
J10,J11,J12
K7,K8,K9,K10,
K11,K12,L7,
L8,L9,L10,
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Fo
rI
L11, M8,M9,M10
-
-
ne
H9,H10,H11,
H12,J7,J8,J9,
-
tO
N9,N10
Pin Description
Default Pull
Buffer
Up/Down
Strength (mA)
nly
BALL#
Default
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 22
Pin Description
4.2. GPIO MULTIPLEXING FUNCTIONS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Pull-up
Pull-up
Z
Pull-up
Pull-up
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
A23 Datasheet (Revision 1.0)
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
UART2_TX
UART2_RX
UART2_RTS
UART2_CTS
PCM0_SYNC
PCM0_CLK
PCM0_DOUT
PCM0_DIN
NAND_WE
NAND_ALE
NAND_CLE
NAND_CE1
NAND_CE0
NAND_RE
NAND_RB0
NAND_RB1
NAND_DQ0
NAND_DQ1
NAND_DQ2
NAND_DQ3
NAND_DQ4
NAND_DQ5
NAND_DQ6
NAND_DQ7
NAND_DQS
LCD_D2
LCD_D3
LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D18
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23
LCD_CLK
LCD_DE
SPI0_MOSI
SPI0_MISO
SPI0_CLK
SPI0_CS
SDC2_CLK
SDC2_CMD
SDC2_D0
SDC2_D1
SDC2_D2
SDC2_D3
SDC2_D4
SDC2_D5
SDC2_D6
SDC2_D7
SDC2_RST
SDC1_CLK
SDC1_CMD
SDC1_D0
SDC1_D1
SDC1_D2
SDC1_D3
UART1_TX
UART1_RX
UART1_RTS
UART1_CTS
PB_EINT0
PB_EINT1
PB_EINT2
PB_EINT3
PB_EINT4
PB_EINT5
PB_EINT6
PB_EINT7
-
tO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Default Default Pull
IO State Up/Down
ne
Function
IO Type
Fo
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PD2
PD3
PD4
PD5
PD6
PD7
PD10
PD11
PD12
PD13
PD14
PD15
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
Default
rI
Port
nly
Following table provides a description of the GPIO multiplexing functions of A23.
LVDS_VP0
LVDS_VN0
LVDS_VP1
LVDS_VN1
LVDS_VP2
LVDS_VN2
LVDS_VPC
LVDS_VNC
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 23
Pin Description
A23 Datasheet (Revision 1.0)
LCD_HSYNC
LCD_VSYNC
CSI_PCLK
CSI_MCLK
CSI_HSYNC
CSI_VSYNC
CSI_D0
CSI_D1
CSI_D2
CSI_D3
CSI_D4
CSI_D5
CSI_D6
CSI_D7
CSI_SCK
CSI_SDA
SDC0_D1
SDC0_D0
SDC0_CLK
SDC0_CMD
SDC0_D3
SDC0_D2
SDC1_CLK
SDC1_CMD
SDC1_D0
SDC1_D1
SDC1_D2
SDC1_D3
UART1_TX
UART1_RX
URAT1_RTS
UART1_CTS
PCM1_SYNC
PCM1_CLK
PCM1_DOUT
PCM1_DIN
PWM0
PWM1
TWI0_SCK
TWI0_SDA
TWI1_SCK
TWI1_SDA
SPI0_CS
SPI0_CLK
SPI0_DOUT
SPI0_DIN
S_RSB_SCK
S_RSB_SDA
S_UART_TX
S_UART_RX
LVDS_VP3
LVDS_VN3
TWI2_SCK
TWI2_SDA
UART3_TX
UART3_RX
UART_RTS
UART_CTS
S_TWI_SCK
S_TWI_SDA
-
PG_EINT0
PG_EINT1
PG_EINT2
PG_EINT3
PG_EINT4
PG_EINT5
PG_EINT6
PG_EINT7
PG_EINT8
PG_EINT9
PG_EINT10
PG_EINT11
PG_EINT12
PG_EINT13
S_PL_EINT0
S_PL_EINT1
S_PL_EINT2
S_PL_EINT3
S_PL_EINT4
nly
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Pull-up
Pull-up
Z
Z
Z
tO
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
JTAG
JTAG
DIS
JTAG
DIS
JTAG
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
ne
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
rI
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Fo
PD26
PD27
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PF0
PF1
PF2
PF3
PF4
PF5
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PL0
PL1
PL2
PL3
PL4
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 24
Pin Description
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Z
Z
Z
Z
Z
Z
Z
S_TWI_SCK
S_TWI_SDA
S_PWM
-
-
S_PL_EINT5
S_PL_EINT6
S_PL_EINT7
S_PL_EINT8
S_PL_EINT9
S_PL_EINT10
S_PL_EINT11
nly
PL5
PL6
PL7
PL8
PL9
PL10
PL11
4.3. DETAILED PIN/SIGNAL DESCRIPTION
tO
Description
I/O
P
I/O
I/O
O
O
O
O
O
O
O
O
O
O
A
O
P
P
Port B Bit[7:0]
Port C Bit[18:0]
Port D Bit[27:0]
Port D Power Supply
Port E Bit[17:0]
Port F Bit[5:0]
Port G Bit[13:0]
Port H Bit[9:0]
Port L Bit[11:0]
I/O
I/O
I/O
P
I/O
I/O
I/O
I/O
I/O
Non-Maskable Interrupt
Reset Signal
I
I
External Interrupt
I
PWM
O
Clock Input of 32768Hz Crystal
A
Fo
A23 Datasheet (Revision 1.0)
Type
DRAM DQ[15:0]
DRAM Reference Input
DRAM Data Strobe DQS[1:0]
DRAM Data Strobe DQSB[1:0]
DRAM Clock
DRAM CKB
DRAM Clock Enable
DRAM Data Address[15:0]
DRAM Bank Address[2:0]
DRAM Write Enable
DRAM Column Address Strobe
DRAM Row Address Strobe
DRAM Chip Select
DRAM ODT Control
DRAM ZQ Calibration
DRAM Reset
DLL Power Supply
DRAM Power Supply
rI
DRAM
DQ[15:0]
DVREF
DQS[1:0]
DQSB[1:0]
DCK
DCKB
DCKE
DA[15:0]
DBA[2:0]
DWE
DCAS
DRAS
DCS
DODT
DZQ
DRST
VDD-DLL
VCC-DRAM
GPIO
PB[7:0]
PC[18:0]
PD[27:0]
VCC-PD
PE[17:0]
PF[5:0]
PG[13:0]
PH[9:0]
PL[11:0]
SYSTEM CONTROL
NMI
RESET
INTERRUPT
EINT
PWM
PWM[1:0]
CLOCK
X32KIN
ne
Pin/Signal
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 25
Pin Description
A
OD
P
P
A
A
P
I/O
O
O
O
O
O
I
I/O
LCD Data Bit[23:0]
LCD Clock Signal
LCD Data Enable
LCD Horizontal SYNC
LCD Vertical SYNC
O
O
O
O
O
LVDS Data Positive Signal Output[3:0]
LVDS Data Negative Signal Output[3:0]
LVDS Clock Positive Output
LVDS Clock Negative Output
A
A
A
A
DSI Data Negative
DSI Data Positive
DSI Clock Negative
DSI Clock Positive
DSI Power Supply
A
A
A
A
P
CSI0 Data Bit[7:0]
CSI Pixel Clock
CSI Master Clock
CSI Clock Signal
CSI Data Signal
CSI Horizontal SYNC
CSI Vertical SYNC
I
I
O
O
IO
I
I
USB DM[1:0] Signal
USB DP[1:0] Signal
USB Power Supply
A
A
P
HSIC Power Supply
USB HSIC signal
USB HSIC signal
P
A
A
Phone Negative Output
Phone Positive Output
Phone Negative Input
A
A
A
tO
NAND Flash Data Bit[7:0]
NAND Flash Chip Select[1:0]
NAND Flash Write Enable
NAND Flash Address Latch Enable
NAND Flash Command Latch Enable
NAND Flash Read Enable
NAND Flash Ready/Busy Bit
NAND Flash Data Strobe
Fo
A23 Datasheet (Revision 1.0)
Type
nly
Clock Output of 32768Hz Crystal
Clock Output of LOSC (X32KFOUT can be gating)
RTC Power
RTC Power Supply
Clock Input of 24MHz Crystal
Clock Output of 24MHz Crystal
PLL Power
rI
X32KOUT
X32KFOUT
RTCVIO
VCC-RTC
X24MIN
X24MOUT
VCC-PLL
NAND FLASH
NAND-DQ[7:0]
NAND-CE[1:0]
NAND-WE
NAND-ALE
NAND-CLE
NAND-RE
NAND-RB
NAND-DQS
LCD
LCD-D[23:0]
LCD-CLK
LCD-DE
LCD-HSYNC
LCD-VSYNC
LVDS
LVDS-VP[3:0]
LVDS-VN[3:0]
LVDS-VPC
LVDS-VNC
DSI
DSI-DN(3:0)
DSI-DP(3:0)
DSI-CKN
DSI-CKP
VCC-DSI
CSI
CSI-D[7:0]
CSI-PCLK
CSI-MCLK
CSI-SCK
CSI-SDA
CSI-HSYNC
CSI-VSYNC
USB
USB-DM[1:0]
USB-DP[1:0]
VCC-USB
HSIC
VCC-HSIC
HSIC-STR
HSIC-DAT
AUDIO CODEC
PHONEOUTN
PHONEOUTP
PHONEINN
Description
ne
Pin/Signal
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 26
Pin Description
Description
A
A
A
A
A
A
A
A
A
P
A
G
A
A
A
A
A
A
A
tO
LRADC Input
A
SPI Chip Select Signal
SPI Clock Signal
SPI Data Output
SPI Data Input
SPI Master Data Out, Slave Data In
SPI Master Data In, Slave Data Out
I/O
I/O
O
I
I/O
I/O
UART Data Transmit
UART Data Receive
UART Data Request to Send
UART Data Clear to Send
O
I
O
I
TWI Clock Signal
TWI Data Signal
I/O
I/O
SD/MMC/SDIO Data Bit
SD/MMC/SDIO Clock
SD/MMC/SDIO Command Signal
SD/MMC/SDIO Reset Signal
I/O
O
I/O
O
PCM SYNC
PCM Clock
PCM Data Output
PCM Data Input
I/O
I/O
O
I
RSB Clock
RSB Data
O
I/O
CPU Power Supply
CPUS Power Supply
System Power Supply
P
P
P
Fo
A23 Datasheet (Revision 1.0)
Type
nly
Phone Positive Input
MIC Negative Input
MIC Positive Input
Line-in Right Input
Line-in Left Input
HBIAS
MBIAS
Reference (1.5V)
Reference (1.5V)
Analog Power Supply
Reference (3.0V)
Analog Ground
Headphone Right Channel Output
Headphone Left Channel Output
Headphone VCC Input
Headphone VCC Bypass
Headphone Common Reference
Headphone Common Reference Feedback
Headphone Bypass Output
rI
PHONEINP
MICINN[2:1]
MICINP[2:1]
LINEINR
LINEINL
HBIAS
MBIAS
VRA1
VRA2
AVCC
VRP
AGND
HPOUTR
HPOUTL
HPVCCIN
HPVCCBP
HPCOM
HPCOMFB
HPBP
LRADC
LRADC0
SPI
SPI0-CS
SPI0-CLK
SPI0-DOUT
SPI0-DIN
SPI0-MOSI
SPI0-MISO
UART (x=[3:0])
UARTx-TX
UARTx-RX
UARTx-RTS
UARTx-CTS
TWI (x=[2:0])(Open-Drain)
TWIx-SCK
TWIx-SDA
SD/MMC (x=[2:0])
SDCx-D
SDCx-CLK
SDCx-CMD
SDC-RST
PCM(x=[1:0])
PCMx-SYNC
PCMx-CLK
PCMx-DOUT
PCMx-DIN
RSB
S-RSB-SCK
S-RSB-SDA
POWER
VDD-CPU
VDD-CPUS
VDD-SYS
ne
Pin/Signal
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 27
Pin Description
Pin/Signal
Type
Description
Ground
IO Power Supply
G
P
Fo
rI
ne
tO
nly
GND
VCC-IO
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 28
Electrical Characteristics
5
nly
5.1.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
tO
Functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
SYMBOL
PARAMETER
Tg
Storage Temperature
II/O
In/Out current for input and output
MIN
MAX
UNIT
-65
150
°C
mA
-
-
HBM(human body model)
-4000
+4000
CDM(charged device model)
NA
NA
ESD stress voltage
VCC-IO
DC Supply Voltage for I/O
-
3.6
V
VDD-DLL
Power Supply for DLL
-
2.75
V
Power Supply for DRAM (DDR3L)
-
1.35
V
Power Supply for DRAM (DDR3)
-
1.5
V
VCC-PLL
Power Supply for PLL
-
3.3
V
VCC-RTC
Power Supply for RTC
-
3.3
V
AVCC
DC Supply Voltage for Analog Part
-
3.3
V
Power Supply for USB PHY
-
3.6
V
Power Supply for DSI
-
3.6
V
Power Supply for CPU
-
1.3
V
Power Supply for System
-
1.3
V
VCC-USB
VCC-DSI
VDD-CPU
Fo
VDD-SYS
rI
VCC-DRAM
ne
VESD
5.2.
VESD
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
Ambient Operating Temperature[Commercial]
-20
-
70
°C
Operating Temperature[Extended]
NA
NA
NA
°C
GND
Ground
0
0
0
V
VCC-IO
DC Supply Voltage for I/O
1.8
3.0
3.6
V
Ta
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 29
Electrical Characteristics
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VDD-DLL
Power Supply for DLL
2.37
2.5
2.63
V
Power Supply for DRAM (DDR3L)
-
1.35
-
V
VCC-DRAM
-
1.5
-
V
Power Supply for PLL
2.85
3.0
3.15
V
VCC-USB
Power Supply for USB PHY
2.7
3.3
3.6
V
VCC-RTC
Power Supply for RTC
2.85
3.0
3.15
V
DC Supply Voltage for Analog Part
Power Supply for MIPI DSI
VDD-CPU
Power Supply for CPU
VDD-SYS
Power Supply for System
5.3.
2.8
3.0
3.3
V
3.14
3.3
3.47
V
1.0
-
1.3
V
1.0
-
1.3
V
tO
AVCC
VCC-DSI
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Power Supply for DRAM (DDR3)
VCC-PLL
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC-IO=3.0V
2.1
3.0
3.6
V
-0.3
0
0.7
V
-
-
-
-
mV
VCC-IO=3.0V, VI=3.0V
TBD
TBD
TBD
uA
Low-Level Input Current
VCC-IO=3.0V, VI=0V
TBD
TBD
TBD
uA
VOH
High-Level Output Voltage
VCC-IO=3.0V
2.7
3.0
NA
V
VOL
Low-Level Output Voltage
VCC-IO=3.0V
NA
0
0.4
V
IOZ
Tri-State Output Leakage Current
VCC-IO=3.0V
TBD
TBD
TBD
uA
CIN
Input Capacitance
-
NA
NA
5
pF
COUT
Output Capacitance
-
NA
NA
5
pF
High-Level Input Voltage
VIL
Low-Level Input Voltage
VCC-IO=3.0V
VHYS
Hysteresis Voltage
IIH
High-Level Input Current
IIL
Fo
rI
ne
VIH
5.4.
OSCILLATOR ELECTRICAL CHARACTERISTICS
The A23 contains two oscillators: a 24MHz oscillator and a 32768Hz oscillator. Each oscillator requires a
specific crystal.
The A23 device operation requires following two input clocks:
●● The 32768Hz frequency is used for low frequency operation.
●● The 24MHz frequency is used to generate the main source clock of the A23 device.
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 30
Electrical Characteristics
5.4.1. 24MHz OSCILLATOR CHARACTERISTICS
The 24MHz crystal is connected between the HOSCI (amplifier input) and HOSCO (amplifier output).
PARAMETER
1/(tCPMAIN)
Crystal Oscillator Frequency Range
tST
Startup Time
Frequency Tolerance at 25°C
Oscillation Mode
MIN
TYP
MAX
UNIT
-
24
-
MHz
-
-
-
ms
-50
-
50
ppm
-50
-
50
ppm
-
-
50
uW
-
-
-
pF
-
-
-
pF
-
-
-
Ω
30
50
70
%
-
-
-
pF
-
-
-
pF
-
-
-
MΩ
nly
SYMBOL
Fundamental
Maximum Change Over Temperature Range
Drive Level
CL
Equivalent Load Capacitance
CL1,CL2
Internal Load Capacitance(CL1=CL2)
RS
Series Resistance(ESR)
CM
Motional Capacitance
CSHUT
Shunt Capacitance
RBIAS
Internal Bias Resistor
ne
Duty Cycle
tO
PON
-
5.4.2. 32768HZ OSCILLATOR CHARACTERISTICS
The 32768Hz crystal is connected between the LOSCI (amplifier input) and LOSCO (amplifier output).
PARAMETER
MIN
TYP
MAX
UNIT
Crystal Oscillator Frequency Range
-
32768
-
Hz
Startup Time
-
-
-
ms
Frequency Tolerance at 25°C
-50
-
50
ppm
Oscillation Mode
Fundamental
tST
rI
SYMBOL
1/(tCPMAIN)
Maximum Change Over Temperature Range -50
PON
CL1,CL2
RS
-
50
ppm
Drive Level
-
-
50
uW
Equivalent Load Capacitance
-
-
-
pF
Internal Load Capacitance(CL1=CL2)
-
-
-
pF
Fo
CL
-
Series Resistance(ESR)
-
-
-
Ω
Duty Cycle
30
50
70
%
CM
Motional Capacitance
-
-
-
pF
CSHUT
Shunt Capacitance
-
-
-
pF
RBIAS
Internal Bias Resistor
-
-
-
MΩ
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 31
Electrical Characteristics
5.5.
POWER UP/DOWN SEQUENCE
Fo
rI
ne
tO
nly
The external voltage regulator and other power-on devices must provide the processor with a specific sequence of
power and resets to ensure proper operations.
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 32
Pin Assignment
6
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PIN MAP
Fo
rI
ne
tO
6.1.
PIN ASSIGNMENT
A23 Datasheet (Revision 1.0)
Copyright ©2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 33
Pin Assignment
Fo
rI
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tO
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6.2. PACKAGE DIMENSION
A23 Datasheet (Revision 1.0)
Copyright ©2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 34
Fo
rI
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tO
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A23
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Allwinner Technology Co., Ltd.
4th Floor, B6 Building, NO.1, Software Road,
Zhuhai, Guangdong Province, China
Contact Us: [email protected]
www.allwinnertech.com
A23 Datasheet (Revision 1.0)
Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved.
Page 35

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