Micross AS4DDR232M72APBG 4-bit prefetch architecture Datasheet

iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
32Mx72 DDR2 SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
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BENEFITS
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Military Temp
Package:
• 255 Plastic Ball Grid Array (PBGA), 25 x 32mm
• 1.27mm pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V ±0.1V power supply and I/O (VCC/VCCQ)
Programmable CAS latency: 3, 4, 5, or 6
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Organized as 32M x 72 w/ support for x80
Weight: AS4DDR232M72APBG ~ 3.5 grams typical
 SPACE conscious PBGA defined for easy
SMT manufacturability (50 mil ball pitch)
 Reduced part count
 47% I/O reduction vs Individual CSP approach
 Reduced trace lengths for lower parasitic
capacitance
 Suitable for hi-reliability applications
 Upgradable to 64M x 72 density
(consult factory for info on
AS4DDR264M72PBG)
Configuration Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
32 Meg x 72
8 Meg x 16 x 4 Banks
8K
8K (A0‐A12)
4 (BA0‐BA1)
1K (A0‐A9)
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-1
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VCCL
VSSDL
2
VSSDL
B
2
2
2
2
3
3
C
2
2
VSSDL
D
2
2
3
3
VCCL
2
2
3
3
DQ64-79
3
2
2
3
3
A
AS4DDR232M72APBG
Rev. 1.1 12/12
VCCL
VSSDL
2
3
CS4\
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
RASx\,CASx\,WEx\
CKx,CKx\,CKEx
VCCL
VSSDL
A
2
CS0\
CS1\
CS2\
CS3\
VCCL
DQ0-15 B
DQ16-31 C
DQ32-47 D
1
DQ48-63
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
SDRAM-DDRII PINOUT TOP VIEW
Rev. A, 07/06 - X72/X80
SDRAM-DDRII Pinout Top View
Rev. B, 10/06 - X72/X80
1
a
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0
DQ14
DQ15
VSS
VSS
A9
A10
A11
A8
VCCQ
VCCQ
DQ16
DQ17
DQ31
VSS
a
b
DQ1
DQ2
DQ12
DQ13
VSS
VSS
A0
A7
A6
A1
VCC
VCC
DQ18
DQ19
DQ29
DQ30
b
c
DQ3
DQ4
DQ10
DQ11
VCC
VCC
A2
A5
A4
A3
VSS
VSS
DQ20
DQ21
DQ27
DQ28
c
d
DQ6
DQ5
DQ8
DQ9
VCCQ
VCCQ
A12/NC
DNU
DNU
DNU
VSS
VSS
DQ22
DQ23
DQ26
DQ25
d
e
DQ7
LDM0
VCC
UDM0
UDQS3 LDQS0 UDQS0
BA0
BA1
LDQS1 UDQS1
VREF
LDM1
VSS
NC
DQ24
e
f
CAS0\
WE0\
VCC
CLK0
LDQS3 UDQS3\ LDQS0\ UDQS0\
NC
UDQS1\ LDQS1\
RAS1\
WE1\
VSS
UDM1
CLK1
f
g
CS0\
RAS0\
VCC
CKE0
CLK0\
LDQS3\
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS1\
CS1\
VSS
CLK1\
CKE1
g
h
VSS
VSS
VCC
VCCQ
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VCC
VSS
VSS
VCCQ
VCC
h
j
VSS
VSS
VCC
VCCQ
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VCC
VSS
VSS
VCCQ
VCC
j
k
CLK3\
CKE3
VCC
CS3\
VSSQ
VSSQ
VSSQ
VSSQ
NC
CLK2\
CKE2
VSS
RAS2\
CS2\
k
l
NC
CLK3
VCC
CAS3\
RAS3\
ODT
LDQS4\
NC
NC
LDQS2\ UDQS2\ LDQS2
CLK2
VSS
WE2\
CAS2\ l
m
DQ56
UDM3
VCC
WE3\
LDM3
CKE4
UDM4
CLK4
CAS4\
WE4\
RAS4\
CS4\
UDM2
VSS
LDM2
DQ39
m
n
DQ57
DQ58
DQ55
DQ54
UDQS4
CLK4\
DQ73
DQ72
DQ71
DQ70
LDM4
UDQS2
DQ41
DQ40
DQ37
DQ38
n
p
DQ60
DQ59
DQ53
DQ52
VSS
VSS
DQ75
DQ74
DQ69
DQ68
VCC
VCC
DQ43
DQ42
DQ36
DQ35
p
r
DQ62
DQ61
DQ51
DQ50
VCC
VCC
DQ77
DQ76
DQ67
DQ66
VSS
VSS
DQ45
DQ44
DQ34
DQ33
r
t
VSS
DQ63
DQ49
DQ48
VCCQ
VCCQ
DQ79
DQ78
DQ65
DQ64
VSS
VSS
DQ47
DQ46
DQ32
VCC
t
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Ground
Level REF.
LDQS4 UDQS4\
Array Power
D/Q Power
Address
Data IO
CNTRL
ADDRESS-DNU
UNPOPULATED
NC
ADVANCE INFORMATION
AS4DDR232M72APBG
Rev. 1.1 12/12
2
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
BGA Locations
Symbol
Type
ODT
CNTL Input
On-Die-Termination: Registered High enables on data bus termination
CKx, CKx\
CNTL Input
Differential input clocks, one set for each x16bits
G4, G16, K13, M6, K2
CKEx
CNTL Input
Clock enable which activates all on silicon clocking circuitry
G1, G13, K16, K4, M12
F12, G2, K15, L5, M11
F1, G12, M9, L16, L4,
F2, F13, L15, M4, M10
E4, F15, M13, M7, M2
E2, E13, M15, M5, N11
E5, E7, E11, N12, N5
F6, F8, F10, K6, L11
CSx\
RASx\
CASx\
Wex\
UDMx
LDMx
UDQSx
UDQSx\
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
CNTL Input
Chip Selects, one for each 16 bits of the data bus width
Command input which along with CAS\, WE\ and CS\ define operations
Command input which along with RAS\, WE\ and CS\ define operations
Command input which along with RAS\, CAS\ and CS\ define operations
One Data Mask cntl. for each upper 8 bits of a x16 word
One Data Mask cntl. For each lower 8 bits of a x16 word
Data Strobe input for upper byte of each x16 word
Differential input of UDQSx, only used when Differential DQS mode is enabled
E6, E10, F5, K5, L12
F7, F11, G6, L7, L10
LDQSx
LDQSx\
CNTL Input
CNTL Input
Data Strobe input for lower byte of each x16 word
Differential input of LDQSx, only used when Differential DQS mode is enabled
L6
F4, F16, G5, G15, K12
Description
L13, L2, K1, M8, N6
A7, A8, A9, A10, B7,
Ax
Input
B8, B9, B10, C7, C8,
C9, C10, D7
D8, D9, D10
DNU
Future Input
E8, E9
BA0, BA1
Input
A2, A3, A4, A13, A14,
DQx
Input/Output
A15, B1, B2, B3, B4,
B13, B14, B15, B16,
C1, C2, C3, C4, C13,
C14, C15, C16, D1, D2,
D3, D4, D13, D14, D15,
D16, E1, E16, M1, M16,
N1, N2, N3, N4, N7, N8,
N9, N10, N13, N14,
N15, N16, PP1, P2, P3,
P4, P7, P8, P9, P10,
P13, P14, P15, P16,
R1, R2, R3, R4, R7, R8,
R9, R10, R13, R14,
R15, R16, T2, T3, T4,
T7, T8, T9, T10, T13,
T14, T15
E12
Vref
Supply
B11, B12, C5, C6,E3,
VCC
Supply
F3, G3, H3, H12, H16,
J3, J12, J16, K3, L3,
M3, P11, P12, R5, R6,
T16
A11, A12, D5, D6, H4,
VCCQ
Supply
H15, J4, J15, T5, T6
A5, A6, A16, B5, B6,
VSS
Supply
C11, C12, D11, D12,
E14, F14, G14, H1, H2,
H14, J1, J2, J5, J13,
J14, K14, L14, M14, P5,
P6, R11, R12, T1, T11,
T12, H5, H13
G7, G8, G9, G10, H7,
VSSQ
Supply
H8, H9, H10, J7, J8, J9,
J10, K7, K8, K9, K10
E15, F9, G11, H6, H11,
NC
J6, J11, K11, L1, L8, L9,
A1
UNPOPULATED
AS4DDR232M72APBG
Rev. 1.1 12/12
Array Address inputs providing ROW addresses for Active commands, and
the column address and auto precharge bit (A10) for READ/WRITE commands
Bank Address inputs
Data bidirectional input/Output pins
SSTL_18 Voltage Reference
Core Power Supply
I/O Power
Core Ground return
I/O Ground return
No connection
Unpopulated ball matrix location (location registration aid)
3
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
DESCRIPTION
The 2.4Gb DDR2 SDRAM, a high-speed CMOS, dynamic
random-access memory containing 2,684,354,560 bits.
Each of the five chips in the MCP are internally configured
as 4-bank DRAM. The block diagram of the device is
shown in Figure 2. Ball assignments and are shown in
Figure 3.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent
operation, thereby providing high, effective bandwidth by
hiding row precharge and activation time.
The 2.4Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer
two data words per clock cycle at the I/O balls. A
single read or write access for the x72 DDR2 SDRAM
effectively consists of a single 4n-bit-wide, one-clockcycle data transfer at the internal DRAM core and four
corresponding n-bit-wide, one-half-clock-cycle data
transfers at the I/O balls.
A self refresh mode is provided, along with a powersaving power-down mode.
All inputs are compatible with the JEDEC standard for
SSTL_18. All full drive-strength outputs are SSTL_18compatible.
GENERAL NOTES
• The functionality and the timing specifications
discussed in this data sheet are for the DLLenabled
mode of operation.
• Throughout the data sheet, the various figures and
text refer to DQs as ¡°DQ.¡± The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, each chip
is divided into 2 bytes, the lower byte and upper
byte. For the lower byte (DQ0¨CDQ7), DM refers to
LDM and DQS refers to LDQS. For the upper byte
(DQ8¨CDQ15), DM refers to UDM and DQS refers to
UDQS.
• Complete functionality is described throughout
the document and any page or diagram may have
been simplified to convey a topic and may not be
inclusive of all requirements.
• Any specific requirement takes precedence over a
general statement.
A bidirectional data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. There
are strobes, one for the lower byte (LDQS, LDQS#) and
one for the upper byte (UDQS, UDQS#).
The MCP DDR2 SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data
is referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR2 SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed.
The address bits registered coincident with the READ
or WRITE command are used to select the bank and the
starting column location for the burst access.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
The following sequence is required for power up and
initialization and is shown in Figure 4 on page 8.
1. Applying power; if CKE is maintained below 0.2 x
V CCQ, outputs remain disabled. To guarantee RTT
(ODT resistance) is off, VREF must be valid and a
low level must be applied to the ODT ball (all other
inputs may be undefined, I/Os and outputs must be
less than VCCQ during voltage ramp time to avoid
DDR2 SDRAM device latch-up). At least one of the
The DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with
another read, or a burst write of eight with another
write.
AS4DDR232M72APBG
Rev. 1.1 12/12
4
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
following two sets of conditions (A or B) must be met to
obtain a stable supply state (stable supply defi ned as
V C C , V C C Q , V R E F, a n d V T T a r e b e t w e e n t h e i r
minimum and maximum values as stated in Table20);
A. (single power source) The VCC voltage ramp from
300mV to V CC (MIN) must take no longer than
200ms; during the VCC voltage ramp, |VCC - VCCQ|
± 0.3V. Once supply voltage ramping is complete
(when V CCQ crosses V CC (MIN)), Table 20
specifications apply. • V CC , V CCQ are driven from a single power
converter output
• VTT is limited to 0.95V MAX
• V REF t r a c k s V CCQ/2; V REF m u s t b e w i t h i n
± 0.3V with respect to VCCQ/2 during supply ramp
time
• VCCQ > VREF at all times
B. (multiple power sources) V CC > V CCQ must be
maintained during supply voltage ramping, for both
AC and DC levels, until supply voltage ramping
completes (VCCQ crosses VCC [MIN]). Once supply
voltage ramping is complete, Table 20 specifications
apply.
• Apply V CC before or at the same time as
VCCQ; VCC voltage ramp time must be < 200ms
from when VCC ramps from 300mV to VCC (MIN)
• Apply VCCQ before or at the same time as VTT; the
VCCQ voltage ramp time from when VCC (MIN) is
achieved to when VCCQ (MIN) is achieved must be
<500ms; while VCC is ramping, current can be
supplied from VCC through the device to VCCQ
• VREF must track VCCQ/2, VREF must be within
± 0.3V with respect to VCCQ/2 during supply ramp
time; V CCQ > V REF must be met at all times
• Apply VTT; The VTT voltage ramp time from when
VCCQ (MIN) is achieved to when VTT (MIN) is achieved
must be no greater than 500ms
AS4DDR232M72APBG
Rev. 1.1 12/12
2. For a minimum of 200 µs after stable power nd clock
(CK, CK#), apply NOP or DESELECT commands and
take CKE HIGH.
3. Wa i t a m i n i m u m o f 4 0 0 n s , t h e n i s s u e a
PRECHARGE ALL command.
4. Issue an LOAD MODE command to the EMR(2). (To
issue an EMR(2) command, provide LOW to BA0,
provide HIGH to BA1.)
5. Issue a LOAD MODE command to the EMR(3). (To
issue an EMR(3) command, provide HIGH to BA0 and
BA1.)
6. Issue an LOAD MODE command to the EMR to enable
DLL. To issue a DLL ENABLE command, provide LOW
to BA1 and A0, provide HIGH to BA0. Bits E7, E8, and
E9 can be set to “0” or “1”; Micron recommends setting
them to “0”.
7. Issue a LOAD MODE command for DLL RESET. 200
cycles of clock input is required to lock the DLL. (To
issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA1, and BA0.) CKE must be HIGH the entire
time.
8. Issue PRECHARGE ALL command.
9. Issue two or more REFRESH commands, followed
by a dummy WRITE.
5
Micross Components reserves the right to change products or specifications without notice.
iPEM
iPEM
SDRAM-DDR2
2.4 Gb
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
AS4DDR232M72PBG
FIGURE 4 - POWER-UP AND
INITIALIZATION
FIGURE
4 – POWER-UP AND INITIALIZATION
Notes appear on page 7
Notes appear on page 9
VCC
VCCQ
t VTD1
VTT1
VREF
T0
CK
Ta0
tCK
CK#
tCL
Te0
Td 0
Tc0
Tb 0
Tg 0
Tf 0
Th 0
Ti 0
Tk 0
Tj 0
Tm 0
Tl 0
tCL
See
not e
3
SSTL_18
LVCM OS
CKE LOW LEVEL8 LOW LEVEL8
ODT
NOP2
COM M A ND
PRE
LM
LM
LM
LM
PRE
A 10 = 1
CODE
CODE
CODE
CODE
A 10 = 1
REF
REF
LM
LM
LM
VA LID3
CODE
CODE
CODE
VA LID
DM 7
A DDRESS9
DQS7
Hi g h -Z
DQ7
Hi g h -Z
RTT
Hi g h -Z
T = 200µ s (M IN)
Po w er -u p :
VCC an d st ab l e
cl o ck (CK, CK#)
DON’ T CA RE
AS4DDR232M72PBG
Rev. 0.0
07/06
AS4DDR232M72APBG
Rev. 1.1 12/12
T = 400n s
(M IN)
t RPA
t M RD
EM R(2)
t M RD
t M RD
t M RD
t RPA
EM R w i t h
DLL ENA BLE5
EM R(3)
M R w it h
DLL RESET
In d i cat es a b r eak i n
t i m e scal e
6
t RFC
t RFC
t M RD
t M RD
t M RD
See not e 4
EM R w i t h
M R w /o
DLL RESET OCD Def au l t 10
200 cycl es o f CK3
EM R w i t h
OCD Exi t 11
No r m al
Op er at i o n
AustinSemiconductor, Inc. • (512) 339-1188 • www.austinsemiconductor.com
6
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
NOTES:
1. A p p l y i n g p o w e r ; i f C K E i s m a i n t a i n e d b e l o w 0 . 2 x V C C Q ,
outputs remain disabled. To guarantee RTT (ODT resistance) is off,
VREF must be valid and a low level must be applied to the ODT ball (all
other inputs may be undefined, I/Os and outputs must be less
than VCCQ during voltage ramp time to avoid DDR2 SDRAM
device latch-up). At least one of the following two sets of conditions (A
or B) must be met to obtain a stable supply state (stable
supply defined as VCC, VCCQ,VREF, and VTT are between their
minimum and maximum values as stated in DC Operating Conditions table):
A. (single power source) The VCC voltage ramp from 300mV
to VCC(MIN) must take no longer than 200ms; during the VCC
voltage ramp, |VCC - VCCQ| < 0.3V. Once supply voltage
r a m p i n g i s c o m p l e t e ( w h e n V C C Q c r o s s e s V C C ( M I N ) , D C
Operating Conditions table specifications apply.
• VCC, VCCQ are driven from a single power converter output
• VTT is limited to 0.95V MAX
• VREF tracks VCCQ/2; VREF must be within ±3V with respect
to VCCQ/2 during supply ramp time.
• VCCQ > VREF at all times
B. (multiple power sources) VCC e” VCCQ must be maintained
during supply voltage ramping, for both AC and DC levels, until
supply voltage ramping completes (VCCQ crosses VCC [MIN]).
O n c e s u p p l y v o l t a g e r a m p i n g i s c o m p l e t e , D C O p e r a t i n g
Conditions table specifications apply.
• Apply VCC before or at the same time as VCCQ;
VCC voltage ramp time must be < 200ms from when VCC ramps from
300mV to VCC (MIN)
• Apply VCCQ before or at the same time as VTT; the VCCQ
voltage ramp time from when VCC (MIN) is achieved to when
VCCQ (MIN) is achieved must be < 500ms; while VCC is
ramping, current can be supplied from VCC through the device
to VCCQ
• VREF must track VCCQ/2, VREF must be within ±0.3V with
respect to VCCQ/2 during supply ramp time; VCCQ > VREF
must be met at all times
• Apply VTT; The VTT voltage ramp time from when VCCQ
(MIN) is achieved to when VTT (MIN) is achieved must be no
greater than 500ms
2. For a minimum of 200µs after stable power and clock (CK, CK#),
apply NOP or DESELECT commands and take CKE HIGH.
AS4DDR232M72APBG
Rev. 1.1 12/12
3. Wait a minimum of 400ns, then issue a PRECHARGE ALL command/
4. Issue an LOAD MODE command to the EMR(2). (To issue an
EMR(2) command, provide LOW to BA0, provide HIGH to BA1.)
5. Issue a LOAD MODE command to the EMR(3). (To issue an EMR(3)
command, provide HIGH to BA0 and BA1.)
6. Issue an LOAD MODE command to the EMR to enable DLL. To
issue a DLL E N A B L E c o m m a n d , p r o v i d e L O W t o B A 1 a n d A 0 ,
provide HIGH to BA0. Bits E7, E8, and E9 can be set to “0” or “1”;
Micron recommends setting them to “0.”
7. Issue a LOAD MODE command for DLL RESET. 200 cycles of
clock input i s r e q u i r e d t o l o c k t h e D L L . ( To i s s u e a D L L
RESET, provide HIGH to A8 and provide LOW to BA1, and BA0.) CKE
must be HIGH the entire time.
8. Issue PRECHARGE ALL command.
9. Issue two or more REFRESH commands, followed by a dummy WRITE.
10. Issue a LOAD MODE command with LOW to A8 to initialize
device operation (i.e., to program operating parameters without resetting the
DLL).
11. Issue a LOAD MODE command to the EMR to enable OCD default
by setting bits E7, E8, and E9 to “1,” and then setting all other
desired parameters.
12. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits
E7, E8, and E9 to “0,” and then setting all other desired parameters.
13. Issue a LOAD MODE command with LOW to A8 to initialize
device operation (i.e., to program operating parameters without resetting the
DLL).
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting
bits E7,E8, and E9 to “1,” and then setting all other desired parameters.
15. I s s u e a L O A D M O D E c o m m a n d t o t h e E M R t o
enable OCD exit by setting bits E7, E8, and E9 to “0,” and then
setting all other desired parameters. The DDR2 SDRAM is now
initialized and ready for normal operation 200 clocks after DLL RESET (in
step 7).
7
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AS4DDR232M72PBG
AS4DDR232M72APBG
MODE REGISTER (MR)
MODE REGISTER (MR)
The mode register is used to define the
FIGURE
5 –– MODE
MODE REGISTER
REGISTER(MR)
(MR)DEFINITION
DEFINITION
FIGURE 5
specific mode of
The
register
is usedThis
to define
the specific
mode
operation
of mode
the DDR2
SDRAM.
definition
includes
the of
of length,
the DDR2
SDRAM.
Thisoperating
definition mode,
includes
selectionoperation
of a burst
burst
type, CL,
the selection
of a burst length,
burst type, CL,
operating
DLL RESET,
write recovery,
and power-down
mode,
as
mode,
DLL5.RESET,
writeof
recovery,
and register
power-down
shown in
Figure
Contents
the mode
canmode,
be
as shown
in Figure
Contents
of the(LM)
modecommand.
register canIf be
altered by
re-executing
the5. LOAD
MODE
the useraltered
chooses
modify onlythe
a subset
of the MR
variables,
byto
re-executing
LOAD MODE
(LM)
command.
all variables
(M0–M14)
must
be programmed
when
theMR
If the user
chooses
to modify
only a subset
of the
command
is issued.
variables,
all variables (M0–M14) must be programmed
when the command is issued.
The mode register is programmed via the LM command
The mode register is programmed via the LM command
(bits BA1–BA0 = 0, 0) and other bits (M12–M0) will retain the
(bits BA1–BA0 = 0, 0) and other bits (M12–M0) will retain
stored information until it is programmed again or the device
the stored information until it is programmed again or
loses power (except for bit M8, which is selfclearing).
the device loses power (except for bit M8, which is selfReprogramming the mode register will not alter the contents
clearing). Reprogramming the mode register will not alter
of the memory array, provided it is performed correctly.
the contents of the memory array, provided it is performed
correctly.
The LM command can only be issued (or reissued) when all
The
canstate
only be
issued
(orand
reissued)
when all
banks are
inLM
thecommand
precharged
(idle
state)
no bursts
banks areThe
in the
precharged
state
(idle
state)
and notime
bursts
are in progress.
controller
must
wait
the
specified
are in initiating
progress.any
Thesubsequent
controller must
wait thesuch
specified
tMRD before
operations
as
t
timecommand.
MRD before
initiating
anyofsubsequent
operations
an ACTIVE
Violating
either
these requirements
such
as an ACTIVE
command. Violating either of these
will result
in unspecified
operation.
requirements will result in unspecified operation.
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
15 14 13 12 11 10
01 PD
MR
WR
PD mode
0
Fast Exit
(Normal)
1
1
Test
M8 DLL Reset
Slow Exit
(Low Power)
0
No
1
Yes
M11 M10 M9 WRITE RECOVERY
M15 M14
0
0
0
Reserved
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
Reserved
1
1
1
Reserved
Mo de Register Definition
0
0
Mode Register (MR)
0
1
Extended Mode Register (EMR)
1
0
Extended Mode Register (EMR2)
1
1
Extended Mode Register (EMR3)
M3
0
0
0
Reserved
0
0
1
Reserved
0
1
0
4
0
1
1
8
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
CAS Laten cy (CL)
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
Note: 1. Not used on this part
BURSTTYPE
TYPE
BURST
Accesseswithin
withinaa given
given burst
to be
Accesses
burst may
maybebeprogrammed
programmed
to be
either
sequential
or
interleaved.
The
burst
type
is
selected
either sequential or interleaved. The burst type is selected
M3,as
asshown
shown in Figure
ordering
of accesses
viavia
bitbitM3,
Figure5.5.The
The
ordering
of accesses
withina aburst
burstisis determined
determined by
thethe
burst
within
bythe
theburst
burstlength,
length,
burst
type,and
andthe
thestarting
starting column
in Table
type,
column address,
address,asasshown
shown
in Table
DDR2
SDRAMsupports
supports4-bit
4-bitburst
burst mode and
2. 2.
DDR2
SDRAM
and 8-bit
8-bitburst
burst
modeonly.
only.For
For 8-bit
8-bit burst
burst mode,
address
mode
mode,full
fullinterleave
interleave
address
ordering
is supported;
however,
sequential
address
ordering
is supported;
however,
sequential
address
ordering
is nibble-based.
is ordering
nibble-based.
8
8
M12
Mode Register (Mx)
M2 M1 M0 Burst Length
0 Normal
as shown in Figure
5. ReadBurst
and write
SDRAM
are in
burstlengthaccesses
is definedtobythe
bitsDDR2
M0–M3,
as shown
Figure
oriented,5.with
theand
burst
length
being programmable
to eitherare
Read
write
accesses
to the DDR2 SDRAM
four or burst-oriented,
eight. The burst
dete
rmines
theprogrammable
maximum
withlength
the burst
length
being
number to
of column
locations
that The
can be
accessed
a given
either four
or eight.
burst
length for
dete
rmines
READ orthe
WRITE
command.
maximum
number of column locations that can be
accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
columns equal to the burst length is effectively selected.
accesses for that burst take place within this block, meaning
All accesses
thatthe
burst
take
place within
this block,
that the burst
will wrap for
within
block
if a boundary
is reached.
meaning
that
the
burst
will
wrap
within
the
The block is uniquely selected by A2–Ai when BL = 4 block
and byif a
boundary
block
is significant
uniquely selected
A3–Ai when
BL = is
8 reached.
(where AiThe
is the
most
column by
BL =
4 and by A3–Ai
BL = 8(least
(where
addressA2–Ai
bit forwhen
a given
configuration).
Thewhen
remaining
Ai
is
the
most
significant
column
address
bit
for
a
given
significant) address bit(s) is (are) used to select the starting
configuration).
The
remaining
(least
significant)
address
location within the block. The programmed burst length applies
bit(s) isand
(are)
used to
select the starting location within the
to both READ
WRITE
bursts.
block. The programmed burst length applies to both READ
and WRITE bursts.
AS4DDR232M72APBG
Rev. 1.1 12/12
8 7 6 5 4 3 2 1 0
DLL TM CAS# Latency BT Burst Length
M7 Mo de
BURST LENGTH
BURST
LENGTH
Burst length
is defined
by bits M0–M3,
AS4DDR232M72PBG
Rev. 0.0
07/06
9
Address Bus
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2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
TABLE 2 - BURST DEFINITION
Burst
Length
A1
8
Type = Sequential
Type = Interleaved
DLL RESET is defined by bit M8, as shown in Figure 5.
Programming bit M8 to “1” will activate the DLL RESET
function. Bit M8 is self-clearing, meaning it returns back
to a value of ¡°0¡± after the DLL RESET function has been
issued.
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2
A1
A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
4
DLL RESET
Order of Accesses Within a Burst
Starting Column
Address
Anytime the DLL RESET function is used, 200 clock cycles
must occur before a READ command can be issued to allow
time for the internal clock to be synchronized with the external
clock. Failing to wait for synchronization to occur may result in
a violation of the tAC or tDQSCK parameters.
WRITE RECOVERY
Write recovery (WR) time is defined by bits M9-M11, as shown
in Figure 5. The WR register is used by the DDR2 SDRAM
during WRITE with auto precharge operation. During WRITE
with auto precharge operation, the DDR2 SDRAM delays the
internal auto precharge operation by WR clocks (programmed
in bits M9-M11) from the last data burst.
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block;
A0 selects the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block;
A0-1 select the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
WR values of 2, 3, 4, 5, or 6 clocks may be used for
programming bits M9-M11. The user is required to program
the value of WR, which is calculated by dividing tWR (in ns)
by tCK (in ns) and rounding up a non integer value to the next
integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved states
should not be used as unknown operation or incompatibility
with future versions may result.
OPERATING MODE
The normal operating mode is selected by issuing a
command with bit M7 set to ¡°0,¡± and all other bits set to
the desired values, as shown in Figure 5. When bit M7 is
“1,” no other bits of the mode register are programmed.
Programming bit M7 to ¡°1¡± places the DDR2 SDRAM into a
test mode that is only used by the manufacturer and should
not be used. No operation or functionality is guaranteed
if M7 bit is “1.”
POWER-DOWN MODE
Active power-down (PD) mode is defined by bit M12,
as shown in Figure 5. PD mode allows the user to
determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does
not apply to precharge PD mode.
When bit M12 = 0, standard active PD mode or “fast-exit”
active PD mode is enabled. The tXARD parameter is used
for fast-exit active PD exit timing. The DLL is expected to be
enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode or “slowexit”
active PD mode is enabled. The tXARD parameter is used
for slow-exit active PD exit timing. The DLL can be enabled,
but “frozen” during active PD mode since the exit-to-READ
command timing is relaxed. The power difference expected
between PD normal and PD low-power mode is defined in
the ICC table.
AS4DDR232M72APBG
Rev. 1.1 12/12
9
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SDRAM-DDR2
AS4DDR232M72APBG
AS4DDR232M72PBG
CAS LATENCY (CL)
The
CASLATENCY
latency (CL) is(CL)
defined by bits M4-M6, as shown
CAS
in Figure 5. CL is the delay, in clock cycles, between the
The CAS latency (CL) is defined by bits M4–M6, as shown
registration of a READ command and the availability of the first
in of
Figure
CL isThe
theCL
delay,
the
bit
output5.data.
can in
beclock
set tocycles,
3, 4, 5,between
or 6 clocks,
registration
READgrade
command
availability of
depending
onof
thea speed
option and
beingthe
used.
DDR2 SDRAM also supports a feature called posted CAS
additive latency (AL). This feature allows the READ command
DDR2 SDRAM also supports a feature called posted
to be issued prior to tRCD (MIN) by delaying the
CAS additive
latency
This feature
allows
the clocks.
READ
internal
command
to (AL).
the DDR2
SDRAM
by AL
or 6 clocks,
depending
the speed
grade option
being
DDR2
SDRAM
does not on
support
any half-clock
latencies.
Reserved
used. states should not be used as unknown operation
or incompatibility with future versions may result.
assume
AL of
= 0.
command
registered
at clock
Examples
CLIf =a 3READ
and CL
= 4 areisshown
in Figure
6;
edge
n,
and
the
CL
is
m
clocks,
the
data
will
be
available
both assume AL = 0. If a READ command is registered
nominally coincident with clock edge n+m (this assumes
at clock edge n, and the CL is m clocks, the data will be
AL = 0).
command to be issued prior to tRCD (MIN) by delaying the
internal command
theCL
DDR2
SDRAM
clocks.
Examples
of CL = 3 to
and
= 4 are
shownby
in AL
Figure
6; both
the first bit of output data. The CL can be set to 3, 4, 5,
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
FIGURE 6 - CAS LATENCY (CL)
CK#
available nominally coincident with clock edge n+m (this
assumes AL = 0).
FIGURE 6 – CAS LATENCY (CL)
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
DQS, DQS#
DOUT
n
DQ
CL = 3 (AL = 0)
CK#
DOUT
n+1
DOUT
n+2
DOUT
n+3
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
DQS, DQS#
DOUT
n
DQ
CL = 4 (AL = 0)
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal t AC, t DQSCK, and t DQSQ
AS4DDR232M72PBG
AS4DDR232M72APBG
Rev.1.1
0.012/12 07/06
Rev.
DOUT
n+1
TRANSITIONING DATA
10
10
DOUT
n+2
DOUT
n+3
DON’T CARE
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AS4DDR232M72APBG
AS4DDR232M72PBG
EXTENDED MODE REGISTER (EMR)
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the memory
array, provided it is performed correctly.
The extended mode register controls functions beyond those
controlled
by the mode
register;REGISTER
these additional functions
EXTENDED
MODE
(EMR) are
DLL enable/disable, output drive strength, on die termination
The (RTT),
extended
mode
registerdriver
controls
functions
beyond
(ODT)
posted
AL, off-chip
impedance
calibration
those
controlled
by
the
mode
register;
these
additional
(OCD), DQS# enable/disable, RDQS/RDQS# enable/disable,
functions
are DLL enable/disable,
output
drive strength,
and
output disable/enable.
These functions
are controlled
via the
bits
in Figure 7.(ODT)
The EMR
is programmed
the LOAD
onshown
die termination
(RTT),
posted AL, via
off-chip
driver
MODE
(LM) command
and will
retainDQS#
the stored
information
impedance
calibration
(OCD),
enable/disable,
until it is programmed again or the device loses power.
the EMR
will
alterare
theidle
contents
the
TheReprogramming
EMR must be loaded
when
allnot
banks
and noofbursts
are memory
in progress,
and
the controller
must waitcorrectly.
the specified time
array,
provided
it is performed
tMRD before initiating any subsequent operation. Violating either
The EMR must be loaded when all banks are idle and
of these requirements could esult in unspecified operation.
no bursts are in progress, and the controller must wait
the specified time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
RDQS/RDQS# enable/disable, and output disable/enable.
These functions are controlled via the bits shown in
Figure 7. The EMR is programmed via the LOAD MODE
(LM) command and will retain the stored information
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3
15 14
13
MRS
12
11
10
9
8
7
5
4
3
A1 A0
2
1
0
02 out RDQS DQS# OCD Program Rtt Posted CAS# Rtt ODS DLL
E12
Outputs
0
Enabled
1
Disabled
0
No
1
Yes
Enable
1
Disable
Extended Mode
Register (Ex)
E0
DLL Enable
0
Enable (Normal)
Rtt Disabled
1
Disable (Test/Debug)
0
0
0
1
75Ω
1
0
150Ω
E1
1
1
50Ω
0
Full Strength (18 Ω target)
1
Reduced Strength (40 Ω target)
E10 DQS# Enab le
0
Address Bus
E6 E2 Rtt (nominal)
E11 RDQS Enab le
Output Drive Strength
E5 E4 E3 Poste d CAS# Add itive Laten cy (AL)
E9 E8 E7 OCD Operation
E15 E14
6
A2
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
0
0
0
OCD Not Supported
0
0
1
Reserved
1
0
1
Reserved
0
1
0
Reserved
1
1
0
Reserved
1
0
0
Reserved
1
1
1
Reserved
1
1
1
OCD default state
1
1
Mo de Register Set
Mode Register Set (MR S)
0
0
0
1
Extended Mode Register (EMR S)
1
0
Extended Mode Register (EMR S2)
1
1
Extended Mode Register (EMR S3)
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is finished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
AS4DDR232M72APBG
AS4DDR232M72PBG
Rev.
1.10.0
12/12 07/06
Rev.
11
11
Micross
Components reserves
the• right
change products
or specifications without notice.
AustinSemiconductor,
Inc.
(512)to339-1188
• www.austinsemiconductor.com
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
DLL ENABLE/DISABLE
OUTPUT ENABLE/DISABLE
The DLL is automatically disabled when entering SELF
REFRESH operation and is automatically re-enabled and reset
upon exit of SELF REFRESH operation. Any time the DLL is
enabled (and subsequently reset), 200 clock cycles must occur
before a READ command can be issued, to allow time for the
internal clock to synchronize with the external clock. Failing to
wait for synchronization to occur may result in a violation of
the tAC or tDQSCK parameters.
ON-DIE TERMINATION (ODT)
The OUTPUT ENABLE function is defined by bit E12, as shown
in Figure 7. When enabled (E12 = 0), all outputs (DQs, DQS,
DQS#, RDQS, RDQS#) function normally. When disabled (E12
= 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS,
RDQS#) are disabled, thus removing output buffer current.
The output disable feature is intended to be used during ICC
characterization of read current.
The DLL may be enabled or disabled by programming bit
E0 during the LM command, as shown in Figure 7. The DLL
must be enabled for normal operation. DLL enable is required
during power-up initialization and upon returning to normal
operation after having disabled the DLL for the purpose of
debugging or evaluation. Enabling the DLL should always be
followed by resetting the DLL using an LM command.
ODT effective resistance, RTT (EFF), is defined by bits E2
and E6 of the EMR, as shown in Figure 7. The ODT feature
is designed to improve signal integrity of the memory channel
by allowing the DDR2 SDRAM controller to independently
turn on/off ODT for any or all devices. RTT effective resistance
values of 50Ω, 75Ω, and 150Ω are selectable and apply
to each DQ, DQS/DQS#, RDQS/ RDQS#, UDQS/UDQS#,
LDQS/LDQS#, DM, and UDM/ LDM signals. Bits (E6, E2)
determine what ODT resistance is enabled by turning on/off
“sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
elected by enabling switch “sw1,” which enables all R1 values
that are 150Ω each, enabling an effective resistance of 75Ω
(RTT2(EFF) = R2/2). Similarly, if “sw2” is enabled, all R2 values
that are 300Ω each, enable an effective ODT resistance of
150Ω (RTT2(EFF) = R2/2). Switch “sw3” enables R1 values
of 100Ω enabling effective resistance of 50Ω Reserved states
should not be used, as unknown operation or incompatibility
with future versions may result.
OUTPUT DRIVE STRENGTH
The output drive strength is defined by bit E1, as shown
in Figure 7. The normal drive strength for all outputs are
specified to be SSTL_18. Programming bit E1 = 0 selects
normal (full strength) drive strength for all outputs. Selecting
a reduced drive strength option (E1 = 1) will reduce all outputs
to approximately 60 percent of the SSTL_18 drive strength.
This option is intended for the support of lighter load and/or
point-to-point environments.
DQS# ENABLE/DISABLE
The ODT control ball is used to determine when RTT(EFF)
is turned on and off, assuming ODT has been enabled via
bits E2 and E6 of the EMR. The ODT feature and ODT input
ball are only used during active, active power-down (both
fast-exit and slow-exit modes), and precharge powerdown
modes of operation. ODT must be turned off prior to entering
self refresh. During power-up and initialization of the DDR2
SDRAM, ODT should be disabled until issuing the EMR
command to enable the ODT feature, at which point the ODT
ball will determine the RTT(EFF) value. Any time the EMR
enables the ODT function, ODT may not be driven HIGH until
eight clocks after the EMR has been enabled. See “ODT Timing”
section for ODT timing diagrams.
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is
the complement of the differential data strobe pair DQS/DQS#.
When disabled (E10 = 1), DQS is used in a single ended mode
and the DQS# ball is disabled. When disabled, DQS# should
be left floating. This function is also used to enable/disable
RDQS#. If RDQS is enabled (E11 = 1) and DQS# is enabled
(E10 = 0), then both DQS# and RDQS# will be enabled.
AS4DDR232M72APBG
Rev. 1.1 12/12
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2.4 Gb SDRAM-DDR2
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
AS4DDR232M72PBG
POSTED CAS ADDITIVE LATENCY (AL)
Posted CASCAS
additive
latency (AL)
is supported
to make
POSTED
ADDITIVE
LATENCY
(AL)
In this operation, the DDR2 SDRAM allows a READ or
Posted
CAS additive
(AL) efficient
is supported
make the
the command
andlatency
data bus
for to
sustainable
command
andindata
bus
efficientBits
for sustainable
bandwidths
bandwidths
DDR2
SDRAM.
E3–E5 define
the value
inofDDR2
E3–E5
the value
AL,user
as
AL, asSDRAM.
shown inBitsFigure
7. define
Bits E3–E5
allowofthe
shown
in
Figure
7.
Bits
E3–E5
allow
the
user
to
program
the
to program the DDR2 SDRAM with an inverse AL of 0, 1,
DDR2 SDRAM with an inverse AL of 0, 1, 2, 3, or 4 clocks.
2, 3, or 4 clocks. Reserved states should not be used as
Reserved states should not be used as unknown operation
unknown operation or incompatibility with future versions
or incompatibility with future versions may result.
In WRITE
this operation,
the DDR2
allows
READ(MIN)
or WRITE
command
to be SDRAM
issued prior
to atRCD
with
t
command
to be issued
tRCD
(MIN)Awith
the application
requirement
the requirement
thatprior
AL ≤toRCD
(MIN).
typical
t
that
AL d”
tRCD
(MIN).
A typical
using
feature
using
this
feature
would
set ALapplication
= tRCD (MIN)
- 1xthis
CK.
The
would
set
AL
=
tRCD (MIN) - 1x tCK. The READ or WRITE
READ or WRITE command is held for the time of the AL
command is held for the time of the AL before it is issued internally
before it is issued internally to the DDR2 SDRAM device.
to the DDR2 SDRAM device. RL is controlled by the sum of AL
RL is controlled by the sum of AL and CL; RL = AL+CL.
and CL; RL = AL+CL. Write latency (WL) is equal to RL minus
Write
latency
(WL)
is equal
to RL minus one clock; WL =
one
clock;
WL = AL
+ CL
- 1 x tCK.
may result.
AL + CL - 1 x tCK.
FIGURE 8 - EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2
15 14 13 12 11 10 9 8 7 6 5 4 3 2
EMR2 01 01 01 01 01 01 01 01 01 01 01 01
M15 M14
Mode Register Definition
0
0
Mo de Register (MR)
0
1
Extended Mo de Register (EMR)
1
0
Extended Mo de Register (EMR2)
1
1
Extended Mo de Register (EMR3)
A1 A0
1
0
1
0
01
Add ress Bus
Extended Mo de
Reg ister (Ex)
E7 High Temperature Self Refresh rate enable
Commer cial-Temperature default
Industrial-Temperature option;
use if T C exceeds 85°C
0
1
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
AS4DDR232M72PBG
Rev. 0.0
07/06
AS4DDR232M72APBG
Rev. 1.1 12/12
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2.4 Gb SDRAM-DDR2
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
AS4DDR232M72PBG
iPEM
FIGURE 9 - EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2
15 14 13 12 11 10 9 8 7 6 5 4 3
EMR3 01 01 01 01 01 01 01 01 01 01 01
M15 M14
2
01
A1 A0
1 0
01 01
Add ress Bus
Extended Mo de
Register (Ex)
Mode Register Definition
0
0
Mo de Register (MR)
0
1
Extended Mo de Register (EMR)
1
0
Extended Mo de Register (EMR2)
1
1
Extended Mo de Register (EMR3)
Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
EXTENDEDMODE
MODE
REGISTER
EXTENDED
REGISTER
2 2
EMR3 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
EMR3
be loaded
all banks are idle and no bursts
t
specifimust
ed time
MRD when
before
initiating any subsequent
are in progress, and the controller must wait the specifi ed time
operation. Violating either of these requirements could
tMRD before initiating any subsequent operation. Violating
result in
operation.could result in unspecified
either
ofunspecified
these requirements
The
functions
Theextended
extendedmode
mode register
register 22 (EMR2) controls functions
beyond
register.
Currently
all
beyondthose
thosecontrolled
controlledbybythe
themode
mode
register.
Currently
bits
in
EMR2
are
reserved,
as
shown
in
Figure
8.
The
EMR2
all bits in EMR2 are reserved, as shown in Figure 8. The
is programmed via the LM command and will retain the stored
EMR2 is programmed via the LM command and will
information until it is programmed again or the device loses
retain the stored information until it is programmed again
power. Reprogramming the EMR will not alter the contents of
or memory
the device
loses
power.it Reprogramming
the EMR will
the
array,
provided
is performed correctly.
operation.
COMMAND TRUTH TABLES
COMMAND
TRUTH
TABLES
The following tables
provide
a quick reference of DDR2
not alter the contents of the memory array, provided it is
performed
correctly.
EMR2
must be
loaded when all banks are idle and no bursts are
The
following
tablescommands,
provide a quick
reference
of DDR2
SDRAM
SDRAM
available
including
CKE
power-down
available
commands,
including
CKE power-down modes, and
modes, and
bank-to-bank
commands.
bank-to-bank commands.
inEMR2
progress,
andbe
theloaded
controller
mustall
wait
the specified
tMRD
must
when
banks
are idletime
and
no
before
initiating
any
subsequent
operation.
Violating
either
of
bursts are in progress, and the controller must wait the
these requirements
t could result in unspecified operation.
specified time MRD before initiating any subsequent
operation. Violating either of these requirements could
EXTENDED
MODE
REGISTER 3
result in unspecified
operation.
The extended mode register 3 (EMR3) controls functions
beyond those controlled by the mode register. Currently, all
EXTENDED
MODEasREGISTER
bits
in EMR3 are reserved,
shown in Figure39. The EMR3
isThe
programmed
via
the
LM
command
and will
retain the
stored
extended mode register 3 (EMR3)
controls
functions
information
until
it
is
programmed
again
or
the
device
loses
beyond those controlled by the mode register. Currently,
power.
EMR will
alter the
of
all bitsReprogramming
in EMR3 are the
reserved,
asnot
shown
in contents
Figure 9.
the
memory
provided it via
is performed
correctly. and will
The
EMR3 array,
is programmed
the LM command
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
AS4DDR232M72PBG
AS4DDR232M72APBG
Rev.1.1
0.012/12 07/06
Rev.
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iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
TABLE 3 - TRUTH TABLE - DDR2 COMMANDS
CKE
Function
RAS#
CAS#
WE#
BA1
A12
BA0
A11
Previous
Cycle
Current
Cycle
CS#
A10
A9-A0
LOAD MODE
H
H
L
L
L
L
BA
REFRESH
H
H
L
L
L
H
X
X
X
X
SELF-REFRESH Entry
H
L
L
L
L
H
X
X
X
X
SELF-REFRESH exit
L
H
X
X
X
X
7
Single Bank Precharge
H
X
X
L
X
2
All banks PRECHARGE
X
H
X
Bank Activate
OP CODE
Notes
2
H
X
X
X
L
H
H
H
H
L
L
H
L
H
H
L
L
H
L
X
H
H
L
L
H
L
BA
WRITE
H
H
L
L
H
L
BA
WRITE with auto precharge
H
H
L
H
L
L
BA
READ
H
H
L
H
L
H
BA
READ with auto precharge
H
H
L
H
L
H
BA
NO OPERATION
H
X
L
H
H
H
X
X
X
X
Device DESELECT
H
X
H
X
X
X
X
X
X
X
H
X
X
X
L
H
H
H
X
X
X
X
4
X
X
X
X
4
POWER-DOWN entry
H
L
POWER-DOWN exit
L
H
H
X
X
X
L
H
H
H
ROW ADDRESS
Column
Address
Column
Address
Column
Address
Column
Address
L
H
L
L
Column
Address
Column
Address
Column
Address
Column
Address
2,3
2,3
2,3
2,3
Note: 1. All DDR2-SDRAM commands are defined by staes of CS#, RAS#, CAS#, WE#, and CKE a
the rising edge of the clock.
2. Bank addresses (BA) BA0-BA12 determine which bank is to be operated upon. BA during a LM
command selects which mode register is programmed.
3. Burst reads or writes at BL=4 cannot be terminated or interrupted.
4. The power down mode does not perform any REFRESH operations. The duration of power down
is therefore limited by the refresh requirements outlined in the AC parametric section.
5. The state of ODT does not effect the states described in this table. The ODT function is not available
during self refresh. See “On Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level)
7. Self refresh exit is asynchronous.
AS4DDR232M72APBG
Rev. 1.1 12/12
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2.4 Gb SDRAM-DDR2
AS4DDR232M72PBG
DESELECT
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
The DESELECT function (CS# HIGH) prevents new
commands from being executed by the DDR2 SDRAM.
The DDR2 SDRAM is effectively deselected. Operations
already in progress are not affected.
entered. The same procedure is used to convert other
specification limits from time units to clock cycles. For
example, a tRCD (MIN) specification of 20ns with a 266
MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded
up to 6.
DESELECT
NO
OPERATION (NOP)
The DESELECT function (CS# HIGH) prevents new commands
AAsubsequent
subsequentACTIVE
ACTIVEcommand
command to
to aadifferent
differentrow
rowininthe
the
same
bank
can
only
be
issued
after
the
previous
active
same bank can only be issued after the previous active
row
row
closed
(precharged).
The minimum
time
hashas
beenbeen
closed
(precharged).
The minimum
time interval
betweenbetween
successive
ACTIVE commands
to the same to
bank
interval
successive
ACTIVE commands
theis
defined
by tis
RCdefined by tRC
same
bank
The
NO
OPERATION
command
used
to instruct
from
being
executed by(NOP)
the DDR2
SDRAM.isThe
DDR2
SDRAM
is effectively
deselected.
Operations
already
in progress
are
the
selected DDR2
SDRAM
to perform
a NOP
(CS# is
not affected.
LOW;
RAS#, CAS#, and WE are HIGH). This prevents
unwanted commands from being registered during idle
(NOP)
orNO
waitOPERATION
states. Operations
already in progress are not
The NO OPERATION (NOP) command is used to instruct the
affected.
AAsubsequent
subsequentACTIVE
ACTIVEcommand
commandtotoanother
anotherbank
bankcan
canbe
be
issued
while
the
first
bank
is
being
accessed,
which
results
issued while the first bank is being accessed, which results in
inaareduction
reductionofoftotal
totalrow-access
row-access
overhead.
minimum
overhead.
TheThe
minimum
time
time
interval
between
successive
ACTIVE
commands
to
interval
between
successive
ACTIVE
commands
to different
t
different
defined
banks isbanks
definedisby
tRRD. by RRD
selected DDR2 SDRAM to perform a NOP (CS# is LOW; RAS#,
CAS#, and WE are HIGH). This prevents unwanted commands
LOAD
MODE (LM)
from being registered during idle or wait states. Operations
The
mode
arenot
loaded
via inputs BA1–BA0, and
already
in registers
progress are
affected.
A12–A0. BA1–BA0 determine which mode register will
beLOAD
programmed.
“Mode Register (MR)”. The LM
MODESee
(LM)
command
only beare
issued
when
banksBA1–BA0,
are idle, and
The modecan
registers
loaded
viaallinputs
and
BA1–BA0
determine
which mode
register
will be
a A12–A0.
subsequent
execute
able command
cannot
be issued
t
programmed.
See “Mode Register (MR)”. The LM command
until
MRD is met.
FIGUREFIGURE
10 - ACTIVE
10 –COMMAND
ACTIVE COMMAND
can only be issued when all banks are idle, and a subsequent
execute able command cannot be issued until tMRD is met.
BANK/ROW ACTIVATION
CK#
BANK/ROW
ACTIVATION
ACTIVE
COMMAND
CK
ACTIVE COMMAND
The
commandisisused
used
open
(or activate)
TheACTIVE
ACTIVE command
to to
open
(or activate)
a rowain
row
in
a
particular
bank
for
a
subsequent
access.
The
a particular bank for a subsequent access. The value on
the
value
on the
BA1–BA0
selects
the address
bank, and
the
BA1–BA0
inputs
selectsinputs
the bank,
and the
provided
address
on inputs
A12–A0
selects
row.(or
on inputsprovided
A12–A0 selects
the row.
This row
remainsthe
active
open)
for remains
accesses active
until a PRECHARGE
is issued
This
row
(or open) forcommand
accesses
until
that bank. A PRECHARGE
must
issued
before
a toPRECHARGE
commandcommand
is issued
to be
that
bank.
A
opening a different
row in the
same
bank. before opening
PRECHARGE
command
must
be issued
a different row in the same bank.
CKE
CS#
RAS#
CAS#
ACTIVE OPERATION
Before any OPERATION
READ or WRITE commands can be issued to a
ACTIVE
bank within the DDR2 SDRAM, a row in that bank must be
WE#
Before
any
READ oreven
WRITE
commands
can beisissued
to
opened
(activated),
when
additive latency
used. This
a is
bank
within thevia
DDR2
SDRAM,
a row inwhich
that bank
must
accomplished
the ACTIVE
command,
selects
both
bank and
the row to
be activated.
bethe
opened
(activated),
even
when additive latency is used.
This is accomplished via the ACTIVE command, which
After aboth
row is
opened
with the
an ACTIVE
command,
a READ or
selects
the
bank and
row to be
activated.
WRITE command may be issued to that row, subject to the
After
a specification.
row is opened
with(MIN)
an ACTIVE
command,
READ
tRCD
tRCD
should be
divided bya the
clock
orperiod
WRITE
command
may
be
issued
to
that
row,
subject
to
and rounded up to the next whole number to determine
t
thetRCD
earliest
clock edge after
ACTIVE
command
on which
the
specification.
RCDthe
(MIN)
should
be divided
by
a READ
or WRITE
command
benext
entered.
same
the
clock period
and rounded
up can
to the
wholeThe
number
is used
convertclock
other specification
limitsACTIVE
from time
toprocedure
determine
the to
earliest
edge after the
units to clock
cycles.aFor
example,
a tRCDcommand
(MIN) specification
command
on which
READ
or WRITE
can be
of 20ns with a 266 MHz clock (tCK = 3.75ns) results in 5.3
clocks, rounded up to 6.
AS4DDR232M72PBG
Rev. 0.0
07/06
AS4DDR232M72APBG
Rev. 1.1 12/12
ADDRESS
Row
BANK ADDRESS
Bank
DON’T CARE
16
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SDRAM-DDR2
2.4 2.4
GbGb
SDRAM-DDR2
AS4DDR232M72PBG
AS4DDR232M72APBG
READ
COMMAND
READ
COMMAND
TheThe
READ
command
is is
used
toto
initiate
READ
command
used
initiatea aburst
burstread
readaccess
access
to an
active
row.
The
to an
active
row.
Thevalue
valueononthe
theBA1–BA0
BA1–BA0inputs
inputsselects
selects
the bank, and the address provided on inputs A0–i (where
the bank, and the address provided on inputs A0–i (where
i = A9) selects the starting column location. The value on
i = A9) selects the starting column location. The value on
input A10 determines whether or not auto precharge is used.
inputprecharge
A10 determines
whether
or being
not auto
precharge
If auto
is selected,
the row
accessed
will beis
used.
If
auto
precharge
is
selected,
the
row
being
accessed
precharged at the end of the READ burst; if auto precharge
will be
precharged
at the
of the
READ
if auto
is not
selected,
the row
willend
remain
open
for burst;
subsequent
precharge is not selected, the row will remain open for
accesses.
FIGURE 11 - READ COMMAND
subsequent accesses.
FIGURE 11 – READ COMMAND
READ OPERATION
READ
READ
burstsOPERATION
are initiated with a READ command. The starting
column
and
bank
addresses
the READ
READ bursts are
initiated are
with provided
a READ with
command.
The
command and auto precharge is either enabled or disabled for
starting column and bank addresses are provided with the
that burst access. If auto precharge is enabled, the row being
READ command and auto precharge is either enabled or
accessed is automatically precharged at the completion of the
disabled
that burstisaccess.
If auto
enabled,
burst.
If autoforprecharge
disabled,
the precharge
row will beisleft
open
thethe
row
being accessed
is automatically precharged at the
after
completion
of the burst.
CK#
CK
CKE
CS#
completion of the burst. If auto precharge is disabled, the
row will
be left
openthe
after
the data-out
completion
of the from
burst.the
During
READ
bursts,
valid
element
starting
column
available
READ
latency
(RL)
During
READaddress
bursts, will
the be
valid
data-out
element
from
the
clocks
later.
RL
is
defined
as
the
sum
of
AL
and
CL;
RL
=
AL
starting column address will be available READ latency
+ CL. The value for AL and CL are programmable via the MR
(RL) clocks later. RL is defined as the sum of AL and CL;
and EMR commands, respectively. Each subsequent data-out
RL = AL + CL. The value for AL and CL are programmable
element will be valid nominally at the next positive or negative
viaedge
the (i.e.,
MR and
commands,
clock
at theEMR
next crossing
of CKrespectively.
and CK#). Each
RAS#
CAS#
WE#
subsequent data-out element will be valid nominally at
the next positive
edgealong
(i.e.,with
at the
next
DQS/DQS#
is drivenor
bynegative
the DDR2clock
SDRAM
output
crossing
of CK
and
CK#).
data.
The initial
LOW
state
on DQS and HIGH state on DQS#
ADDRESS
is known
as theisread
preamble
The LOWalong
statewith
on
DQS/DQS#
driven
by the(tRPRE).
DDR2 SDRAM
DQS
and HIGH
stateinitial
on DQS#
with the
data-out
output
data. The
LOWcoincident
state on DQS
andlast
HIGH
state
element is known as the read postamble (tRPST).t
Col
ENABLE
AUTO PRECHARGE
on DQS# is known as the read preamble ( RPRE). The
LOW state on DQS and HIGH state on DQS# coincident
Upon completion of a burst, assuming no other commands
with
theinitiated,
last data-out
is known as the read
have
been
the DQ element
will go High-Z.
postamble (tRPST).
A10
DISABLE
BANK ADDRESS
Data
fromcompletion
any READ of
burst
may be
concatenated
withcommands
data from
Upon
a burst,
assuming
no other
a subsequent
READ command
to provide
a continuous flow
have been initiated,
the DQ will
go High-Z.
of data. The first data element from the new burst follows the
fromofany
READ burst
with
lastData
element
a completed
burst.may
The be
newconcatenated
READ command
databefrom
a subsequent
to provide
should
issued
x cycles after READ
the first command
READ command,
wherea
continuous
of data. The first data element from the
x equals
BL / 2 flow
cycles.
Bank
DON’T CARE
new burst follows the last element of a completed burst.
The new READ command should be issued x cycles after
the first READ command, where x equals BL / 2 cycles.
AS4DDR232M72PBG
Rev. 0.0
07/06
AS4DDR232M72APBG
Rev. 1.1 12/12
17
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iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
WRITE COMMAND
The WRITE command is used to initiate a burst write access
to an active row. The value on the BA1–BA0 inputs selects the
bank, and the address provided on inputs A0–9 selects the
starting column location. The value on input A10 determines
whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the
end of the WRITE burst; if auto precharge is not selected, the
row will remain open for subsequent accesses.
The time between the WRITE command and the fi rst rising
DQS edge is WL ± tDQSS. Subsequent DQS positive rising
edges are timed, relative to the associated clock edge, as ±
tDQSS. tDQSS is specified with a relatively wide range (25
percent of one clock cycle). All of the WRITE diagrams show
the nominal case, and where the two extreme cases (tDQSS
[MIN] and tDQSS [MAX]) might not be intuitive, they have also
been included. Upon completion of a burst, assuming no other
commands have been initiated, the DQ will remain High-Z and
any additional input data will be ignored.
Input data appearing on the DQ is written to the memory array
subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW, the corresponding
data will be written to memory; if the DM signal is registered
HIGH, the corresponding data inputs will be ignored, and a
WRITE will not be executed to that byte/column location.
Data for any WRITE burst may be concatenated with a
subsequent WRITE command to provide continuous flow of
input data. The fi rst data element from the new burst is applied
after the last element of a completed burst. The new WRITE
command should be issued x cycles after the first WRITE
command, where x equals BL/2.
WRITE OPERATION
WRITE bursts are initiated with a WRITE command, as shown
in Figure 12. DDR2 SDRAM uses WL equal to RL minus one
clock cycle [WL = RL - 1CK = AL + (CL - 1CK)]. The starting
column and bank addresses are provided with the WRITE
command, and auto precharge is either enabled or disabled
for that access. If auto precharge is enabled, the row being
accessed is precharged at the completion of the burst. For the
generic WRITE commands used in the following illustrations,
auto precharge is disabled.
DDR2 SDRAM supports concurrent auto precharge options,
as shown in Table 4.
DDR2 SDRAM does not allow interrupting or truncating any
WRITE burst using BL = 4 operation. Once the BL = 4 WRITE
command is registered, it must be allowed to complete the
entire WRITE burst cycle. However, a WRITE (with auto
precharge disabled) using BL = 8 operation might be interrupted
and truncated ONLY by another WRITE burst as long as the
interruption occurs on a 4-bit boundary, due to the 4n prefetch
architecture of DDR2 SDRAM. WRITE burst BL = 8 operations
may not to be interrupted or truncated with any command
except another WRITE command.
During WRITE bursts, the first valid data-in element will be
registered on the first rising edge of DQS following the WRITE
command, and subsequent data elements will be registered on
successive edges of DQS. The LOW state on DQS between
the WRITE command and the first rising edge is known as the
write preamble; the LOW state on DQS following the last data-in
element is known as the write postamble.
AS4DDR232M72APBG
Rev. 1.1 12/12
Data for any WRITE burst may be followed by a subsequent
READ command. The number of clock cycles required to meet
tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any
WRITE burst may be followed by a subsequent PRECHARGE
command. tWT starts at the end of the data burst, regardless
of the data mask condition.
18
Micross Components reserves the right to change products or specifications without notice.
iPEM
iPEM
2.42.4
GbGbSDRAM-DDR2
SDRAM-DDR2
AS4DDR232M72APBG
AS4DDR232M72PBG
FIGURE 12 - WRITE COMMAND
FIGURE 12 – WRITE COMMAND
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ADDRESS
CA
EN AP
A10
DIS AP
BANK ADDRESS
BA
DON’T CARE
Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and
DIS AP = disable auto precharge.
TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE
From Command (Bank n)
To Command (Bank m)
Minimum Delay (With Concurrent
Auto Precharge)
READ OR READ w/AP
(CL-1) + (BL/2) + tWTR
TABLE 4 - WRITE USING CONCURRENT AUTO PRECHARGE
WRITE with Auto Precharge
WRITE or WRITE w/AP
From Command (Bank n )
To
Command (Bank m )
PRECHARGE or ACTIVE
WRITE with Auto Precharge
READ OR READ w/ AP
WRITE OR WRITE w/ AP
PRECHARGE or ACTIVE
AS4DDR232M72PBG
Rev. 0.0
07/06
AS4DDR232M72APBG
Rev. 1.1 12/12
19
19
Units
t
CK
(BL/2) (With Concurrent tCK
Minimum Delay
Units
t
1 Precharge)
CK
Auto
(CL-1) + (BL/2) + tWTR
(BL/2)
1
t
CK
CK
t
CK
t
AustinSemiconductor, Inc. • (512) 339-1188 • www.austinsemiconductor.com
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
AS4DDR232M72PBG
PRECHARGE COMMAND
The PRECHARGE command, illustrated in Figure 13, is
used
to deactivate COMMAND
the open row in a particular bank or
PRECHARGE
the
row in allcommand,
banks. The
bank(s)
be 13,
available
Theopen
PRECHARGE
illustrated
in will
Figure
is used
for
a subsequent
rowrow
activation
a specified
time
RP)
to deactivate
the open
in a particular
bank or
the(topen
row inthe
all banks.
The bank(s)
will be available
for a subsequent
after
PRECHARGE
command
is issued,
except in
rowcase
activation
a specified
time
(tRP) afterwhere
the PRECHARGE
the
of concurrent
auto
precharge,
a READ or
command
is
issued,
except
in
the
case
of
concurrent
auto
WRITE command to a different bank is allowed
as long
precharge, where a READ or WRITE command to a different
as it does not interrupt the data transfer in the current
bank is allowed as long as it does not interrupt the data
bank and does not violate any other timing parameters.
transfer in the current bank and does not violate any other
Once
bank has been
it is inprecharged,
the idle state
timing aparameters.
Onceprecharged,
a bank has been
it is
and
must
be
activated
prior
to
any
READ
or READ
WRITE
in the idle state and must be activated prior to any
or
commands
being being
issuedissued
to that
bank.
AA
PRECHARGE
WRITE commands
to that
bank.
PRECHARGE
command
is allowed
allowedif ifthere
thereis is
open
in that
command is
nono
open
rowrow
in that
bankbank
(idle
state)state)
or if the
open row
is already
the process
(idle
or previously
if the previously
open
row isinalready
in theof
precharging.
However, the precharge
will be determined
process
of precharging.
However, period
the precharge
period
by
the
last
PRECHARGE
command
issued
to the command
bank.
will be determined by the last PRECHARGE
issued to the bank.
FIGURE 13 – PRECHARGE COMMAND
FIGURE 13 – PRECHARGE COMMAND
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
PRECHARGE OPERATION
Input A10 determines
whether one or all banks are to be
PRECHARGE
OPERATION
precharged, and in the case where only one bank is to be
ADDRESS
Input
A10 determines
whether select
one orthe
all banks
are to be
precharged,
inputs BA1–BA0
bank. Otherwise
BA1–BA0 areand
treated
ascase
“Don’t
Care.”only
When
banks
arebe
to
precharged,
in the
where
oneallbank
is to
be precharged,
inputs
BA1–BA0select
are treated
as “Don’t
Care.”
precharged,
inputs
BA1–BA0
the bank.
Otherwise
BA1–BA0 are treated as “Don’t Care.”
ALL BANKS
A10
ONE BANK
Once a bank has been precharged, it is in the idle state and
BA0, BA1
BA
When
allactivated
banks are
to be
precharged,
must be
prior
to any
READ or inputs
WRITE BA1–BA0
commands
are
treated
as
“Don’t
Care.”
Once
a
bank
has
been
being issued to that bank. tRPA timing applies when the
DON’T CARE
precharged,
it is(ALL)
in thecommand
idle state and
must be
activatedof
prior
PRECHARGE
is issued,
regardless
the
number
of banks
alreadycommands
open or closed.
a single-bank
to
any READ
or WRITE
beingIfissued
to that
t
PRECHARGE
command
is when
issued,the
tRP
timing applies. (ALL)
Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").
bank.
RPA timing
applies
PRECHARGE
command is issued, regardless of the number of banks issued). The differential clock should remain stable and meet tCKE
issued). The
differential
should self
remain
stable
and
already
or closed.
If a single-bank PRECHARGE specifications
at least
1 x tCK clock
after entering
refresh
mode.
All
SELF open
REFRESH
COMMAND
t
t
t
meet
CKE
specifications
at
least
1
x
CK
after
entering
command
is
issued,
RP
timing
applies.
command
and
address
input
signals
except
CKE
are
“Don’t
Care”
The SELF REFRESH command can be used to retain data in
self refresh.
self refresh
mode. All command and address input signals
the DDR2 SDRAM, even if the rest of the system is powered during
down.
When
in
the
self
refresh
mode,
the
DDR2
SDRAM
except
CKE
are “Don’t Care” during self refresh.
SELF REFRESH COMMAND
retains data without external clocking. All power supply inputs The procedure for exiting self refresh requires a sequence of
The procedure
for exiting
selfclock
refresh
requires
a sequence
commands.
First, the
differential
must
be stable
and meet
of
commands.
First,
the
differential
clock
must
be stable
tCK specifications at least 1 x tCK prior to CKE going back
HIGH.
t
andCKE
meet
CK specifications
at been
least satisfied
1 x tCK with
priorfour
to CKE
Once
is HIGH
(tCLE(MIN) has
clock
going backthe
HIGH.
CKE
is have
HIGHNOP
(tCLE(MIN)
has
registrations),
DDR2Once
SDRAM
must
or DESELECT
commands
issued with
for tXSNR
because
time is required
for the
been satisfied
four clock
registrations),
the DDR2
completion
anyhave
internal
refresh
in progress.
A simple algorithm
SDRAM of
must
NOP
or DESELECT
commands
issued
forfor
meeting
refreshtime
and is
DLL
requirements
to apply NOP
t
XSNRboth
because
required
for theiscompletion
of
DESELECT commands for 200 clock cycles before applying
cycles must then occur before a READ command can be or any
internal refresh in progress. A simple algorithm for
The SELF REFRESH command is initiated like a any other command.
The
SELFVREF
REFRESH
can
belevels
usedupon
to retain
(including
) must be command
maintained at
valid
entry/
data
in the
DDR2
SDRAM,
evenoperation.
if the rest of the system
exit and
during
SELF
REFRESH
is powered down. When in the self refresh mode, the
DDR2
SDRAM
retains data
without external
clocking.
The SELF
REFRESH
command
is initiated
likeAlla
REFRESH
command
except CKE
LOW.
The DLL is
power
supply
inputs (including
VREF) ismust
be maintained
automatically
disabled
upon and
entering
refresh
and is
at
valid levels upon
entry/exit
duringself
SELF
REFRESH
automatically
enabled
upon
exiting
self
refresh
(200
clock
operation.
REFRESH command except CKE is LOW. The DLL is
automatically disabled upon entering self refresh and is
automatically enabled upon exiting self refresh (200 clock
cycles must then occur before a READ command can be
AS4DDR232M72PBG
Rev. 0.0
07/06
AS4DDR232M72APBG
Rev. 1.1 12/12
meeting both refresh and DLL requirements is to apply
NOP or DESELECT commands for 200 clock cycles before
applying any other command.
Note: Self refresh not available at military temperature.
Note: Self refresh not available at military temperature..
20
20
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iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
DC OPERATING CONDITIONS
All Voltages referenced to Vss
Symbol
MIN
Parameter
TYP
MAX
Units
Notes
Supply Voltage
VCC
1.7
1.8
1.9
V
1
I/O Supply Voltage
VCCQ
1.7
1.8
1.9
V
4
I/O Reference Voltage
VREF
0.49 x VCCQ
0.50 x VCCQ
0.51 x VCCQ
V
2
I/O Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
3
Notes:
1. VCC VCCQ must track each other. VCCQ must be less than or equal to VCC.
exceed ± 1 percent of the DC value.
2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not
Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF. This measurement is to be taken at the
nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track
variations in the DC level of VREF.
4. VCCQ tracks with VCC track with VCC.
ABSOLUTE MAXIMUM RATINGS
Min
Max
Unit
VCC
Voltage on VCC pin relative to VSS
Parameter
-1.0
2.3
V
VCCQ
Voltage on VCCQ pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
TSTG
Storage Temperature
-55.0
125.0
C
TCASE
Device Operating Temperature
Symbol
VIN, VOUT
II
Input Leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
-55.0
125.0
C
CMD/ADR, RAS\, CAS\
WE\' CS\. CKE
-10.0
10.0
uA
CK, CK\
-10.0
10.0
uA
DM
-5
5
uA
-10
10
uA
-10
10
uA
IQZ
IVREF
INPUT / OUTPUT CAPACITANCE
TA = 25oC, f = 1 MHz, VCC = VCCQ = 1.8V
Parameter
Input capacitance (A0-A12, BA0-BA1)
Symbol
CADDR
Max
28
Input capacitance (CS#, RAS#, CAS#, WE#, CKE, ODT)
CIN1
10
pF
Input capacitance CK, CK#
CIN2
8
pF
Input capacitance DM, DQS, DQS#
CIN3
10
pF
Input capacitance DQ0-71
COUT
12
pF
AS4DDR232M72APBG
Rev. 1.1 12/12
21
Unit
pF
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2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
INPUT DC LOGIC LEVEL
All voltages referenced to Vss
Parameter
Input High (Logic 1) Voltage
Symbol
VIH (DC)
Input Low (Logic 0) Voltage
VIL (DC)
Min
Max
VREF + 0.125 VCCQ + 0.300
VREF - 0.125
-0.300
Unit
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to Vss
Parameter
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
Symbol
VIH (AC)
Min
VREF + 0.250
Max
---
Unit
V
AC Input High (Logic 1) Voltage DDR2-667
VIH (AC)
VREF + 0.200
ACInput Low (Logic 0) Voltage DDR2-400 & DDR2-533
---
--VREF - 0.250
V
VIL (AC)
AC Input Low (Logic 1) Voltage DDR2-667
VIL (AC)
---
VREF - 0.200
V
AS4DDR232M72APBG
Rev. 1.1 12/12
22
V
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2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
DDRII ICC SPECIFICATIONS AND CONDITIONS
Parameter
Operating Current: One bank active-precharge
tCL=tCK(ICC), tRC=tRC(ICC), tRAS=tRAS MIN(ICC); CKE is
HIGH, CS\ is HIGH between valid commands; Address bus
switching, Data bus switching
Operating Current: One bank active-READ-precharge
current
IOUT=0ma; BL=4, CL=CL(ICC), AL=0; tCK = tCK(ICC), tRCtRC(ICC), tRAS=tRAS MIN(ICC), tRCD=tRCD(ICC); CKE is
HIGH, CS\ is HIGH between valid commands; Address bus is
switching; Data bus is switching
Precharge POWER-DOWN current
All banks idle; tCK-tCK(ICC); CKE is LOW; Other control and
address bus inputs are stable; Data bus inputs are floating
Symbol
-3
-38
-5
Units
ICC0
600
550
500
mA
ICC1
750
650
600
mA
ICC2P
30
30
30
mA
ICC2Q
275
225
175
mA
ICC2N
300
250
200
mA
175
150
125
40
40
40
ICC3N
325
275
225
mA
ICC4W
850
700
600
mA
ICC4R
850
700
600
mA
ICC5
725
675
625
mA
ICC6
30
30
30
mA
ICC7
1200
1200
1200
mA
Precharge quiet STANDBY current
All banks idle; tCK=tCK(ICC); CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge STANDBY current
All banks idle; tCK-=tCK(ICC); CKE is HIGH, CS\ is HIGH;
Other control and address bus inputs are switching; Data bus
inputs are switching
Active POWER-DOWN current
All banks open; tCK=tCK(ICC); CKE is LOW;
Other control and address inputs are stable; Data
bus inputs are floating
MRS[12]=0
ICC3P
mA
MRS[12]=1
Active STANDBY current
All banks open; tCK=tCK(ICC), tRAS MAX(ICC),
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are
switching; Data bus inputs are switching
Operating Burst WRITE current
All banks open, continuous burst writes; BL=4, CL=CL(ICC),
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid
commands; Address bus inputs are switching; Data bus
inputs are switching
Operating Burst READ current
All banks open, continuous burst READS, Iout=0mA; BL=4,
CL=CL(ICC), AL=0; tCL=tCK(ICC), tRAS=tRAS MAX(ICC),
tRP=tRP(ICC); CKE is HIGH, CS\ is HIGH betwwn valid
commands; Address and Data bus inputs switching
Burst REFRESH current
tCK=tCK(ICC); refresh command at every tRFC(ICC) interval;
CKE is HIGH, CS\ is HIGH betwwn valid commands; Other
control, Address and Data bus inputs are switching
Self REFRESH current
CK and CK\ at 0V; CKE</=0.2V; Other control, address and
data inputs are floating
Operating bank Interleave READ current:
All bank interleaving READS, IOUT = 0mA; BL=4,
CL=CL(ICC), AL=tRCD(ICC)-1xtCK(ICC); tCK=tCK(ICC),
tRC=tRC(ICC), tRRD=tRRD(ICC); CKE is HIGH, CS\ is HIGH
between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
AS4DDR232M72APBG
Rev. 1.1 12/12
23
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
AC OPERATING SPECIFICATIONS
Parameter
Clock
Clock Cycle Time
Clock Jitter
DATA
Symbol
tCKAVG
CL=4
tCKAVG
CL=3
Clock High Time
Clock Low Time
Half Clock Period
Clock Jitter - Period
DATA Strobe
CL=5
Min of
Clock Jitter - Half Period
Clock Jitter - Cycle to Cycle
-3
333MHz/667Mbps
MIN
MAX
3
8
3.75
8
-38
266MHz/567Mbps
MIN
MAX
-5
200MHz/400Mbps
MIN
MAX
Units
ns
3.75
8
5
8
ns
tCKAVG
5
8
5
8
5
8
ns
tCHAVG
0.48
0.52
0.48
0.52
0.48
0.52
tCK
tCLAVG
tHP
tJITPER
0.48
0.52
0.48
0.52
0.48
0.52
tCH,tCL
-125
125
-125
125
-125
125
tCK
ps
ps
tJIT DUTY
-125
125
-125
125
-150
150
ps
tJITCC
tCH,tCL
250
tCH,tCL
250
ps
250
tERR2PER
-175
175
-175
175
-175
175
ps
Cumulative Jitter error, 4 Cycles
tERR4PER
-250
250
-250
250
-250
250
ps
Cumulative Jitter error, 6-10 Cycles
tERR10PER
-350
350
-350
350
-350
350
ps
Cumulative Jitter error, 11-50 Cycles
DQ hold skew factor
DQ output access time from CK/CK\
Data-out High-Z window from CK/CK\
DQS Low-Z window from CL/CK\
tERR50PER
tQHS
tAC
tHZ
tLZ1
-450
-450
450
340
450
-450
-500
450
400
500
-450
-600
450
450
600
tAC(MIN)
tAC(MAX)
tAC(MIN)
tAC(MAX)
tAC(MIN)
tAC(MAX)
ps
ps
ps
ps
ps
tAC(MAX)
2*tAC(MIN)
tAC(MAX)
2*tAC(MIN)
tAC(MAX)
Cumulative Jitter error, 2 Cycles
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ2
2*tAC(MIN)
DQ and DM input setup time relative to DQS
tDSJEDEC
100
100
150
ps
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data Hold skew factor
DQ-DQS Hold, DQS to first DQ to go non valid, per access
Data valid output window (DVW)
DQS input-high pulse width
DQS input-low pulse width
DQS output access time from CK/CK\
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising-hold time
DQS-DQ skew, DQS to last DQ valid, per group, per access
DQS READ preamble
DQS READ postamble
WRITE preamble setup time
DQS WRITE preamble
DQS WRITE postamble
Positive DQS latching edge to associated Clock edge
WRITE command to first DQS latching transition
tDSJEDEC
tDIPW
tQHS
tQH
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tDQSQ
tRPRE
tRPST
tWPRES
tWPRE
tWPST
tDQSS
175
0.35
225
0.35
275
0.35
ps
tCK
ps
ps
ps
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
tCK
tCK
DQ Low-Z window from CK/CK\
AS4DDR232M72APBG
Rev. 1.1 12/12
340
400
tHP-tQHS
tHP-tQHS
tHP-tQHS
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
0.35
0.35
-400
0.2
0.2
0.9
0.4
0
0.35
0.4
-0.25
400
240
1.1
0.6
0.6
0.25
0.35
0.35
-400
0.2
0.2
0.9
0.4
0
0.25
0.4
-0.25
400
300
1.1
0.6
0.6
0.25
0.35
0.35
-450
0.2
0.2
0.9
0.4
0
0.25
0.4
-0.25
450
450
350
1.1
0.6
0.6
0.25
WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS WL-tDQSS WL+tDQSS
24
ps
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2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
AC OPERATING SPECIFICATIONS (CONTINUED)
AC Operating Specifications (cont'd)
PWRDN
ODT
S. REFRESH
REFRESH
COMMAND and ADDRESS
Parameter
Address and Control input puslse width for each input
Address and Control input setup time
Address and Control input hold time
CAS\ to CAS\ command delay
ACTIVE to ACTIVE command (same bank)
ACTIVE bank a to ACTIVE bank b Command
ACTIVE to READ or WRITE delay
4‐Bank activate period
ACTIVE to PRECHARGE
Internal READ to PRECHARGE command delay
WRITE recovery time
Auto PRECHARGE WRITE recovery+PRECHARGE time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE, command Cycle time
CKE LOW to CK, CK\ uncertainty
REFRESH to ACTIVE or REFRESH to REFRESH
command Interval
Average periodic REFRESH interval [Industrial temp]
Average periodic REFRESH interval [Enhanced temp]
Average periodic REFRESH interval [Military temp]
Exit SELF REFRESH to non READ command
Exit SELF REFRESH to READ command
Exit SELF REFRESH timing reference
Symbol
tIPW
tISJEDEC
tIHJEDEC
tCCD
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
tDAL
tWTR
tRP
tRPA
tMRD
tDELAY
tRFC
-3
-38
-5
333MHz/667Mbps 266MHz/567Mbps 200MHz/400Mbps
MIN
MAX
MIN
MAX
MIN
MAX
0.6
200
275
2
55
10
15
50
40
7.5
15
70000
0.6
250
375
2
55
10
15
50
10
7.5
15
70000
0.6
350
475
2
55
10
15
50
40
7.5
15
70000
tWR + tRP
tWR + tRP
tWR + tRP
7.5
15
7.5
15
10
15
tRP+tCL
tRP+tCL
tRP+tCL
2
2
2
tIS + tCL + tIH
tIS + tCL + tIH
tIS + tCL + tIH
105
tREFIIT
tREFIET
tREFIXT
70000
105
7.8
TBD
TBD
70000
105
7.8
3.9
TBD
Units
tCK
ps
ps
ps
ps
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
70000
ns
7.8
3.9
3.9
us
us
us
tXSNR
tRFC(min)+
10
tRFC(min)+
10
tRFC(min)+
10
ns
tXSRD
200
200
200
tCK
tISXR
tIS
tIS
tIS
ps
ODT turn‐on delay
tAOND
2
2
2
2
2
2
ODT turn‐on delay
tAOND
tAC(min)
tAC(max)+
700
tAC(min)
tAC(max)+
1000
tAC(min)
tAC(max)+
1000
ps
ODT turn‐off delay
tAOPD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn‐off delay
tAOF
tAC(max)+
600
2 x tCK +
tAC(max)+
1000
2.5 x tCK +
tAC(max)+
1000
ps
ODT turn‐on (power‐down mode)
tAONPD
ODT turn‐off (power‐down mode)
tAQFPD
ODT to power‐down entry latency
ODT power‐down exit latency
ODT enable from MRS command
Exit active POWER‐DOWN to READ command, MR[12]=0
Exit active POWER‐DOWN to READ command, MR[12]=1
Exit PRECHARGE POWER‐DOWN to any non READ
CKE Min. HIGH/LOW time
tANPD
tAXPD
tMOD
tXARD
tSARDS
tXP
tCLE
AS4DDR232M72APBG
Rev. 1.1 12/12
tAC(max)+
tAC(min)
600
2 x tCK +
tAC(min) +
tAC(min) +
tAC(max)+
2000
2000
1000
2.5 x tCK +
tAC(min) +
tAC(min) +
tAC(max)+
2000
2000
1000
tAC(min)
tAC(max)+
tAC(min)
600
2 x tCK +
tAC(min) +
tAC(max)+
2000
1000
2.5 x tCK +
tAC(min) +
tAC(max)+
2000
1000
3
8
12
2
3
8
12
2
3
8
12
2
7 - AL
6 - AL
6 - AL
2
3
2
3
2
3
25
tCK
ps
ps
tCK
tCK
ns
tCK
tCK
tCK
tCK
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
MECHANICAL DIAGRAM
1
2
3
4
5
6 7
8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
19.05
NOM
24.90
25.10
H
G
F
E
D
1.27
NOM
C
B
A
(Bottom View)
255 x 0.762 NOM
1.27 NOM
31.90
32.10
0.61 NOM
2.03 MAX
AS4DDR232M72APBG
Rev. 1.1 12/12
26
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
ORDERING INFORMATION
Part Number
AS4DDR232M72APBG-3/IT
AS4DDR232M72APBG-38/IT
AS4DDR232M72APBG-5/IT
AS4DDR232M72APBG-3/ET
AS4DDR232M72APBG-38/ET
AS4DDR232M72APBG-5/ET
AS4DDR232M72APBG-3/XT
AS4DDR232M72APBG-38/XT
AS4DDR232M72APBG-5/XT
AS4DDR232M72APBGR-3/IT
AS4DDR232M72APBGR-38/IT
AS4DDR232M72APBGR-5/IT
AS4DDR232M72APBGR-3/ET
AS4DDR232M72APBGR-38/ET
AS4DDR232M72APBGR-5/ET
AS4DDR232M72APBGR-3/XT
AS4DDR232M72APBGR-38/XT
AS4DDR232M72APBGR-5/XT
Core Freqency
333MHz
266MHz
200MHZ
333MHz
266MHz
200MHZ
333MHz
266MHz
200MHZ
333MHz
266MHz
200MHZ
333MHz
266MHz
200MHZ
333MHz
266MHz
200MHZ
Data Rate
667Mbps
533Mbps
400Mbps
667Mbps
533Mbps
400Mbps
667Mbps
533Mbps
400Mbps
667Mbps
533Mbps
400Mbps
667Mbps
533Mbps
400Mbps
667Mbps
533Mbps
400Mbps
Device Grade
Industrial
Industrial
Industrial
Enhanced
Enhanced
Enhanced
Military
Military
Military
Industrial ‐ RoHS
Industrial ‐ RoHS
Industrial ‐ RoHS
Enhanced ‐ RoHS
Enhanced ‐ RoHS
Enhanced ‐ RoHS
Military ‐ RoHS
Military ‐ RoHS
Military ‐ RoHS
Availability
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
Production
IT = Industrial = Full production, Industrial class integrated component, fully operable across -40C to +85C
ET = Enhanced = Full production, Enhanced class integrated component, fully operable across -40C to +105C
XT = Military = Full production, Mil-Temperature class integrated component, fully operable across -55C to +125C
* Contact Micross Sales Rep for IBIS Models
* Contact Micross Sales Rep for Thermal Models
AS4DDR232M72APBG
Rev. 1.1 12/12
27
Micross Components reserves the right to change products or specifications without notice.
iPEM
2.4 Gb SDRAM-DDR2
AS4DDR232M72APBG
DOCUMENT TITLE
2.4Gb, 32M x 72, DDR2 SDRAM, 25mm x 32mm - 255 PBGA Multi-Chip Package [iPEM]
REVISION HISTORY
Rev #
HistoryRelease Date
Status
0.0Initial ReleaseJuly 2010Preliminary
1.0
Updated status to “Release”
February 2011
Release
1.1
Updated availability to “Production”
December 2012
Release
AS4DDR232M72APBG
Rev. 1.1 12/12
28
Micross Components reserves the right to change products or specifications without notice.
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