Fairchild HCPL062NR2 3.3v dual channel high speed-10 mbit/s logic gate optocoupler Datasheet

HCPL062N
3.3V Dual Channel High Speed-10 MBit/s Logic Gate
Optocouplers
Features
Description
■ Compact SO8 package
The HCPL062N optocouplers consist of an AlGaAs LED,
optically coupled to a very high speed integrated photodetector logic gate consisting of bipolar transistors on a
CMOS process for reduced power consumption. The
output features an open collector, thereby permitting
wired OR outputs. The devices are housed in a compact
small-outline package. The coupled parameters are
guaranteed over the temperature range of -40°C to
+85°C. An internal noise shield and provides superior
common mode rejection.
■ Very high speed – 10MBit/s
■ Superior CMR – 25kV/µs minimum (1,000 volts
■
■
■
■
common mode)
Logic gate output
Wired OR-open collector
Fixed threshold detector design minimizes thermal
impact on switching times
U.L. recognized (File # E90700)
tm
Applications
■ Ground loop elimination
■ Field buses
■ Line receiver, data transmission
■ Data multiplexing
■ Switching power supplies
■ Pulse transformer replacement
■ Computer-peripheral interface
■ Instrumentation input/output isolation
Package Dimensions
SEATING PLANE
0.164 (4.16)
0.144 (3.66)
Pin 1
0.202 (5.13)
0.182 (4.63)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
0.143 (3.63)
0.123 (3.13)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.244 (6.19)
0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
0.050 (1.27)
TYP
Note:
All dimensions are in inches (millimeters)
©2006 Fairchild Semiconductor Corporation
HCPL062N Rev. 1.0.0
1
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
July 2006
8 VCC
+ 1
V
F1
_ 2
_
V
7 V01
6 V02
3
F2
5 GND
+ 4
Note:
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected no further than 3mm
from the VCC and GND pins of each device.
Truth Table (Positive Logic)
Input
Output
H
L
L
H
A 0.1µF bypass capacitor must be connected between pins 8 and 5.
2
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Circuit Drawing(1)
Symbol
Parameter
Value
Units
TSTG
Storage Temperature
-40 to +125
°C
TOPR
Operating Temperature
-40 to +85
°C
EMITTER
IF
DC/Average Forward Input Current (each channel)
50
mA
VR
Reverse Input Voltage (each channel)
5.0
V
PI
Power Dissipation
45
mW
7.0
V
Output Current (each channel)
15
mA
VO
Output Voltage (each channel)
7.0
V
PO
Collector Output Power Dissipation
85
mW
Min.
Max.
Units
Input Current, Low Level
0
250
µA
IFH
Input Current, High Level
6.3(2)
15
mA
VCC
Supply Voltage, Output
2.7
3.3
V
TA
Operating Temperature
-40
+85
°C
N
Fan Out (TTL load)
–
5
TTL Loads
RL
Output Pull-up
330
4K
Ω
DETECTOR
VCC
Supply Voltage
(1 minute max)
IO
Recommended Operating Conditions
Symbol
IFL
Parameter
Note:
2. 6.3mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value
is 5.0mA or less
3
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings (No derating required up to 85°C)
Individual Component Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.(3)
Max.
Unit
–
–
1.8
V
EMITTER
VF
Input Forward Voltage
IF = 10mA
–
–
1.75
BVR
Input Reverse Breakdown
Voltage
IR = 10µA
5.0
–
–
V
∆VF/∆TA
Input Diode Temperature
Coefficient
IF = 10mA
–
-1.5
–
mV/°C
TA =25°C
DETECTOR
ICCH
High Level Supply Current
IF = 0mA, VCC = 3.3V
–
7.1
10
mA
ICCL
Low Level Supply Current
IF = 10mA, VCC = 3.3V
–
6.7
15
mA
Switching Characteristics (TA = -40°C to +85°C, VCC = 3.3V, IF = 7.5 mA Unless otherwise specified.)
Symbol
AC Characteristics
Test Conditions
Min.
Typ.(3)
Max.
Unit
TPLH
Propagation Delay
Time to Output High
Level
RL = 350Ω, CL = 15pF
Note 4, Fig. 10
–
–
90
ns
TPHL
Propagation Delay
Time to Output Low
Level
RL = 350Ω, CL = 15pF
Note 5, Fig. 10
–
–
75
ns
RL = 350Ω, CL = 15pF
Fig. 10
–
–
25
ns
|TPHL–TPLH| Pulse Width Distortion
tr
Output Rise Time
(10–90%)
RL = 350Ω, CL = 15pF)
Note 6, Fig. 10
–
16
–
ns
tf
Output Fall Time
(90–10%)
RL = 350Ω, CL = 15pF
Note 7, Fig. 10
–
4
–
ns
|CMH|
Common Mode
Transient Immunity
(at Output High Level)
RL = 350Ω, TA = 25°C, IF = 0 mA,
VCC = 3.3V, VO(Min.) = 2V
|VCM| = 1,000V
Notes 8, 11, Fig. 11
25,000
–
–
V/µs
|CML|
Common Mode
Transient Immunity
(at Output Low Level)
RL = 350Ω, TA =25°C, IF = 7.5mA,
VCC = 3.3V, VO(Max.) = 0.8V
|VCM| = 1,000V
Notes 9, 11, Fig. 11
25,000
–
–
V/µs
4
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Electrical Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
Symbol
DC Characteristics
Test Conditions
Min.
Typ.(3)
Max.
Unit
VOL
Low Level Output Voltage
VCC = 3.3V, IF = 5mA, IOL = 13mA
–
–
0.6
V
IFT
Input Threshold Current
VCC = 3.3V, VO = 0.6V, IOL = 13mA
–
–
5
mA
Isolation Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
Test Conditions
Min.
Typ.(3)
Max.
Unit
Input-Output
Insulation Leakage Current
Relative humidity = 45%
TA = 25°C, t = 5 sec.
VI-O = 3000 VDC, Note 10
–
–
1.0
µA
VISO
Withstand Insulation Test
Voltage
RH < 50%, TA = 25°C
II-O ≤ 2µA, t = 1 min.,
Note 10
2500
–
–
VRMS
RI-O
Resistance (Input to Output)
VI-O = 500V, Note 10
–
1012
–
Ω
CI-O
Capacitance (Input to Output)
f = 1MHz, Note 10
–
0.6
–
pF
Symbol
II-O
Characteristics
Notes:
3. All typical values are at VCC = 3.3V, TA = 25°C unless otherwise specified.
4. tPLH – Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current
pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
5. tPHL – Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current
pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
6. tr – Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
7. tf – Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
8. CMH – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high
state (i.e., VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
9. CML – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low
output state (i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
10. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
11. The power supply bypass capacitors must be no further than 3mm from the leads of the optocoupler. A low
inductance ground plane width of with ≤ 5nHy of series lead inductance is required.
5
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Transfer Characteristics (TA = -40°C to +85°C Unless otherwise specified.)
Fig. 2 High Level Output Current vs.
Ambient Temperature
Fig. 1 Forward Current vs. Forward Voltage
12
IOH – HIGH LEVEL OUTPUT CURRENT (nA)
IF – FORWARD CURRENT (mA)
100
10
TA = 100oC
1
TA = 85oC
TA = -40oC
0.1
TA = 0oC
TA = 25oC
0.01
VO = VCC = 3.3V
IF = 250µA
10
8
6
4
2
0
0.001
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
-40
1.7
-20
VF – FORWARD VOLTAGE (V)
60
80
100
2.5
V
CC
VCC = 3.3V
VO = 0.6V
RL = 350Ω, 1kΩ, 4kΩ
= 3.3V
ITH - INPUT THRESHOLD CURRENT (mA)
IOL - LOW LEVEL OUTPUT CURRENT (mA)
40
Fig. 4 Input Threshold Current vs. Temperature
40
VOL = 0.6V
IF = 5mA
30
25
20
15
10
-40
20
TA – AMBIENT TEMPERATURE (°C)
Fig. 3 Low Level Output Current vs. Ambient Temperature
35
0
2.0
1.5
1.0
0.5
0.0
-20
0
20
40
60
80
-40
100
6
HCPL062N Rev. 1.0.0
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (°C)
TA – AMBIENT TEMPERATURE (°C)
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Typical Performance Curves
Fig. 5 Pulse Width Distortion vs. Ambient Temperature
Fig. 6 Propagation Delay vs. Pulse Input Current
120
VCC = 3.3V
VCC = 3.3V
RL = 350Ω
IF = 7.5mA
RL = 350Ω
25
tP – PROPAGATION DELAY (ns)
PWD – PULSE WIDTH DISTORTION (ns)
30
20
15
10
5
TA = 25oC
100
80
tPLH
60
tPHL
40
20
0
0
-40
-20
0
20
40
60
80
100
5
7
TA – AMBIENT TEMPERATURE (˚C)
Fig. 7 Propagation Delay vs. Ambient Temperature
11
13
15
Fig. 8 Rise and Fall Times vs. Ambient Temperature
100
30
VCC = 3.3V
VCC = 3.3V
IF = 7.5mA
90
IF = 7.5mA
RL = 350Ω
RL = 350Ω
25
tr, tf – RISE, FALL TIMES (ns)
tP – PROPAGATION DELAY (ns)
9
IF – PULSE INPUT CURRENT (mA)
80
70
tPLH
60
50
tPHL
40
20
tr
15
10
5
30
tf
0
20
-40
-20
0
20
40
60
80
100
-40
TA – AMBIENT TEMPERATURE (˚C)
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (˚C)
7
HCPL062N Rev. 1.0.0
-20
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Typical Performance Curves (Continued)
Fig. 9 Low Level Output Voltage vs. Ambient Temperature
VOL – LOW LEVEL OUTPUT VOLTAGE (V)
0.6
VCC = 3.3V
0.5
IO = 13mA
IF = 5mA
0.4
0.3
0.2
0.1
0.0
-40
-20
0
20
40
60
80
100
TA – AMBIENT TEMPERATURE (˚C)
8
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
Fig. 10 Test Circuit and Waveforms for tPLH, tPHL, tr and tf
≤3mm spacing
Pulse Gen.
ZO = 50 Ω
tf = tr = 5 ns
Dual Channel
1
VCC 8
RL
2
7
3
6
4
5
0.1µF
Bypass
RM
t PHL
Output VO
Monitoring
Node
t PLH
Output
(VO )
CL*
GND
I F = 3.75 mA
Input
(I F)
+3.3V
IF
Input
Monitoring
Node
I F = 7.5 mA
1.5 V
90%
Output
(VO )
10%
tf
tr
Fig. 11 Test Circuit and Waveforms for Common Mode Transient Immunity
≤3mm spacing
IF
Dual Channel
B
A
+3.3V
VCC 8
1
RL
2
7
3
6
VFF
GND
4
0.1µF
Bypass
Output VO
Monitoring
Node
5
VCM
+
–
Pulse
Generator
ZO = 50 Ω
VCM
0V
Peak
3.3V
CM H
Switching Pos. (A), IF = 0
VO
VO (Min)
VO (Max)
VO
0.5 V
Switching Pos. (B), IF = 7.5 mA
CM L
9
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Test Circuits
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Footprint
8-Pin Small Outline
0.024 (0.61)
0.060 (1.52)
0.275 (6.99)
0.155 (3.94)
0.050 (1.27)
10
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Ordering Information
Option
No Suffix
Order Entry Identifier
Description
HCPL062N
Shipped in tubes (50 units per tube)
R1
HCPL062NR1
Tape and Reel (500 units per reel)
R2
HCPL062NR2
Tape and Reel (2500 units per reel)
Marking Information
1
62N
X YY S
3
2
5
4
Definitions
1
Fairchild logo
2
Device number
3
One digit year code, e.g., ‘3’
4
Two digit work week ranging from ‘01’ to ‘53’
5
Assembly package code
11
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
8.0 ± 0.10
3.50 ± 0.20
2.0 ± 0.05
Ø1.5 MIN
4.0 ± 0.10
0.30 MAX
1.75 ± 0.10
5.5 ± 0.05
12.0 ± 0.3
8.3 ± 0.10
5.20 ± 0.20
Ø1.5 ± 0.1/-0
6.40 ± 0.20
0.1 MAX
User Direction of Feed
Reflow Profile
300
260°C
280
260
>245°C = 42 Sec
240
220
200
180
°C
Time above
183°C = 90 Sec
160
140
120
1.822°C/Sec Ramp up rate
100
80
60
40
33 Sec
20
0
0
60
120
180
270
360
Time (s)
12
HCPL062N Rev. 1.0.0
www.fairchildsemi.com
HCPL062N 3.3V Dual Channel High Speed-10 MBit/s Logic Gate Optocouplers
Carrier Tape Specification
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
®
ACEx
Across the board. Around the world.™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
CTL™
Current Transfer Logic™
DOME™
2
E CMOS™
®
EcoSPARK
EnSigna™
FACT Quiet Series™
®
FACT
®
FAST
FASTr™
FPS™
®
FRFET
GlobalOptoisolator™
GTO™
HiSeC™
i-Lo™
ImpliedDisconnect™
IntelliMAX™
ISOPLANAR™
MICROCOUPLER™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
®
OPTOLOGIC
®
OPTOPLANAR
PACMAN™
POP™
®
Power220
®
Power247
PowerEdge™
PowerSaver™
®
PowerTrench
Programmable Active Droop™
®
QFET
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
ScalarPump™
SMART START™
®
SPM
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TCM™
®
The Power Franchise
®
TinyLogic
TINYOPTO™
TinyPower™
TinyWire™
TruTranslation™
μSerDes™
®
UHC
UniFET™
VCX™
Wire™
™
TinyBoost™
TinyBuck™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Definition
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
© 2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com