® ® ADS-CCD1201 12-Bit, 1.2MHz, Sampling A/D’s Optimized for CCD Applications IN N O VA T IO N a n d E X C E L L E N C E FEATURES • • • • • • • • • Unipolar input range (0 to +10V) 1.2MHz sampling rate 4096-to-1 dynamic range (72.2dB) Low noise, 400µVrms (1/6 of an LSB) Outstanding differential nonlinearity error (±0.35 LSB max.) Small, 24-pin ceramic DDIP Low power, 1.7 Watts Operates from ±12V or ±15V supplies Edge-triggered, no pipeline delay INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION The functionally complete, easy-to-use ADS-CCD1201 is a 12-bit, 1.2MHz Sampling A/D Converter whose performance and production testing have been optimized for use in electronic imaging applications, particularly those employing charge coupled devices (CCD’s) as their photodetectors. The ADS-CCD1201 delivers the lowest noise (400µVrms) and the best differential nonlinearity error (±0.35LSB max.) of any commercially available 12-bit A/D in its speed class. It can respond to full scale input steps (from empty to full well) with less than a single count of error, and its input is immune to overvoltages that may occur due to blooming. Packaged in an industry-standard, 24-pin, ceramic DDIP, the ADS-CCD1201 requires ±15V (or ±12V) and +5V supplies and typically consumes 1.7 (1.4) Watts. The device is 100% production tested for all critical performance parameters and is fully specified over both the 0 to +70°C and –55 to +125°C operating temperature ranges. For those applications using correlated double sampling, the ADS-CCD1201 can be supplied without its internal sample- PIN FUNCTION PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 (MSB) 24 23 22 21 20 19 18 17 16 15 14 13 –12V/–15V SUPPLY GROUND +12V/+15V SUPPLY +10V REFERENCE OUT ANALOG INPUT GROUND NO CONNECT NO CONNECT START CONVERT EOC GROUND +5V SUPPLY hold amplifier. DATEL will also entertain discussions about including the CDS circuit internal to the ADS-CCD1201. Please contact us for more details. – ANALOG INPUT 20 S/H DAC + S1 S2 12 BIT 1 (MSB) 11 BIT 2 +10V REFERENCE 21 10 BIT 3 REF REGISTER DIGITAL CORRECTION LOGIC FLASH ADC BUFFER REGISTER START CONVERT 16 9 BIT 4 8 BIT 5 7 BIT 6 6 BIT 7 5 BIT 8 4 BIT 9 3 BIT 10 2 BIT 11 1 BIT 12 (LSB) TIMING AND CONTROL LOGIC EOC 15 13 +5V SUPPLY 17, 18 NO CONNECT 22 +12V/+15V SUPPLY 14, 19, 23 GROUND 24 –12V/–15V SUPPLY Figure 1. ADS-CCD1201 Functional Block Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.) • Tel: (508) 339-3000 Fax: (508)339-6356 • For immediate assistance: (800) 233-2765 ® ® ADS-CCD1201 ABSOLUTE MAXIMUM RATINGS PARAMETERS +12V/+15V Supply (Pin 22) –12V/–15V Supply (Pin 24) +5V Supply (Pin 13) Digital Input (Pin 16) Analog Input (Pin 20) Lead Temp. (10 seconds) PHYSICAL/ENVIRONMENTAL LIMITS UNITS 0 to +16 0 to –16 0 to +6 –0.3 to +VDD +0.3 –4 to +17 +300 Volts Volts Volts Volts Volts °C PARAMETERS MIN. TYP. MAX. UNITS 0 –55 — — +70 +125 °C °C Operating Temp. Range, Case ADS-CCD1201MC ADS-CCD1201MM Thermal Impedance θjc θca Storage Temperature Range Package Type Weight — 5 — °C/Watt — 24 — °C/Watt –65 – +150 °C 24-pin, metal-sealed ceramic DDIP 0.42 ounces (12 grams) FUNCTIONAL SPECIFICATIONS (TA = +25°C, ±Vcc = ±15V (or ±12V), +VDD = +5V, 1.2MHz sampling rate, and a minimum 1 minute warmup➀ unless otherwise specified.) +25°C ANALOG INPUT Input Voltage Range ➁ Input Resistance Input Capacitance 0 to +70°C –55 to +125° C MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS — — — 0 to +10 1 7 — — 15 — — — 0 to +10 1 7 — — 15 — — — 0 to +10 1 7 — — 15 Volts kΩ pF +2.0 — — — — — — — — 100 — +0.8 +20 –20 — +2.0 — — — — — — — — 100 — +0.8 +20 –20 — +2.0 — — — — — — — — 100 — +0.8 +20 –20 — Volts Volts µA µA ns — — — — — — 12 12 ±0.5 +0.25 +0.1 ±0.05 ±0.1 — — — ±0.35 ±0.3 ±0.15 ±0.3 — — — — — — — 12 12 ±0.5 ±0.25 ±0.2 ±0.1 ±0.2 — — — ±0.35 ±0.5 ±0.15 ±0.5 — — — — — — — 12 12 ±1 ±0.35 ±0.3 ±0.15 ±0.3 — — — ±0.75 ±0.5 ±0.4 ±0.5 — Bits LSB LSB %FSR %FSR % Bits — — –86 –84 –80 –78 — — –86 –84 –80 –78 — — –82 –81 –76 –75 dB dB — — –84 –82 –79 –77 — — –84 –82 –79 –77 — — –77 –76 –71 –70 dB dB 72 71 73 72 — — 72 71 73 72 — — 70 70 72 72 — — dB dB 71 71 73 72 — — 71 71 73 72 — — 68 68 71 71 — — dB dB — — –85 400 — — — — –84 500 — — — — –83 700 — — dB µVrms — — 7.5 6 — — — — 7.5 6 — — — — 7.5 6 — — MHz MHz — — — — 84 ±60 ±20 5 — — — — — — — — 84 ±60 ±20 5 — — — — — — — — 84 ±60 ±20 5 — — — — dB V/µs ns ps rms 360 — 1.2 400 400 — 440 833 — 360 — 1.2 400 400 — 440 833 — 360 — 1.2 400 400 — 440 833 — ns ns MHz DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Start Convert Positive Pulse Width ➂ STATIC PERFORMANCE Resolution Integral Nonlinearity (fin = 10kHz) Differential Nonlinearity (fin = 10kHz) Full Scale Absolute Accuracy Offset Error (Tech Note 2) Gain Error (Tech Note 2) No Missing Codes (fin = 10kHz) DYNAMIC PERFORMANCE Peak Harmonics (–0.5dB) dc to 100kHz 100kHz to 500kHz Total Harmonic Distortion (–0.5dB) dc to 100kHz 100kHz to 500kHz Signal-to-Noise Ratio (w/o distortion, –0.5dB) dc to 100kHz 100kHz to 500kHz Signal-to-Noise Ratio ➃ (8 distortion, –0.5dB) dc to 100kHz 100kHz to 500kHz Two-tone Intermodulation Distortion (fin = 100kHz, 240kHz fs = 1.2MHz, –0.5dB) Noise Input Bandwidth (–3dB) Small Signal (–20dB input) Large Signal(–0.5dB input) Feedthrough Rejection (fin = 500kHz) Slew Rate Aperture Delay Time Aperture Uncertainty S/H Acquisition Time ( to ±0.01%FSR, 10V step) Overvoltage Recovery Time ➄ A/D Conversion Rate 2. ® ® ADS-CCD1201 +25°C 0 to +70°C –55 to +125°C ANALOG OUTPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS Internal Reference Voltage Drift External Current +9.95 — — +10.0 ±5 — +10.05 — 1.5 +9.95 — — +10.0 ±5 — +10.05 — 1.5 +9.95 — — +10.0 ±5 — +10.05 — 1.5 Volts ppm/ºC mA +2.4 — — — — — — — — +0.4 –4 +4 +2.4 — — — — — — — — +0.4 –4 +4 +2.4 — — — — — — — — +0.4 –4 +4 Volts Volts mA mA — — 35 — — Straight Binary 35 — — 35 ns +14.5 –14.5 +4.75 +15.0 –15.0 +5.0 +15.5 –15.5 +5.25 +14.5 –14.5 +4.75 +15.0 –15.0 +5.0 +15.5 –15.5 +5.25 +14.5 –14.5 +4.75 +15.0 –15.0 +5.0 +15.5 –15.5 +5.25 Volts Volts Volts — — — — — +50 –40 +70 1.7 — +65 –50 +85 1.9 ±0.01 — — — — — +50 –40 +70 1.7 — +65 –50 +85 1.9 ±0.01 — — — — — +50 –40 +70 1.7 — +65 –50 +85 1.9 ±0.01 mA mA mA Watts %FSR/%V +11.5 –11.5 +4.75 +12.0 –12.0 +5.0 +12.5 –12.5 +5.25 +11.5 –11.5 +4.75 +12.0 –12.0 +5.0 +12.5 –12.5 +5.25 +11.5 –11.5 +4.75 +12.0 –12.0 +5.0 +12.5 –12.5 +5.25 Volts Volts Volts — — — — — +50 –40 +70 1.4 — +65 –48 +80 1.6 ±0.01 — — — — — +50 –40 +70 1.4 — +65 –48 +80 1.6 ±0.01 — — — — — +50 –40 +70 1.4 — +65 –48 +80 1.6 ±0.01 mA mA mA Watts %FSR/%V DIGITAL OUTPUTS Logic Levels Logic "1" Logic "0" Logic Loading “1" Logic Loading "0" Delay, Falling Edge of EOC to Output Data Valid Output Coding POWER REQUIREMENTS, ±15V Power Supply Range +15V Supply –15V Supply +5V Supply Power Supply Current +15V Supply –15V Supply +5V Supply Power Dissipation Power Supply Rejection POWER REQUIREMENTS, ±12V Power Supply Range +12V Supply –12V Supply +5V Supply Power Supply Current +12V Supply –12V Supply +5V Supply Power Dissipation Power Supply Rejection Footnotes: ➀ All power supplies must be on before applying a start convert pulse. All supplies and the clock (START CONVERT) must be present during warmup periods. The device must be continuously converting during this time. There is a slight degradation in performance when using ±12V supplies. ➁ Contact DATEL for availability of other input voltage ranges. ➂ A 100ns wide start convert pulse is used for all production testing. ➃ Effective bits is equal to: (SNR + Distortion) – 1.76 + 20 log Full Scale Amplitude Actual Input Amplitude 6.02 ➄ This is the time required before the A/D output data is valid after the analog input is back within the specified range. TECHNICAL NOTES 3. When operating the ADS-CCD1201 from ±12V supplies, do not drive external circuitry with the REFERENCE OUTPUT (pin 21). The reference’s accuracy and drift specifications may not be met, and loading the circuit may cause accuracy errors within the converter. 1. Obtaining fully specified performance from the ADS-CCD1201 requires careful attention to pc-card layout and power supply decoupling. The device’s analog and digital ground systems are connected to each other internally. For optimal performance, tie all ground pins (14, 19, and 23) directly to a large analog ground plane beneath the package. 4. A passive bandpass filter is used at the input of the A/D for all production testing. Bypass all power supplies, as well as the REFERENCE OUTPUT (pin 21), to ground with 4.7µF tantalum capacitors in parallel with 0.1µF ceramic capacitors. Locate the bypass capacitors as close to the unit as possible. If the user-installed offset and gain adjusting circuit shown in Figure 2 is used, also locate it as close to the ADS-CCD1201 as possible. 5. Applying a start pulse while a conversion is in progress (EOC = logic "1") initiates a new and inaccurate conversion cycle. Data for the interrupted and subsequent conversions will be invalid. Table 1. Zero and Gain Adjust 2. ADS-CCD1201 achieves its specified accuracies without external calibration. If required, the device’s small initial offset and gain errors can be reduced to zero using the input circuit of Figure 2. When using this circuit, or any similar offset and gaincalibration hardware, make adjustments following warmup. To avoid interaction, always adjust offset before gain. 3. Input Voltage Range Zero Adjust +1/2 LSB Gain Adjust +FS – 1 1/2 LSB 0 to +10V +1.2207mV +9.99634V ® ® ADS-CCD1201 For the ADS-CCD1201, offset adjusting is normally accomplished at the point where all output bits are 0’s and the LSB just changes from a 0 to a 1. This digital output transition ideally occurs when the applied analog input is +1/2LSB (+1.2207mV). CALIBRATION PROCEDURE (Refer to Figures 2 and 3) Any offset and/or gain calibration procedures should not be implemented until devices are fully warmed up. To avoid interaction, offset must be adjusted before gain. The ranges of adjustment for the circuit of Figure 2 are guaranteed to compensate for the ADS-CCD1201’s initial accuracy errors and may not be able to compensate for additional system errors. Gain adjusting is accomplished when all bits are 1’s and the LSB just changes from a 1 to a 0. This transition ideally occurs when the analog input is at +full scale minus 1 1/2 LSB’s (+9.99634V). +15V Offset Adjust Procedure 200k Ω 20k Ω ZERO/ OFFSET ADJUST 2k Ω 1. Apply a train of pulses to the START CONVERT input (pin 16) so the converter is continuously converting. If using LED’s on the outputs, a 200kHz conversion rate will reduce flicker. GAIN ADJUST –15V +15V 1.98k Ω SIGNAL INPUT 2. Apply +1.2207mV to the ANALOG INPUT (pin 20). To Pin 20 of ADS-CCD1201 50 Ω 3. Adjust the offset potentiometer until the output bits are 0000 0000 00000 and the LSB flickers between 0 and 1. Gain Adjust Procedure –15V Figure 2. ADS-CCD1201 Calibration Circuit 1. Apply +9.99634V to the ANALOG INPUT (pin 20). 2. Adjust the gain potentiometer until all output bits are 1’s and the LSB flickers between 1 and 0. All fixed resistors in Figure 2 should be metal-film types, and multi-turn potentiometers should have TCR’s of 100ppm/°C or less to minimize drift with temperature. In many applications, the CCD will require an offset-adjust (black balance) circuit near its output and also a gain stage, presumably with adjust capabilities, to match the output voltage of the CCD to the input range of the AID. If one is performing a "system I/O calibration" (from light in to digital out), these circuits can be used to compensate for the relatively small initial offset and gain errors of the A/D. This would eliminate the need for the circuit shown in Figure 2. Table 2. ADS-CCD1201 Output Coding Input Voltage (0 to +10V) Unipolar Scale Digital Output MSB LSB +9.9976 +7.5000 +5.0000 +2.5000 +0.0024 0 +FS – 1LSB +3/4 FS +1/2 FS +1/4 FS +1LSB 0 1111 1111 1111 1100 0000 0000 1000 0000 0000 0100 0000 0000 0000 0000 0001 0000 0000 0000 Coding is straight binary; 1LSB = 2.44mV +5V 4.7µF 13 + 0.1µF 14 24 –12V/–15V 4.7µF + 4.7µF +12V/+15V + 0.1µF 19, 23 ADS-CCD1201 0.1µF 22 0 to +10V ANALOG 20 INPUT THERMAL REQUIREMENTS 12 BIT 1 (MSB) 11 BIT 2 10 BIT 3 9 BIT 4 8 BIT 5 7 BIT 6 6 BIT 7 5 BIT 8 4 BIT 9 3 BIT 10 2 BIT 11 1 BIT 12 (LSB) All DATEL sampling A/D converters are fully characterized and specified over operating temperature (case) ranges of 0 to +70°C and – 55 to +125°C. All room-temperature (TA = +25°C) production testing is performed without the use of heat sinks or forced-air cooling. Thermal impedance figures for each device are listed in their respective specification tables. These devices do not normally require heat sinks, however, standard precautionary design and layout procedures should be used to ensure devices do not overheat. The ground and power planes beneath the package, as well as all pcb signal runs to and from the device, should be as heavy as possible to help conduct heat away from the package. Electricallyinsulating, thermally-conductive "pads" may be installed underneath the package. Devices should be soldered to boards rather than "socketed," and of course, minimal air flow over the surface can greatly help reduce the package temperature. 21 +10V REF. OUT 0.1µF + 4.7µF 17, 18 15 EOC NO CONNECT Figure 3. Typical ADS-CCD1201 Connection Diagram In more severe ambient conditions, the package/junction temperature of a given device can be reduced dramatically (typically 35%) by using one of DATEL’s HS Series heat sinks. See Ordering Information for the assigned part number. See page 1-183 of the DATEL Data Acquisition Components Catalog for more information on the HS Series. Request DATEL Application Note AN-8, "Heat Sinks for DIP Data Converters,"or contact DATEL directly, for additional information. A/D converters are calibrated by positioning their digital outputs exactly on the transition point between two adjacent digital output codes. This can be accomplished by connecting LED’s to the digital outputs and adjusting until certain LED’s "flicker" equally between on and off. Other approaches employ digital comparators or microcontrollers to detect when the outputs change from one code to the next. 4. ® ® ADS-CCD1201 START CONVERT N N+1 100ns typ. 100ns typ. 10ns typ. 10ns typ. Acquisition Time 433ns typ. INTERNAL S/H 400ns typ. Hold 60ns min.,70ns typ., 80ns max. 90ns typ. 420ns Conversion Time EOC 35ns max. 73ns max. OUTPUT DATA DATA (N-1) VALID DATA N VALID 760ns min. INVALID DATA Note: Scale is approximately 25ns per division. Figure 4. ADS-CCD1201 Timing Diagram TIMING not employ "pipeline" delays to increase its throughput rate. It does not require multiple start convert pulses to bring valid digital data to its output pins. The ADSCCD-1201 is an edge triggered device. A conversion is initiated by the rising edge of the start convert pulse and no additional external timing signals are required. The device does C2 15pF COG +15V OFFSET ADJ 20K R5 2K .1% R3 200K 5% R2 12 11 U4 13 C1 0.1MF +15V +5V 74LS86 74LS240 -15V + C4 2.2MF P4 7 2 + 11 4 13 C21 0.1MF C6 2.2MF R7 7 C20 0.1MF C7 0.1MF C5 0.1MF R8 10K 2 13 14 U6 OP-77 0.1% 3 15 + 4 16 P1 5 8 7 + +15V C11 2.2MF 9 12 11 14 13 16 15 C9 2.2MF 20 21 B3 DGND B4 EOC B5 ST. CONV B6 B2 B7 U1 B1 C13 0.1MF 19 12 1Y2 1A3 1Y3 1A4 1Y4 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 2G 1G AGND B9 INPUT B10 +10VREF B11 B12 B13 B14 9 U3 8 74LS240 7 2 6 4 5 6 4 8 3 11 2 13 1 15 17 19 5 2 C24 Y1 1 SEE NOTE 1 14 XTAL 7 8 74LS86 1 J2 SG1 U4 14 J1 START CONVERT U4 16 B2 14 B3 12 B4 9 B5 7 B6 5 B7 SG3 32 33 30 31 28 MSB 29 26 27 24 25 22 23 20 21 3 19 1 P2 C17 0.1MF 20 1A1 1Y1 1A2 1Y2 1A3 1Y3 1A4 1Y4 2A1 2Y1 2A2 2Y2 2A3 2Y3 2A4 2Y4 2G 1G 18 B8 18 17 16 B9 16 15 14 B10 14 13 12 B11 12 11 9 B12 10 7 B13 8 9 7 5 B14 6 LSB 5 3 4 EOC 3 1 2 ST.CONV. 1 34 ENABLE 4 P3 24 23 B1 10 C15 0.1MF 22 21 18 10 +5V 20 19 26 1A2 +5V 18 17 25 1Y1 10 B8 SG2 20 1A1 11 C14 2.2MF -15V +15V +5V 22 +15V 23 AGND 24 -15V C12 0.1MF + 10 19 C10 0.1MF -15V 18 ADS-CCD1201/1202 + 6 17 C23 0.1MF C22 2.2 -15V MF 1 3 + +5V 2 4 15 17 – 6 C8 2.2MF -15V 10K 0.1% C19 2.2MF 8 +5V AD845 + J5 +15V 6 U5 3 R6 2K 0.1% 6 – 0.1% GAIN ADJ 4 + ANALOG INPUT R4 1.98K 50 2 C3 0.1MF + R1 C16 0.1MF U2 3 6 J3 9 10 74LS86 U4 8 J4 74LS86 7 + 2.2MF NOTES: C18 0.1MF 1. FOR ADS-BCCD1201 Y1 IS 1.2MHZ FOR ADS-BCCD1201 Y1 IS 2MHZ +5V 5. Figure 5. ADS-CCD1201 Evaluation Board Schematic ® ® ADS-CCD1201 0 –10 –20 Amplitude Relative to Full Scale (dB) –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 0 60 120 180 240 300 360 420 480 540 600 Frequency (kHz) Figure 6. ADS-CCD1201 FFT (fin = 480kHz, fs = 1.2MHz, Vin = –0.5dB, 16,384 points) SNR vs. Input Frequency Peak Harmonics vs. Input Frequency 90 80 80 70 70 Peak Harmonic (–dB) 90 SNR (dB) 60 50 40 30 60 50 40 30 20 20 10 10 0 0 1 10 100 1000 1 10000 10 Input Frequency (kHz) 1000 10000 1000 10000 THD vs. Input Frequency SNR+D vs. Input Frequency 90 90 80 80 70 70 60 60 THD (–dB) SNR+D (dB) 100 Input Frequency (kHz) 50 40 50 40 30 30 20 20 10 10 0 0 1 10 100 1000 1 10000 10 100 Input Frequency (kHz) Input Frequency (kHz) Figure 7. Typical ADS-CCD1201 Dynamic Performance vs. Input Frequency at +25°C (Vin = –0.5dB, fs = 1.2MHz) 6. ® ADS-CCD1201 4000 Number of Occurences 3500 3000 2500 This histogram represents the typical peak-to-peak noise (including quantization noise) associated with the ADS-CCD1201. 4,096 conversions were processed with the input to the ADS-CCD1201 tied to analog ground. 2000 1500 1000 500 0 Digital Output Code Figure 8. ADS-CCD1201 Grounded Input Histogram DNL (LSB's) +0.15 Number of Occurences ® 0 –0.19 0 0 Digital Output Code Digital Output Code 4096 4096 Figure 9. ADS-CCD1201 Histogram and Differential Nonlinearity 7. ® ® ADS-CCD1201 MECHANICAL DIMENSIONS INCHES (mm) 1.31 MAX. (33.27) 24-PIN DDIP 24 Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) 13 0.80 MAX. (20.32) 1 Lead Material: Kovar alloy Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 12 0.100 TYP. (2.540) 1.100 (27.940) 0.235 MAX. (5.969) 0.200 MAX. (5.080) +0.002 0.010 –0.001 (0.254) 0.190 MAX. (4.826) 0.100 (2.540) 0.040 (1.016) 0.018 ±0.002 (0.457) 0.600 ±0.010 (15.240) SEATING PLANE 0.025 (0.635) 0.100 (2.540) 1.31 MAX. (33.02) 24-PIN SURFACE MOUNT Dimension Tolerances (unless otherwise indicated): 2 place decimal (.XX) ±0.010 (±0.254) 3 place decimal (.XXX) ±0.005 (±0.127) 13 24 Lead Material: Kovar alloy 0.80 MAX. (20.32) 1 0.190 MAX. (4.826) Lead Finish: 50 microinches (minimum) gold plating over 100 microinches (nominal) nickel plating 12 0.020 TYP. (0.508) 0.060 TYP. (1.524) 0.130 TYP. (3.302) PIN 1 INDEX 0.100 (2.540) 0.100 TYP. (2.540) 0.020 (0.508) 0.015 (0.381) MAX. radius for any pin 0.010 TYP. (0.254) 0.040 (1.016) ORDERING INFORMATION Accessories MODEL NUMBER OPERATING TEMP. RANGE ANALOG INPUT ADS-CCD1201MC ADS-CCD1201MM 0 to +70°C –55 to +125°C Unipolar (0 to +10V) Unipolar (0 to +10V) ADS-BCCD1201 HS-24 Receptacles for pc board mounting can be ordered through Amp Inc., part number 3-331272-8 (component lead socket), 24 required. Contact DATEL for availability of surface-mount packaging or high-reliability screening. ® ® INNOVATION and EXCELLENCE Evaluation Board (without ADS-CCD1201) Heat Sink for ADS-CCD1201 models ISO 9001 R DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 / Fax: (508) 339-6356 For immediate assistance: (800) 233-2765 E G I S T E R E D DS-0274C 10/96 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH Munchen, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.