IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT IDT54/74FCT533T/AT/CT IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES Integrated Device Technology, Inc. – Reduced system switching noise FEATURES: • Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT373T/FCT533T/FCT573T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 48mA IOL) – Power off disable outputs permit “live insertion” • Features for FCT2373T/FCT2573T: – Std., A and C speed grades – Resistor output (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) DESCRIPTION: The FCT373T/FCT2373T, FCT533T and FCT573T/ FCT2573T are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high- impedance state. The FCT2373T and FCT2573T have balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall timesreducing the need for external series terminating resistors. The FCT2xxxT parts are plug-in replacements for FCTxxxT parts. FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT373T/2373T AND IDT54/74FCT573T/2573T D0 D1 D D2 D D3 D O D O G D4 D O G D5 D O G D6 D O G D7 D O G O G O G G LE OE O0 O1 O2 O3 O4 O5 O6 O7 2564 cnv* 01 FUNCTIONAL BLOCK DIAGRAM IDT54/74FCT533T D0 D1 D D2 D D3 D O D O G D4 D O G D5 D O G D6 D O G D7 D O G O G O G G LE OE O0 O1 O2 O3 MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. O4 O5 O6 O7 2564 cnv* 02 The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.12 AUGUST 1995 DSC-4216/6 1 IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS O7 18 D7 4 O1 O2 5 D2 D3 7 O3 GND 6 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 17 D6 16 O6 O1 5 15 O5 D5 O2 6 D2 D3 14 13 D4 9 12 O4 10 11 LE 8 3 2 4 D1 1 20 19 18 17 D7 D6 16 O6 7 15 O5 8 14 D5 L20-2 9 10 11 12 13 O3 GND D0 D1 2564 cnv* 03 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW D4 19 VCC O7 2 3 OE O0 VCC O4 20 LE 1 D0 INDEX OE O0 IDT54/74FCT373/2373T 2564 cnv* 04 LCC TOP VIEW 1 20 VCC D0 2 3 19 O0 18 O1 O2 D2 4 D3 5 O3 O4 D4 6 D5 D6 D4 6 D5 7 D6 8 D7 GND 16 15 13 O5 O6 9 12 O7 10 11 LE 14 O1 17 O2 16 O3 7 15 O4 8 14 O5 L20-2 9 10 11 12 13 2564 cnv* 05 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW O6 5 17 O7 D3 P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 20 19 18 1 LE 4 3 2 D7 GND D1 D2 O0 OE OE VCC D1 INDEX D0 IDT54/74FCT573/2573T 2564 cnv* 06 LCC TOP VIEW O7 18 D7 D1 4 O1 5 O2 6 D2 7 P20-1 D20-1 SO20-2 & E20-1 17 3 2 D6 D1 4 16 O6 O1 5 15 O5 O2 D2 D3 6 14 D5 D3 8 13 D4 O3 GND 9 12 O4 10 11 LE 1 20 19 18 17 D7 D6 16 O6 7 15 8 14 O5 D5 L20-2 9 10 11 12 13 2564 cnv* 07 DIP/SOIC/CERPACK TOP VIEW D4 19 VCC O7 2 3 D0 OE O0 O4 VCC LE 20 O3 GND 1 D0 INDEX OE O0 IDT54/74FCT533 2564 cnv* 08 LCC TOP VIEW 6.12 2 IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE (533)(1) Inputs LE DN FUNCTION TABLE (373 and 573)(1) Outputs OE ON DN Inputs LE OE Outputs ON H H L L H H L H L H L H L H L L X X H Z X X H Z NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2564 tbl 01 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2564 tbl 02 DEFINITION OF FUNCTIONAL TERMS Pin Names DN Description Data Inputs LE Latch Enable Input (Active HIGH) OE Output Enable Input (Active LOW) ON 3-State Outputs ON Complementary 3-State Outputs 2564 tbll 03 ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to with Respect to VCC +0.5 GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current –60 to +120 CAPACITANCE (TA = +25°C, f = 1.0MHz) Military –0.5 to +7.0 Unit V –0.5 to VCC +0.5 V –55 to +125 °C –65 to +135 °C –65 to +150 °C 0.5 W –60 to +120 mA Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Typ. 6 VOUT = 0V 8 Max. Unit 10 pF 12 NOTE: 1. This parameter is measured at characterization but not tested. pF 2564 lnk 05 2564 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 6.12 3 IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Symbol VIH Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 Typ.(2) — Max. — Unit V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V II H Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1 µA II L Input LOW Current (4) VI = 0.5V — — ±1 I OZH High Impedance Output Current I OZL (3-State Output pins) (4) II Input HIGH Current(4) VCC = Max., VI = VCC (Max.) VIK Clamp Diode Voltage VH Input Hysteresis I CC Quiescent Power Supply Current VO = 2.7V — — ±1 VO = 0.5V — — ±1 — — ±1 VCC = Min., IIN = –18mA — –0.7 –1.2 V — — 200 — mV — 0.01 1 VCC = Max. VCC = Max., VIN = GND or VCC µA µA mA 2564 lnk 06 OUTPUT DRIVE CHARACTERISTICS FOR FCT373T/533T/573T VOL Output LOW Voltage I OS Short Circuit Current Test Conditions(1) VCC = Min. I OH = –6mA MIL. VIN = VIH or V IL I OH = –8mA COM'L. I OH = –12mA MIL. I OH = –15mA COM'L. VCC = Min. I OL = 32mA MIL. VIN = VIH or V IL I OL = 48mA COM'L. VCC = Max., VO = GND (3) I OFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or V O ≤ 4.5V Symbol VOH Parameter Output HIGH Voltage Min. 2.4 Typ.(2) 3.3 Max. — Unit V 2.0 3.0 — V — 0.3 0.5 V –60 –120 –225 mA — — ±1 µA 2564 lnk 07 OUTPUT DRIVE CHARACTERISTICS FOR FCT2373T/2573T Symbol I ODL Parameter Output LOW Current Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) Min. 16 Typ.(2) 48 Max. — Unit mA I ODH Output HIGH Current VCC = 5V, VIN = VIH or V IL, VOUT = 1.5V (3) –16 –48 — mA VOH Output HIGH Voltage 2.4 3.3 — V VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or V IL — 0.3 0.50 V I OH = –12mA MIL. I OH = –15mA COM'L. I OL = 12mA NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. The test limit for this parameter is ±5µA at TA = –55°C. 5. This parameter is guaranteed but not tested. 6.12 2564 lnk 08 4 IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Total Power Supply Current (6) Test Conditions(1) VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling Min. — Typ.(2) 0.5 Max. 2.0 Unit mA mA/ MHz VIN = VCC FCTxxxT VIN = GND FCT2xxxT — 0.15 0.25 — 0.06 0.12 VIN = VCC — 1.5 3.5 VIN = GND FCT2xxxT — 0.6 2.2 FCTxxxT VIN = 3.4 VIN = GND FCT2xxxT — 1.8 4.5 0.9 3.2 VIN = VCC — 3.0 6.0 (5) VIN = GND FCT2xxxT — 1.2 3.4 (5) FCTxxxT VIN = 3.4 VIN = GND FCT2xxxT — 5.0 14.0 (5) — 3.2 11.4 (5) FCTxxxT FCTxxxT NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz. 6.12 mA 2564 tbl 09 5 IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT373T/2373T/573T/2573T Com'l. Symbol Parameter Conditions(1) Min.(2) CL = 50pF 1.5 FCT373AT/2373AT/573AT/2573AT Mil. Max. Min.(2) 8.0 1.5 Com'l. Max. Min.(2) 8.5 1.5 Mil. Max. Min.(2) Max. Unit 5.2 1.5 5.6 ns tPLH tPHL Propagation Delay DN to ON tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay LE to ON Output Enable Time 2.0 13.0 2.0 15.0 2.0 8.5 2.0 9.8 ns 1.5 12.0 1.5 13.5 1.5 6.5 1.5 7.5 ns Output Disable Time 1.5 7.5 1.5 10.0 1.5 5.5 1.5 6.5 ns Set-up Time HIGH or LOW, DN to LE Hold Time HIGH or LOW, DN to LE LE Pulse Width HIGH 2.0 — 2.0 — 2.0 — 2.0 — ns 1.5 — 1.5 — 1.5 — 1.5 — ns 6.0 — 6.0 — 5.0 — 6.0 — tH tW RL = 500Ω ns 2564 tbl 10 FCT373CT/2373CT/573CT/2573CT Com'l. Symbol Parameter FCT373DT/573DT Mil. Com'l. Mil. Conditions(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit CL = 50pF 1.5 4.2 1.5 5.1 1.5 3.8 — — ns tPLH tPHL Propagation Delay DN to ON tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay LE to ON Output Enable Time 2.0 5.5 2.0 8.0 2.0 4.0 — — ns 1.5 5.5 1.5 6.3 1.5 4.8 — — ns Output Disable Time 1.5 5.0 1.5 5.9 1.5 4.0 — — ns Set-up Time HIGH or LOW, DN to LE Hold Time HIGH or LOW, DN to LE LE Pulse Width HIGH (3) 2.0 — 2.0 — 1.5 — — — ns 1.5 — 1.5 — 1.0 — — — ns 5.0 — 6.0 — 3.0 — — — tH tW RL = 500Ω ns 2564 tbl 11 FCT533T Com'l. Symbol Parameter tPLH tPHL Propagation Delay DN to ON tPLH tPHL tPZH tPZL tPHZ tPLZ tSU Propagation Delay LE to ON Output Enable Time Output Disable Time Set-up Time HIGH or LOW, DN to LE Hold Time HIGH or LOW, DN to LE LE Pulse Width HIGH tH tW FCT533AT Mil. Com'l. FCT533CT Mil. Com'l. Mil. Conditions (1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit CL = 50pF 1.5 10.0 1.5 12.0 1.5 5.2 1.5 5.6 1.5 4.2 1.5 5.1 ns 2.0 13.0 2.0 14.0 2.0 8.5 2.0 9.8 2.0 5.5 2.0 8.0 ns 1.5 11.0 1.5 12.5 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns 1.5 7.0 1.5 8.5 1.5 5.5 1.5 6.5 1.5 5.0 1.5 5.9 ns 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — 2.0 — ns 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 6.0 — 6.0 — 5.0 — 6.0 — 5.0 — 6.0 — ns RL = 500Ω NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 2564 tbl 12 6.12 6 IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC 7.0V 500Ω Pulse Generator Open Drain Disable Low Closed Open All Other Tests D.U.T. 50pF RT Switch Enable Low V OUT VIN Test 2564 lnk 13 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2564 drw 09 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2564 drw 11 2564 drw 10 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V VOH 1.5V VOL DISABLE 3V 1.5V CONTROL INPUT tPZL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH 2564 drw 12 SWITCH OPEN 0V tPLZ 3.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2564 drw 13 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6.12 7 IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT, IDT54/74FCT533T/AT/CT, IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XX FCT Temp. Range X Family XXXX Device Type X Package X Process Blank B Commercial MIL-STD-883, Class B P D SO L E PY Q Plastic DIP CERDIP Small Outline IC Leadless Chip Carrier CERPACK Shrink Small Outline Package Quarter-size Small Outline Package 373T 573T 533T 373AT 573AT 533AT 373CT 573CT 533CT 373DT 573DT Non-Inverting Octal Transparent Latch Non-Inverting Octal Transparent Latch Inverting Octal Transparent Latch Blank 2 High Drive Balanced Drive 54 74 –55°C to +125°C 0°C to +70°C 2564 drw 14 6.12 8