LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 LM3205 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers Check for Samples: LM3205 FEATURES APPLICATIONS • • • • • • 1 2 • • • • • • • • 2 MHz (typ.) PWM Switching Frequency Operates from a single Li-Ion cell (2.7V to 5.5V) Variable Output Voltage (0.8V to 3.6V) Fast Output Voltage Transient (0.8V to 3.6V in 20µs) 650mA Maximum load capability High Efficiency (96% Typ at 4.2VIN, 3.4VOUT at 400mA) from internal synchronous rectification Current Overload Protection Thermal Overload Protection Packages 8-Pin microSMD (Lead Free) 10-Pin LLP Cellular Phones Hand-Held Radios RF PC Cards Battery Powered RF Devices DESCRIPTION The LM3205 is a DC-DC converter optimized for powering RF power amplifiers (PAs) from a single Lithium-Ion cell, however they may be used in many other applications. It steps down an input voltage from 2.7V to 5.5V to a variable output voltage from 0.8V(typ.) to 3.6V(typ.). Output voltage is set using a VCON analog input for controlling power levels and efficiency of the RF PA. The LM3205 offers superior performance for mobile phones and similar RF PA applications. Fixed-frequency PWM operation minimizes RF interference. Shutdown function turns the device off and reduces battery consumption to 0.01 µA (typ.). The LM3205 is available in micro SMD package and LLP package. For all other package options contact your local NSC sales office. A high switching frequency (2 MHz) allows use of tiny surface-mount components. Only three small external surface-mount components, an inductor and two ceramic capacitors are required. TYPICAL APPLICATION VIN 2.7V to 5.5V VOUT PVIN VDD 0.8V to 3.6V SW EN 10 PF 3.3 PH LM3205 VOUT = 2.5 x VCON FB 4.7 PF VCON 1 2 PGND SGND Figure 1. LM3205 Typical Application Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2009, Texas Instruments Incorporated LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com CONNECTION DIAGRAMS SW SW A2 A2 PIN 1 IDENTIFIER A3 PGND PGND A3 A1 PVIN VDD B1 B3 SGND SGND B3 B1 VDD 32 C1 EN FB C3 C3 FB EN C1 XTS PVIN A1 C2 C2 VCON VCON Top View Bottom View Package Mark õ Top View Figure 2. 8–Bump Thin Micro SMD Package, Large Bump NS Package Number TLA08GNA 10 SW SW 10 1 PGND PGND 2 9 PVin PVin 9 2 PGND SGND 3 8 PVin PVin 8 3 SGND VCON 4 7 VDD VDD 7 4 VCON FB 5 6 EN EN 6 5 FB LM3205 LM3205 Top View XXXXX 1 YYYYY PGND Package Marking Top View Bottom View Figure 3. 10–Pin LLP NS Package Number SDA10A Table 1. PIN DESCRIPTIONS Pin # Name Description microSMD LLP A1 8, 9 PVIN Power Supply Voltage Input to the internal PFET switch. B1 7 VDD Analog Supply Input. C1 6 EN Enable Input. Set this digital input high for normal operation. For shutdown, set low. C2 4 VCON C3 5 FB B3 3 SGND Analog and Control Ground A3 1, 2 PGND Power Ground A2 10 SW Voltage Control Analog input. VCON controls VOUT in PWM mode. Feedback Analog Input. Connect to the output at the output filter capacitor. Switch node connection to the internal PFET switch and NFET synchronous rectifier. Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit specification of the LM3205. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 ABSOLUTE MAXIMUM RATINGS (1) (2) VDD, PVIN to SGND −0.2V to +6.0V PGND to SGND −0.2V to +0.2V EN, FB, VCON (SGND −0.2V) to (VDD +0.2V) w/6.0V max SW (PGND −0.2V) to (PVIN +0.2V) w/6.0V max PVIN to VDD −0.2V to +0.2V Continuous Power Dissipation (3) Internally Limited Junction Temperature (TJ-MAX) +150°C Storage Temperature Range −65°C to +150°C Maximum Lead Temperature (Soldering, 10 sec) +260°C (4) (5) ESD Rating Human Body Model: Machine Model: (1) (2) (3) (4) (5) 2 kV 200V Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pins. The LM3205 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V. Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 130°C (typ.). The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7) The machine model is a 200pF capacitor discharged directly into each pin. National Semiconductor recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper ESD handling techniques can result in damage. OPERATING RATINGS (1) (2) Input Voltage Range 2.7V to 5.5V Recommended Load Current 0mA to 650mA Junction Temperature (TJ) Range −30°C to +125°C Ambient Temperature (TA) Range (3) −30°C to +85°C (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. All voltages are with respect to the potential at the GND pins. The LM3205 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be de-rated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). THERMAL PROPERTIES Junction-to-Ambient Thermal microSMD 100°C/W Resistance (θJA), microSMD TLA08 Package (1) Junction-to-Ambient Thermal LLP 55°C/W Resistance (θJA), LLP SDA10A Package (1) (1) microSMD:Junction-to-ambient thermal resistance (θJA) is taken from thermal measurements, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. A 4 layer, 4" x 4", 2/1/1/2 oz. Cu board as per JEDEC standards is used for the measurements. LLP: The value of (θJA) in LLP-10 could fall in a range of 50°C/W to 150°C/W (if not wider), depending on PWB material, layout, and environmental conditions. In applications where high maximum power dissipation exits (high VIN , high IOUT ), special care must be paid to thermal dissipation areas. For more information on these topics for LLP, refer to Application Note 1187:Leadless Leadframe Package (LLP) and the Power Efficiency and Power Dissipation section of this datasheet Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 3 LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com ELECTRICAL CHARACTERISTICS (1) (2) (3) Limits in standard typeface are for TA = TJ = 25°C. Limits in boldface type apply over the full operating ambient temperature range (−30°C ≤ TA = TJ ≤ +85°C). Unless otherwise noted, all specifications apply to LM3205TL/LM3205SD with: PVIN = VDD = EN = 3.6V. Min Typ Max Units VFB, MIN Symbol Feedback Voltage at minimum setting VCON = 0.32V (3) 0.75 0.8 0.85 V VFB, MAX Feedback Voltage at maximum setting VCON = 1.44V, VIN = 4.2V (3) 3.537 3.6 3.683 V ISHDN Shutdown supply current EN = SW = VCON = 0V, 0.01 2 µA IQ DC bias current into VDD VCON = 2V, FB = 0V, No Switching (5) 1 1.4 mA RDSON(P) micro SMD Pin-pin resistance for PFET ISW = 200mA 140 200 230 mΩ RDSON(N) micro SMD Pin-pin resistance for NFET ISW = -200mA 300 415 485 mΩ RDSON(P)LLP Pin-pin resistance for PFET ISW = 200mA 170 230 260 mΩ RDSON(N)LLP Pin-pin resistance for NFET ISW = -200mA 330 445 515 mΩ ILIM,PFET Switch peak current limit 935 1100 1200 mA FOSC Internal oscillator frequency 1.7 2 2.3 MHz VIH,EN Logic high input threshold 1.2 VIL,EN Logic low input threshold IPIN,EN Pin pull down current ZCON VCON input resistance Gain VCON to VOUT Gain (1) (2) (3) (4) (5) (6) 4 Parameter Conditions (4) (6) V 0.5 5 100 0.32V ≤ VCON ≤ 1.44V 10 V µA kΩ 2.5 V/V All voltages are with respect to the potential at the GND pins. The LM3205 is designed for mobile phone applications where turn-on after power-up is controlled by the system controller and where requirements for a small package size overrule increased die size for internal Under Voltage Lock-Out (UVLO) circuitry. Thus, it should be kept in shutdown by holding the EN pin low until the input voltage exceeds 2.7V. Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Due to the pulsed nature of the testing TA = TJ for the electrical characteristics table. The parameters in the electrical characteristics table are tested under open loop conditions at PVIN = VDD = 3.6V. For performance over the input voltage range and closed loop results refer to the datasheet curves. Shutdown current includes leakage current of PFET. IQ specified here is when the part is operating at 100% duty cycle. Current limit is built-in, fixed, and not adjustable. Refer to datasheet curves for closed loop data and its variation with regards to supply voltage and temperature. Electrical Characteristic table reflects open loop data (FB = 0V and current drawn from SW pin ramped up until cycle by cycle limit is activated). Closed loop current limit is the peak inductor current measured in the application circuit by increasing output current until output voltage drops by 10%. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 SYSTEM CHARACTERISTICS The following spec table entries are guaranteed by design providing the component values in the typical application circuit are used. These parameters are not guaranteed by production testing. Min and Max limits apply over the full operating ambient temperature range (−30°C ≤ TA ≤ 85°C) and over the VIN range = 2.7V to 5.5V, TA = 25°C, PVIN = VDD = EN = 3.6V, L = 3.3µH, DCR of L ≤ 100mΩ, CIN = 10µF, 0603, 6.3V (4.7µF||4.7µF, 0603, 6.3V can be used), COUT = 4.7µF, 0603, 6.3V for LM3205TL/LM3205SD unless otherwise noted. Symbol TRESPONSE Parameter Typ Max Units VIN = 4.2V, COUT = 4.7µF, L = 3.3µH, RLOAD = 5.5Ω 20 30 µs Time for VOUT to fall from 3.6V to VIN = 4.2V, COUT = 4.7µF, L = 3.3µH, 0.8V RLOAD = 10Ω 20 30 µs 20 pF -3 +3 % -10 10 µA 100 µs Time for VOUT to rise from 0.8V to 3.6V Conditions Min CCON VCON input capacitance VCON = 1V, Test frequency = 100 kHz Linearity Linearity in control range 0.32V to 1.44V VIN = 3.9V Monotonic in nature ICON Control pin input current TON Turn on time (time for output to reach 3.6V from Enable low to high transition) EN = Low to High, VIN = 4.2V, VO = 3.6V, COUT = 4.7µF, IOUT ≤ 1mA 70 Efficiency (L = 3.3µH, DCR ≤ 100mΩ) VIN = 3.6V, VOUT = 0.8V, IOUT = 90mA 83 % VIN = 4.2V, VOUT = 3.4V, IOUT = 400mA 96 % VOUT_ripple Ripple voltage, PWM mode VIN = 3V to 4.5V, VOUT = 0.8V, IOUT = 10mA to 400mA (1) 10 mVp-p Line_tr VIN = 600mV perturbance, TRISE = TFALL = 10µs, VOUT = 0.8V, IOUT = 100mA 50 mVpk η Line transient response Load_tr Load transient response VIN = 3.1/3.6/4.5V, VOUT = 0.8V, transients up to 100mA, TRISE = TFALL = 10µs 50 mVpk PSRR VIN = 3.6V, VOUT = 0.8V, IOUT = 100mA sine wave perturbation frequency = 10kHz, amplitude = 100mVp-p 40 dB (1) Ripple voltage should measured at COUT electrode on good layout PC board and under condition using suggested inductors and capacitors. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 5 LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (Circuit in Figure 5, PVIN = VDD = EN = 3.6V, L = 3.3uH, DCR of L ≤ 100mΩ, CIN = 10uF, 0603, 6.3V ( 4.7uF||4.7uF, 0603, 6.3V can be used), COUT = 4.7uF, 0603, 6.3V for LM3205TL/LM3205SD unless otherwise noted) Quiescent Current vs Supply Voltage (VCON = 2V, FB = 0V, No Switching) Shutdown Current vs Temperature (VCON = 0V, EN = 0V) 1.4 QUIESCENT CURRENT (mA) 1.3 TA = 85oC 1.2 TA = 25oC 1.1 1.0 TA = -30oC 0.9 0.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) Switching Frequency Variation vs Temperature (VOUT = 1.3V, IOUT = 200mA) Output Voltage vs Supply Voltage (VOUT = 1.3V) SWITCHING FREQUENCY VARIATION (%) 4.0 3.0 VIN = 5.5V 2.0 VIN = 4.2V 1.0 0.0 -1.0 VIN = 3.6V -2.0 VIN = 2.7V -3.0 -4.0 -40 -20 0 20 40 60 80 100 AMBIENT TEMPERATURE (oC) (VIN 6 Output Voltage vs Temperature = 3.6V, VOUT = 0.8V) (VIN Submit Documentation Feedback Output Voltage vs Temperature = 3.6V, VOUT = 3.4V) Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Circuit in Figure 5, PVIN = VDD = EN = 3.6V, L = 3.3uH, DCR of L ≤ 100mΩ, CIN = 10uF, 0603, 6.3V ( 4.7uF||4.7uF, 0603, 6.3V can be used), COUT = 4.7uF, 0603, 6.3V for LM3205TL/LM3205SD unless otherwise noted) Open/Closed Loop Current Limit vs Temperature (PWM mode) VCON Voltage vs Output Voltage (VIN = 4.2V, RLOAD = 8Ω) Efficiency vs Output Voltage (VIN = 3.9V) Efficiency vs Output Current (VOUT = 0.8V) Efficiency vs Output Current (VOUT = 3.4V) Load Transient Response (VOUT = 0.8V) 50 mV/DIV AC Coupled VOUT VIN = 3.6V VOUT = 0.8V IL 200 mA/DIV 250 mA IOUT 50 mA 10 Ps/DIV Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 7 LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Circuit in Figure 5, PVIN = VDD = EN = 3.6V, L = 3.3uH, DCR of L ≤ 100mΩ, CIN = 10uF, 0603, 6.3V ( 4.7uF||4.7uF, 0603, 6.3V can be used), COUT = 4.7uF, 0603, 6.3V for LM3205TL/LM3205SD unless otherwise noted) Load Transient Response (VIN = 4.2V, VOUT = 3.4V) Startup (VIN = 3.6V, VOUT = 1.3V, RLOAD = 1kΩ) 100 mV/DIV AC Coupled VOUT VIN = 4.2V VOUT = 3.4V IL 200 mA/DIV 400 mA IOUT 100 mA 10 Ps/DIV Startup (VIN = 4.2V, VOUT = 3.4V, RLOAD = 5kΩ) Shutdown Response (VIN = 4.2V, VOUT = 3.4V, RLOAD = 10Ω) VSW 5V/DIV VIN = 4.2V VOUT VOUT = 3.4V RL = 10: 2V/DIV IL 500 mA/DIV 2V/DIV EN 40 Ps/DIV Line Transient Response (VIN = 3.0V to 3.6V, IOUT = 100mA) (VIN VCON Voltage Response = 4.2V, VCON = 0.32V/1.44V, RLOAD = 10Ω) VSW 2V/DIV 3.6V VOUT VIN = 4.2V VCON = 0.32/1.44V RL = 10: 0.8V 1.44V VCON 0.32V 40 Ps/DIV VCON and Load Transient (VIN = 4.2V, VCON = 0.32V/1.44V, 15Ω/8Ω, same time) Timed Current Limit Response (VIN = 3.6V) 2V/DIV VSW 3.6V VOUT VIN = 4.2V VCON = 0.32/1.44V RL = 15:/8: 0.8V 1.44V VCON 0.32V 40 Ps/DIV 8 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Circuit in Figure 5, PVIN = VDD = EN = 3.6V, L = 3.3uH, DCR of L ≤ 100mΩ, CIN = 10uF, 0603, 6.3V ( 4.7uF||4.7uF, 0603, 6.3V can be used), COUT = 4.7uF, 0603, 6.3V for LM3205TL/LM3205SD unless otherwise noted) Output Voltage Ripple (VOUT = 1.3V) Output Voltage Ripple (VOUT = 3.4V) VSW 5V/DIV VIN = 4.2V VOUT = 3.4V IOUT = 200 mA VOUT 10 mV/DIV AC Coupled IL 100 mA/DIV 200 ns/DIV Output Voltage Ripple in Pulse Skip (VIN = 3.64V, VOUT = 3.4V, RLOAD = 5Ω) VSW RDSON vs Temperature (microSMD) (P-ch, ISW = 200mA) 2V/DIV 10 mV/DIV AC Coupled VOUT VIN = 3.64V VOUT = 3.4V RL = 5 : 500 mA/DIV IL 400 ns/DIV RDSON vs Temperature (microSMD) (N-ch, ISW = -200mA) EN High Threshold vs. Vin Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 9 LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com DEVICE INFORMATION BLOCK DIAGRAM PVIN VDD CURRENT SENSE OSCILLATOR FB ERROR AMPLIFIER ~ PWM COMP MOSFET CONTROL LOGIC VCON SW MAIN CONTROL EN SHUTDOWN CONTROL SGND PGND Figure 4. Functional Block Diagram OPERATION DESCRIPTION The LM3205 is a simple, step-down DC-DC converter optimized for powering RF power amplifiers (PAs) in mobile phones, portable communicators, and similar battery powered RF devices. It is designed to allow the RF PA to operate at maximum efficiency over a wide range of power levels from a single Li-Ion battery cell. It is based on a current-mode buck architecture, with synchronous rectification for high efficiency. It is designed for a maximum load capability of 650mA in PWM mode. Maximum load range may vary from this depending on input voltage, output voltage and the inductor chosen. Efficiency is typically around 96% for a 400mA load with 3.4V output, 4.2V input. The output voltage is dynamically programmable from 0.8V (typ.) to 3.6V (typ.) by adjusting the voltage on the control pin without the need for external feedback resistors. This ensures longer battery life by being able to change the PA supply voltage dynamically depending on its transmitting power. Additional features include current overload protection and thermal overload shutdown. The LM3205 is constructed using a chip-scale 8-pin microSMD or 10-pin LLP package. These packages offers the smallest possible size, for space-critical applications such as cell phones, where board area is an important design consideration. Use of a high switching frequency (2MHz) reduces the size of external components. As shown in Figure 1, only three external power components are required for implementation. Use of a microSMD package requires special design considerations for implementation. (See microSMD Package Assembly and use in the Applications Information section.) Its fine bump-pitch requires careful board design and precision assembly equipment. Use of this package is best suited for opaque-case applications, where its edges are not subject to high-intensity ambient red or infrared light. Also, the system controller should set EN low during power-up and other low supply voltage conditions. (See Shutdown Mode in the Device Information section.) 10 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 VIN 2.7V to 5.5V C1* 10 PF PVIN VDD VOUT L1 3.3 PH 0.8V to 3.6V SW SYSTEM DAC CONTROLLER ON/OFF VCON LM3205 FB C2 4.7 PF EN SGND PGND * Place C1 close to PVIN Figure 5. Typical Operating System Circuit CIRCUIT OPERATION Referring to Figure 1 and Figure 4, the LM3205 operates as follows. During the first part of each switching cycle, the control block in the LM3205 turns on the internal PFET (P-channel MOSFET) switch. This allows current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of around (VIN - VOUT) / L, by storing energy in a magnetic field. During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (Nchannel MOSFET) synchronous rectifier on. In response, the inductor’s magnetic field collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter capacitor and load. As the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope around VOUT / L. The output filter capacitor stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on time to control the average current sent to the load. The effect is identical to sending a duty-cycle modulated rectangular wave formed by the switch and synchronous rectifier at SW to a low-pass filter formed by the inductor and output filter capacitor. The output voltage is equal to the average voltage at the SW pin. While in operation, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing the signal from the current-sense amplifier with a slope compensated error signal from the voltage-feedback error amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and adjusts for the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the oscillator is subtracted from the error signal for stability of the current feedback loop. The minimum on time of PFET is 50ns (typ.) SHUTDOWN MODE Setting the EN digital pin low (<0.5V) places the LM3205 in a 0.01µA (typ.) Shutdown mode. During shutdown, the PFET switch, NFET synchronous rectifier, reference voltage source, control and bias circuitry of the LM3205 are turned off. Setting EN high (>1.2V) enables normal operation. EN should be set low to turn off the LM3205 during power-up and under voltage conditions when the power supply is less than the 2.7V minimum operating voltage. The LM3205 is designed for compact portable applications, such as mobile phones. In such applications, the system controller determines power supply sequencing and requirements for small package size outweigh the additional size required for inclusion of UVLO (Under Voltage Lock-Out) circuitry. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 11 LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com INTERNAL SYNCHRONOUS RECTIFICATION While in PWM mode, the LM3205 uses an internal NFET as a synchronous rectifier to reduce rectifier forward voltage drop and associated power loss. Synchronous rectification provides a significant improvement in efficiency whenever the output voltage is relatively low compared to the voltage drop across and ordinary rectifier diode. With medium and heavy loads, the internal NFET synchronous rectifier is turned on during the inductor current down slope in the second part of each cycle. The synchronous rectifier is turned off prior to the next cycle. The NFET is designed to conduct through its intrinsic body diode during transient intervals before it turns on, eliminating the need for an external diode. CURRENT LIMITING A current limit feature allows the LM3205 to protect itself and external components during overload conditions. In PWM mode, an 1200mA (max.) cycle-by-cycle current limit is normally used. If an excessive load pulls the output voltage down to approximately 0.375V, then the device switches to a timed current limit mode. In timed current limit mode the internal PFET switch is turned off after the current comparator trips and the beginning of the next cycle is inhibited for 3.5us to force the instantaneous inductor current to ramp down to a safe value. The synchronous rectifier is off in timed current limit mode. Timed current limit prevents the loss of current control seen in some products when the output voltage is pulled low in serious overload conditions. DYNAMICALLY ADJUSTABLE OUTPUT VOLTAGE The LM3205 features dynamically adjustable output voltage to eliminate the need for external feedback resistors. The output can be set from 0.8V(typ.) to 3.6V(typ.) by changing the voltage on the analog VCON pin. This feature is useful in PA applications where peak power is needed only when the handset is far away from the base station or when data is being transmitted. In other instances the transmitting power can be reduced. Hence the supply voltage to the PA can be reduced, promoting longer battery life. See Setting the Output Voltage in the Application Information section for further details. THERMAL OVERLOAD PROTECTION The LM3205 has a thermal overload protection function that operates to protect itself from short-term misuse and overload conditions. When the junction temperature exceeds around 150°C, the device inhibits operation. Both the PFET and the NFET are turned off in PWM mode. When the temperature drops below 125°C, normal operation resumes. Prolonged operation in thermal overload conditions may damage the device and is considered bad practice. APPLICATION INFORMATION SETTING THE OUTPUT VOLTAGE The LM3205 features a pin-controlled variable output voltage to eliminate the need for external feedback resistors. It can be programmed for an output voltage from 0.8V (typ.) to 3.6V (typ.) by setting the voltage on the VCON pin, as in the following formula: VOUT = 2.5 x VCON (1) When VCON is between 0.32V and 1.44V, the output voltage will follow proportionally by 2.5 times of VCON. If VCON is over 1.44V (VOUT = 3.6V), sub-harmonic oscillation may occur because of insufficient slope compensation. If VCON voltage is less than 0.32V (VOUT = 0.8V), the output voltage may not be regulated due to the required on-time being less than the minimum on-time (50ns). The output voltage can go lower than 0.8V providing a limited VIN range is used. Refer to datasheet curve (VCON Voltage vs Output Voltage) for details. This curve is for a typical part and there could be part-to-part variation for output voltages less than 0.8V over the limited VIN range. 12 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 INDUCTOR SELECTION A 3.3µH inductor with saturation current rating over 1200mA and low inductance drop at the full DC bias condition is recommended for almost all applications. The inductor’s DC resistance should be less than 0.2Ω for good efficiency. For low dropout voltage, lower DCR inductors are advantageous. The lower limit of acceptable inductance is 2.3µH at 1200mA over the operating temperature range. Full attention should be paid to this limit, because some small inductors show large inductance drops at high DC bias. These can not be used with the LM3205. Taiyo-Yuden NR3015T3R3M is an example of an inductor with the lowest acceptable limit (as of Nov./05). Table 2 suggests some inductors and suppliers. Table 2. Suggested inductors and their suppliers Model Size (WxLxH) [mm] Vendor NR3015T3R3M 3.0 x 3.0 x 1.5 Taiyo-Yuden DO3314-332MXC 3.3 x 3.3 x 1.4 Coilcraft If a smaller inductance inductor is used in the application, the LM3205 may become unstable during line and load transients and VCON transient response times may get affected. For low-cost applications, an unshielded bobbin inductor is suggested. For noise-critical applications, a toroidal or shielded-bobbin inductor should be used. A good practice is to lay out the board with footprints accommodating both types for design flexibility. This allows substitution of a low-noise toroidal inductor, in the event that noise from low-cost bobbin models is unacceptable. Saturation occurs when the magnetic flux density from current through the windings of the inductor exceeds what the inductor’s core material can support with a corresponding magnetic field. This can cause poor efficiency, regulation errors or stress to a DC-DC converter like the LM3205. CAPACITOR SELECTION The LM3205 is designed for use with ceramic capacitors for its input and output filters. Use a 10µF ceramic capacitor for input and a 4.7µF ceramic capacitor for output. They should maintain at least 50% capacitance at DC bias and temperature conditions. Ceramic capacitors types such as X5R, X7R are recommended for both filters. These provide an optimal balance between small size, cost, reliability and performance for cell phones and similar applications. Table 3 lists some suggested part numbers and suppliers. DC bias characteristics of the capacitors must be considered when selecting the voltage rating and case size of the capacitor. A few manufactures can supply 4.7µF capacitors in the 0805 case size which maintain at least 50% of their value, but TDK is currently the only manufacturer which can provide such capacitors in the 0603 case size. As of November, 2005, no manufacture can supply 10µF capacitors in the 0603 case size which maintain 50% of their value. If it is necessary to choose a 0603-size capacitor for VIN, the operation of the LM3205 should be carefully evaluated on the system board. Output capacitors with smaller case sizes mitigate piezo electric vibrations when the output voltage is stepped up and down at fast rates. However, they have a larger percentage drop in value with dc bias. Use of multiple 2.2µF or 1µF capacitors in parallel may also be considered. Table 3. Suggested capacitors and their suppliers Model Vendor 0805ZD475KA 4.7µF, 10V AVX C1608X5R0J475M, 4.7µF, 6.3V TDK C2012X5R0J106M,10µF, 6.3V TDK The input filter capacitor supplies AC current drawn by the PFET switch of the LM3205 in the first part of each cycle and reduces the voltage ripple imposed on the input power source. The output filter capacitor absorbs the AC inductor current, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR (Equivalent Series Resistance) to perform these functions. The ESR of the filter capacitors is generally a major factor in voltage ripple. EN PIN CONTROL Drive the EN pin using the system controller to turn the LM3205 ON and OFF. Use a comparator, Schmidt trigger or logic gate to drive the EN pin. Set EN high (>1.2V) for normal operation and low (<0.5V) for a 0.01µA (typ.) shutdown mode. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 13 LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com Set EN low to turn off the LM3205 during power-up and under voltage conditions when the power supply is less than the 2.7V minimum operating voltage. The part is out of regulation when the input voltage is less than 2.7V. The LM3205 is designed for mobile phones where the system controller controls operation mode for maximizing battery life and requirements for small package size outweigh the additional size required for inclusion of UVLO (Under Voltage Lock-Out) circuitry. microSMD PACKAGE ASSEMBLY AND USE Use of the microSMD package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1112. Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with microSMD package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1112 for specific instructions how to do this. The 8-Bump package used for LM3205 has 300micron solder balls and requires 10.82mil pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90°entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 7mil wide, for a section approximately 7mil long, as a thermal relief. Then each trace should neck up or down to its optimal width. The important criterion is symmetry. This ensures the solder bumps on the LM3205 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps A1, A3 and B3. Because PGND and PVIN are typically connected to large copper planes, inadequate thermal relief’s can result in late or inadequate re-flow of these bumps. The microSMD package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the microSMD package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, microSMD devices are sensitive to light, in the red and infrared range, shining on the package’s exposed die edges. LLP PACKAGE ASSEMBLY AND USE Use of the LLP package requires specialized board layout, precision mounting and careful re-flow techniques, as detailed in National Semiconductor Application Note 1187. Refer to the section Surface Mount Technology (SMT) Assembly Recommendations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device and must attach to the DAP(Die Attach Pad) of the LLP package. The pad style used with LLP package must be the NSMD (non-solder mask defined) type. This means that the soldermask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap, from holding the device off the surface of the board and interfering with mounting. See Application Note 1187 for specific instructions how to do this. BOARD LAYOUT CONSIDERATIONS VIN 2.7V to 5.5V Fosc = 2 MHz i i PVIN + C1 E - 10 PF L1 3.3 PH VOUT VDD SW EN FB C2 4.7 PF VCON PGND SGND + - C Figure 6. Current Loop 14 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 LM3205 www.ti.com SNVS388D – JULY 2005 – REVISED MAY 2009 The LM3205 converts higher input voltage to lower output voltage with high efficiency. This is achieved with an inductor-based switching topology. During the first half of the switching cycle, the internal PMOS switch turns on, the input voltage is applied to the inductor, and the current flows from PVDD line to the output capacitor (C2) through the inductor. During the second half cycle, the PMOS turns off and the internal NMOS turns on. The inductor current continues to flow via the inductor from the device PGND line to the output capacitor (C2). Referring toFigure 6 , the LM3205 has two major current loops where pulse and ripple current flow. The loop shown in the left hand side is most important, because pulse current shown inFigure 6 flows in this path. The right hand side is next. The current waveform in this path is triangular, as shown in Figure 6 . Pulse current has many high-frequency components due to fast di/dt. Triangular ripple current also has wide high-frequency components. Board layout and circuit pattern design of these two loops are the key factors for reducing noise radiation and stable operation. Other lines, such as from battery to C1(+) and C2(+) to load, are almost DC current, so it is not necessary to take so much care. Only pattern width (current capability) and DCR drop considerations are needed. 3.3 ÛH 4.7 ÛF 10 ÛF Figure 7. Evaluation Board Layout for microSMD BOARD LAYOUT FLOW (microSMD) 1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is most important. 2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second priority. 3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2(+) and C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if possible. 4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes as possible. Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 15 LM3205 SNVS388D – JULY 2005 – REVISED MAY 2009 www.ti.com 5. SGND should not connect directly to PGND. Connecting these pins under the device should be avoided. (If possible, connect SGND to the common port of C1(-), C2(-) and PGND.) 6. VDD should not be connected directly to PVIN. Connecting these pins under the device should be avoided. It is good idea to connect VDD to the C1(+) to avoid switching noise injection to the VDD line. 7. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield. 3.3uH 10uF 4.7uF Figure 8. Evaluation Board for LLP BOARD LAYOUT FLOW (LLP) 1. Minimize C1, PVIN, and PGND loop. These traces should be as wide and short as possible. This is most important. 2. Minimize L1, C2, SW and PGND loop. These traces also should be wide and short. This is the second priority. 3. Above layout patterns should be placed on the component side of the PCB to minimize parasitic inductance and resistance due to via-holes. It may be a good idea that the SW to L1 path is routed between C2(+) and C2(-) land patterns. If vias are used in these large current paths, multiple via-holes should be used if possible. 4. Connect C1(-), C2(-) and PGND with wide GND pattern. This pattern should be short, so C1(-), C2(-), and PGND should be as close as possible. Then connect to a PCB common GND pattern with as many via-holes as possible. 5. SGND should connect directly to PGND through a single common via as close to C1 as possible. Connecting these pins under the LLP device on a different layer should be avoided. 6. VDD should not be connected directly to PVIN. Connecting these pins under the device should be avoided. It is good idea to connect VDD to the C1(+) to avoid switching noise injection to the VDD line. 7. FB line should be protected from noise. It is a good idea to use an inner GND layer (if available) as a shield. NOTE The evaluation board shown inFigure 7and Figure 8 for the LM3205TL/LM3205SD were designed with these considerations, and it shows good performance. However some aspects have not been optimized because of limitations due to evaluation-specific requirements. The board can be used as a reference, but it is not the best. Please refer questions to a National representative. 16 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Links: LM3205 PACKAGE OPTION ADDENDUM www.ti.com 12-Nov-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) LM3205SD-2/NOPB ACTIVE SON DSC 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3205SDX-2/NOPB ACTIVE SON DSC 10 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM LM3205TL/NOPB ACTIVE DSBGA YZR 8 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM LM3205TLX/NOPB ACTIVE DSBGA YZR 8 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM3205SD-2/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.3 1.0 8.0 12.0 Q1 SON DSC 10 1000 178.0 12.4 LM3205SDX-2/NOPB SON DSC 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM3205TL/NOPB DSBGA YZR 8 250 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1 LM3205TLX/NOPB DSBGA YZR 8 3000 178.0 8.4 1.85 2.01 0.76 4.0 8.0 Q1 Pack Materials-Page 1 3.3 B0 (mm) PACKAGE MATERIALS INFORMATION www.ti.com 15-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3205SD-2/NOPB SON DSC 10 1000 203.0 190.0 41.0 LM3205SDX-2/NOPB SON DSC 10 4500 349.0 337.0 45.0 LM3205TL/NOPB DSBGA YZR 8 250 203.0 190.0 41.0 LM3205TLX/NOPB DSBGA YZR 8 3000 206.0 191.0 90.0 Pack Materials-Page 2 MECHANICAL DATA DSC0010A SDA10A (Rev A) www.ti.com MECHANICAL DATA YZR0008xxx D 0.600±0.075 E TLA08XXX (Rev C) D: Max = 1.882 mm, Min =1.781 mm E: Max = 1.733 mm, Min =1.632 mm 4215045/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: LM3205TLEV