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AD558–SPECIFICATIONS (@ T = +258C, V A Model AD558J Typ Min = +5 V to +15 V unless otherwise noted) AD558K Typ Max Units 8 8 8 Bits RELATIVE ACCURACY 2 0°C to +70°C –55°C to +125°C ± 1/2 ± 1/4 ± 1/2 ± 3/4 ± 1/4 ± 3/8 LSB LSB 0 to +2.56 0 to +10 Max 0 to +2.56 0 to +10 +5 0.8 2.0 Max 0 to +2.56 0 to +10 +5 Internal Passive Pull-Down to Ground 1.5 3.0 0.8 2.0 Min 0 to +2.56 0 to +10 +5 Internal Passive Pull-Down to Ground 4 OUTPUT SETTLING TIME5 0 to 2.56 Volt Range 0 to 10 Volt Range4 Min AD558T1 Typ 8 Current Source Sink Min AD558S1 Typ RESOLUTION OUTPUT Ranges3 Max CC V V mA +5 Internal Passive Pull-Down to Ground 1.5 3.0 0.8 2.0 Internal Passive Pull-Down to Ground 1.5 3.0 0.8 2.0 1.5 3.0 µs µs FULL-SCALE ACCURACY 6 @ 25°C TMIN to TMAX 61.5 62.5 60.5 61 61.5 62.5 60.5 61 LSB LSB ZERO ERROR @ 25°C TMIN to TMAX 61 62 61/2 61 61 62 61/2 61 LSB LSB 100 µA MONOTONICITY 7 TMIN to TMAX DIGITAL INPUTS TMIN to TMAX Input Current Data Inputs, Voltage Bit On-Logic “1” Bit On-Logic “0” Control Inputs, Voltage On-Logic “1” On-Logic “0” Input Capacitance TIMING8 tW, Strobe Pulse Width TMIN to TMAX tDH Data Hold Time TMIN to TMAX tDS Data Set-Up Time TMIN to TMAX POWER SUPPLY Operating Voltage Range (VCC) 2.56 Volt Range 10 Volt Range Current (ICC) Rejection Ratio Guaranteed Guaranteed ± 100 ± 100 2.0 0 0.8 2.0 0 2.0 0 0.8 2.0 0 4 POWER DISSIPATION, V CC = 5 V VCC = 15 V OPERATING TEMPERATURE RANGE 0 2.0 0 0.8 15 75 225 2.0 0 +70 0.8 15 75 225 0 +16.5 +16.5 25 0.03 2.0 0 +70 15 75 225 –55 0.8 200 270 10 10 200 270 +4.5 +11.4 125 375 V V 4 200 270 10 10 200 270 +4.5 +11.4 125 375 2.0 0 4 200 270 10 10 200 270 +16.5 +16.5 25 0.03 Guaranteed ± 100 4 200 270 10 10 200 270 +4.5 +11.4 Guaranteed +16.5 +16.5 25 0.03 +125 ns ns ns ns ns ns +4.5 +11.4 15 125 375 75 225 –55 V V pF +16.5 +16.5 25 0.03 V V mA %/% 125 375 mW mW +125 °C NOTES 1 The AD558 S & T grades are available processed and screened lo MIL-STD-883 Class B. Consult Analog Devices’ Military Databook for details. 2 Relative Accuracy is defined as the deviation of the code transition points from the ideal transfer point on a straight line from the offset to the full scale of the device. See “Measuring Offset Error”. 3 Operation of the 0 volt to 10 volt output range requires a minimum supply voltage of +11.4 volts. 4 Passive pull-down resistance is 2 kΩ for 2.56 volt range, 10 kΩ for 10 volt range. 5 Settling time is specified for a positive-going full-scale step to ± 1/2 LSB. Negative-going steps to zero are slower, but can be improved with an external pull-down. 6 The full range output voltage for the 2.56 range is 2.55 V and is guaranteed with a +5 V supply, for the 10 V range, it is 9.960 V guaranteed with a +15 V supply. 7 A monotonic converter has a maximum differential linearity error of ± 1 LSB. 8 See Figure 7. Specifications shown in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. –2– REV. B AD558 ABSOLUTE MAXIMUM RATINGS* 16 VOUT 1 (LSB) DB0 VCC to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V Digital Inputs (Pins 1–10) . . . . . . . . . . . . . . . . . . 0 V to +7.0 V VOUT . . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Ground Momentary Short to VCC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Storage Temperature Range N/P (Plastic) Packages . . . . . . . . . . . . . . . . –25°C to +100°C D (Ceramic) Package . . . . . . . . . . . . . . . . . –55°C to +150°C Lead Temperature (soldering, 10 sec) . . . . . . . . . . . . . +300°C Thermal Resistance Junction to Ambient/Junction to Case D (Ceramic) Package . . . . . . . . . . . . . . 100°C/W/30°C/W N/P (Plastic) Packages . . . . . . . . . . . . . 140°C/W/55°C/W 15 VOUT SENSE DB1 2 14 VOUT SELECT DB2 3 DB3 4 DB4 5 DB5 6 DB6 AD558 13 GND TOP VIEW 12 GND (Not to Scale) 11 +VCC 10 CS 7 9 (MSB) DB7 8 CE DB2 4 DB3 5 NC 6 AD558 METALIZATION PHOTOGRAPH DB4 Dimensions shown in inches and (mm). DB5 7 8 DB1 DB0 (LSB) NC VOUT *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VOUT SENSE Figure 1a. AD558 Pin Configuration (DIP) 3 2 1 20 19 18 VOUT SELECT 17 GND 16 NC AD558 TOP VIEW (Not to Scale) 15 GND 14 +VCC CS CE NC DB6 (MSB) DB7 9 10 11 12 13 NC = NO CONNECT Figure 1b. AD558 Pin Configuration (PLCC and LCC) Bond Pad Coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 2 13 3 14 15 16 REV. B Pad Name DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CE CS VCC GND GND VOUTSELECT VOUTSENSE VOUT X Coordinate −702 −927 −957 −957 −957 −957 −927 −702 47 272 957 957 946 923 689 −461 –3– Y Coordinate 1265 1265 1004 347 115 −111 −1248 −1248 −1248 −1248 −1225 −965 970 1265 1265 1265 AD558 CIRCUIT DESCRIPTION CHIP AVAILABILITY The AD558 consists of four major functional blocks, fabricated on a single monolithic chip (see Figure 2). The main D-to-A converter section uses eight equally-weighted laser-trimmed current sources switched into a silicon-chromium thin-film R/2R resistor ladder network to give a direct but unbuffered 0 mV to 400 mV output range. The transistors that form the DAC switches are PNPs; this allows direct positive-voltage logic interface and a zero-based output range. The AD558 is available in laser-trimmed, passivated chip form. AD558J and AD558T chips are available. Consult the factory for details. Input Logic Coding Digital Input Code DIGITAL INPUT DATA CONTROL INPUTS I2L CONTROL LOGIC BANDGAP REFERENCE DB7 DB4 DB5 DB3 DB1 DB2 DB0 CE DB6 MSB LSB CS GND GND I2L LATCHES 8-BIT VOLTAGE-SWITCHING D-TO-A CONVERTER CONTROL AMP +VCC OUTPUT AMP Output Voltage Binary Hexadecimal Decimal 2.56 V Range 10.000 V Range 0000 0000 0000 0001 0000 0010 0000 1111 0001 0000 0111 1111 1000 0000 1100 0000 1111 1111 00 01 02 0F 10 7F 80 C0 FF 0 0.010 V 0.020 V 0.150 V 0.160 V 1.270 V 1.280 V 1.920 V 2.55 V 0 1 2 15 16 127 128 192 255 0 0.039 V 0.078 V 0.586 V 0.625 V 4.961 V 5.000 V 7.500 V 9.961 V CONNECTING THE AD558 VOUT The AD558 has been configured for ease of application. All reference, output amplifier and logic connections are made internally. In addition, all calibration trims are performed at the factory assuring specified accuracy without user trims. The only connection decision that must be made by the user is a single jumper to select output voltage range. Clean circuit board layout is facilitated by isolating all digital bit inputs on one side of the package; analog outputs are on the opposite side. VOUT SENSE VOUT SELECT Figure 2. AD558 Functional Block Diagram The high speed output buffer amplifier is operated in the noninverting mode with gain determined by the user-connections at the output range select pin. The gain-setting application resistors are thin-film laser-trimmed to match and track the DAC resistors and to assure precise initial calibration of the two output ranges, 0 V to 2.56 V and 0 V to 10 V. The amplifier output stage is an NPN transistor with passive pull-down for zero-based output capability with a single power supply. The internal precision voltage reference is of the patented bandgap type. This design produces a reference voltage of 1.2 volts and thus, unlike 6.3 volt temperature compensated Zeners, may be operated from a single, low voltage logic power supply. The microprocessor interface logic consists of an 8-bit data latch and control circuitry. Low power, small geometry and high speed are advantages of the I2L design as applied to this section. I2L is bipolar process compatible so that the performance of the analog sections need not be compromised to provide on-chip logic capabilities. The control logic allows the latches to be operated from a decoded microprocessor address and write signal. If the application does not involve a µP or data bus, wiring CS and CE to ground renders the latches “transparent” for direct DAC access. Figure 3 shows the two alternative output range connections. The 0 V to 2.56 V range may be selected for use with any power supply between +4.5 V and +16.5 V. The 0 V to 10 V range requires a power supply of +11.4 V to +16.5 V. OUTPUT AMP OUTPUT AMP 16 VOUT 16 VOUT 15 VOUT SENSE 15 VOUT SENSE 14 VOUT SELECT 14 VOUT SELECT 13 GND 13 GND a. 0 V to 2.56 V Output Range b. 0 V to 10 V Output Range Figure 3. Connection Diagrams Because of its precise factory calibration, the AD558 is intended to be operated without user trims for gain and offset; therefore no provisions have been made for such user trims. If a small increase in scale is required, however, it may be accomplished by slightly altering the effective gain of the output buffer. A resistor in series with VOUT SENSE will increase the output range. MIL-STD-883 The rigors of the military/aerospace environment, temperature extremes, humidity, mechanical stress, etc., demand the utmost in electronic circuits. The AD558, with the inherent reliability of integrated circuit construction, was designed with these applications in mind. The hermetically-sealed, low profile DIP package takes up a fraction of the space required by equivalent modular designs and protects the chip from hazardous environments. To further ensure reliability, military temperature range AD558 grades S and T are available screened to MIL-STD-883. For more complete data sheet information consult the Analog Devices’ Military Databook. For example if a 0 V to 10.24 V output range is desired (40 mV = 1 LSB), a nominal resistance of 850 Ω is required. It must be remembered that, although the internal resistors all ratiomatch and track, the absolute tolerance of these resistors is typically ± 20% and the absolute TC is typically –50 ppm/°C (0 to –100 ppm/°C). That must be considered when rescaling is performed. Figure 4 shows the recommended circuitry for a full-scale output range of 10.24 volts. Internal resistance values shown are nominal. –4– REV. B Applications–AD558 The only consideration in selecting a supply voltage is that, in order to be able to use the 0 V to 10 V output range, the power supply voltage must be between +11.4 V and +16.5 V. If, however, the 0 V to 2.56 V range is to be used, power consumption will be minimized by utilizing the lowest available supply voltage (above +4.5 V). OUTPUT AMP VOUT 16 604Ω 500Ω 15 40kΩ 14 2kΩ 14kΩ 13 TIMING AND CONTROL GND The AD558 has data input latches that simplify interface to 8and 16-bit data buses. These latches are controlled by Chip Enable (CE) and Chip Select (CS) inputs. CE and CS are internally “NORed” so that the latches transmit input data to the DAC section when both CE and CS are at Logic “0”. If the application does not involve a data bus, a “00” condition allows for direct operation of the DAC. When either CE or CS go to Logic “1”, the input data is latched into the registers and held until both CE and CS return to “0”. (Unused CE or CS inputs should be tied to ground.) The truth table is given in Table I. The logic function is also shown in Figure 6. Figure 4. 10.24 V Full-Scale Connection NOTE: Decreasing the scale by putting a resistor in series with GND will not work properly due to the code-dependent currents in GND. Adjusting offset by injecting dc at GND is not recommended for the same reason. GROUNDING AND BYPASSING* All precision converter products require careful application of good grounding practices to maintain full rated performance. Because the AD558 is intended for application in microcomputer systems where digital noise is prevalent, special care must be taken to assure that its inherent precision is realized. Table I. AD558 Control Logic Truth Table The AD558 has two ground (common) pins; this minimizes ground drops and noise in the analog signal path. Figure 5 shows how the ground connections should be made. OUTPUT AMP 16 15 14 13 VOUT VOUT SENSE VOUT SELECT (SEE NEXT PAGE) RL GND CE CS DAC Data Latch Condition 0 1 0 1 0 1 X X 0 0 g g 0 0 1 X 0 0 0 0 g g X 1 0 1 0 1 0 1 Previous Data Previous Data “Transparent” “Transparent” Latching Latching Latching Latching Latched Latched NOTES X = Does not matter. g = Logic Threshold at Positive-Going Transition. GND 12 Input Data TO SYSTEM GND TO SYSTEM GND 0.1µF (SEE TEXT) TO SYSTEM VCC 11 +VCC Figure 5. Recommended Grounding and Bypassing It is often advisable to maintain separate analog and digital grounds throughout a complete system, tying them common in one place only. If the common tie-point is remote and accidental disconnection of that one common tie-point occurs due to card removal with power on, a large differential voltage between the two commons could develop. To protect devices that interface to both digital and analog parts of the system, such as the AD558, it is recommended that common ground tie-points should be provided at each such device. If only one system ground can be connected directly to the AD558, it is recommended that analog common be selected. Figure 6. AD558 Control Logic Function In a level-triggered latch such as that in the AD558 there is an interaction between data setup and hold times and the width of the enable pulse. In an effort to reduce the time required to test all possible combinations in production, the AD558 is tested with tDS = tW = 200 ns at 25°C and 270 ns at TMIN and TMAX, with tDH = 10 ns at all temperatures. Failure to comply with these specifications may result in data not being latched properly. POWER SUPPLY CONSIDERATIONS The AD558 is designed to operate from a single positive power supply voltage. Specified performance is achieved for any supply voltage between +4.5 V and +16.5 V. This makes the AD558 ideal for battery-operated, portable, automotive or digital mainframe applications. Figure 7 shows the timing for the data and control signals; CE and CS are identical in timing as well as in function. *For additional insight, “An IC Amplifier Users’ Guide to Decoupling, Grounding and Making Things Go Right For A change,” is available at no charge from any Analog Devices Sales Office. REV. B –5– AD558 tDH DATA INPUTS 2.0V tDS 0.8V VOUT 16 AD558 VOUT SENSE 15 RL 2.0V CS OR CE 0.8V RP-D = 2x VEE NEGATIVE SUPPLY tW 1/2 LSB DAC V OUTPUT tSETTLING tW = STORAGE PULSE WIDTH = 200ns MIN tDH = DATA HOLD TIME = 10ns MIN tDS = DATA SETUP TIME = 200ns MIN tSETTLING = DAC OUTPUT SETTLING TIME TO ±1/2 LSB VEE (in kΩ) Figure 9. Improved Settling Time available, bipolar output ranges may be achieved by suitable output offsetting and scaling. Figure 10 shows how a ± 1.28 volt output range may be achieved when a –5 volt power supply is available. The offset is provided by the AD589 precision 1.2 volt reference which will operate from a +5 volt supply. The AD544 output amplifier can provide the necessary ± 1.28 volt output swing from ± 5 volt supplies. Coding is complementary offset binary. Figure 7. AD558 Timing 5kΩ VOUT = 0V TO +2.56V USE OF VOUT SENSE Separate access to the feedback resistor of the output amplifier allows additional application versatility. Figure 8a shows how I × R drops in long lines to remote loads may be cancelled by putting the drops “inside the loop.” Figure 8b shows how the separate sense may be used to provide a higher output current by feeding back around a simple current booster. 16 AD558 5kΩ 15 AD544 14 12 4.53kΩ 16 VIN 15 12 VOUT 0V TO +10V 14 13 0.01µF VO +1.28 TO –1.27 1.5kΩ –5V INPUT CODE –1.2V 4.7kΩ 00000000 10000000 11111111 RL GAIN SELECT GND 500Ω BIPOLAR OFFSET ADJUST VOUT VOUT SENSE 0.01µF 13 AD589 AD558 +5V 0.01µF VOUT +128V 0V –1.27V –5V Figure 10. Bipolar Operation of AD558 from ±5 V Supplies a. Compensation for I × R Drops in Output Lines MEASURING OFFSET ERROR One of the most commonly specified endpoint errors associated with real-world nonideal DACs is offset error. VCC AD558 16 15 12 VOUT 2N2222 VOUT SENSE VOUT 0V TO +2.56V 14 13 GND GAIN SELECT RL b. Output Current Booster Figure 8. Use of VOUT Sense OPTIMIZING SETTLING TIME In order to provide single-supply operation and zero-based output voltage ranges, the AD558 output stage has a passive “pull-down” to ground. As a result, settling time for negative going output steps may be longer than for positive-going output steps. The relative difference depends on load resistance and capacitance. If a negative power supply is available, the negative-going settling time may be improved by adding a pulldown resistor from the output to the negative supply as shown in Figure 9. The value of the resistor should be such that, at zero voltage out, current through that resistor is 0.5 mA max. In most DAC testing, the offset error is measured by applying the zero-scale code and measuring the output deviation from 0 volts. There are some DACs, like the AD558 where offset errors may be present but not observable at the zero scale, because of other circuit limitations (such as zero coinciding with singlesupply ground) so that a nonzero output at zero code cannot be read as the offset error. Factors like this make testing the AD558 a little more complicated. By adding a pulldown resistor from the output to a negative supply as shown in Figure 11, we can now read offset errors at zero code that may not have been observable due to circuit limitations. The value of the resistor should be such that, at zero voltage out, current through the resistor is 0.5 mA max. OUTPUT AMP 16 BIPOLAR OUTPUT RANGES –V 15 VOUT SENSE 14 VOUT SELECT 13 The AD558 was designed for operation from a single power supply and is thus capable of providing only unipolar (0 V to +2.56 V and 0 V to 10 V) output ranges. If a negative supply is 0.5mA VOUT AGND a. 0 V to 2.56 V Output Range –6– REV. B AD558 OUTPUT AMP ADDRESS BUS 16 0.5mA VOUT 16 16 –V 15 VOUT SENSE 14 VOUT SELECT ADDRESS SELECT PULSE LOGIC 8080A CS MEMW 13 AD558 VOUT CE AGND DB0–DB7 b. 0 V to 10 V Output Range Figure 11. Offset Connection Diagrams 8 8 DATA BUS INTERFACING THE AD558 TO MICROPROCESSOR DATA BUSES MEMW → CE DECODED ADDRESS SELECT PULSE → CS The AD558 is configured to act like a “write only” location in memory that may be made to coincide with a read only memory location or with a RAM location. The latter case allows data previously written into the DAC to be read back later via the RAM. Address decoding is partially complete for either ROM or RAM. Figure 12 shows interfaces for three popular microprocessor systems. b. 8080A/AD558 Interface 8 ADDRESS BUS 8 MA 0 – 7 ADDRESS LATCH & DECODE TPA 1802 ADDRESS BUS CS AD558 16 16 DB0–DB7 ADDRESS DECODER 6800 VOUT CE MWR 8 8 VMA VOUT CS DATA BUS AD558 φ2 CDP 1802: MWR → CE DECODED ADDRESS SELECT PULSE → CS CE R/W DB0–DB7 c. 1802/AD558 Interface Figure 12. Interfacing the AD558 to Microprocessors 8 8 DATA BUS R/W → CE GATED DECODED ADDRESS → CS a. 6800/AD558 Interface Performance (typical @ +258C, V CC 6 +5 V to +15 V unless otherwise noted) LSB 1.75 1.50 1.25 LSB ALL AD558 AD558S, T 1.00 ALL AD558 AD558S, T 1/2 ZERO ERROR 0.75 0.50 0.25 FULL 0 SCALE –0.25 ERROR –0.50 1/4 0 –55 –25 0 +25 +50 +75 +100 +125 oC –1/4 –0.75 –1.00 –1/2 –55 –25 0 +25 +50 +75 +100 1LSB = 0.39% OF FULL SCALE +125 oC Figure 13. Full-Scale Accuracy vs. Temperature Performance of AD558 REV. B 1LSB = 0.39% OF FULL SCALE Figure 14. Zero Drift vs. Temperature Performance of AD558 –7– OUTLINE DIMENSIONS AD558 0.775 0.755 0.735 16 1 8 14 TOP VIEW 0.100 BSC 12 0.210 MAX SIDE VIEW 0.015 MIN 0.150 0.130 0.115 10 0.022 0.018 0.015 4 6 8 10 12 14 16 0.325 0.310 0.300 0.195 0.130 0.115 SEATING PLANE 0.021 0.016 0.011 0.070 0.045 0.060 0.039 0.055 0.030 0.015 GAUGE PLANE END VIEW 0.012 0.010 0.008 0.430 MAX COMPLIANT TO JEDEC STANDARDS MS-001-BB 18 VOLTS 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-16) Dimensions shown in inches VCC Figure 15. Quiescent Current vs. Power Supply Voltage for AD558 0.005 (0.13) MIN PIN 1 0.080 (2.03) MAX 16 9 1 8 0.310 (7.87) 0.220 (5.59) 0.840 (21.34) MAX 0.200 (5.08) MAX 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.015 (0.38) 0.008 (0.20) 0.100 0.070 (1.78) SEATING (2.54) 0.030 (0.76) PLANE BSC 0.023 (0.58) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 16-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-16) Dimensions shown in inches and (millimeters) Figure 16. AD558 Settling Characteristics Detail 0 V to 2.56 V Output Range Full-Scale Step 0.180 (4.57) 0.165 (4.19) 0.048 (1.22 ) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 3 4 PIN 1 IDENTIFIER 18 TOP VIEW (PINS DOWN) 8 9 0.020 (0.51) R 0.20 (0.51) MIN 19 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 14 13 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.03) SQ 0.385 (9.78) 0.020 (0.50) R BOTTOM VIEW (PINS UP) 0.045 (1.14) R 0.025 (0.64) 0.120 (3.04) 0.090 (2.29) COMPLIANT TO JEDEC STANDARDS MO-047-AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.100 (2.54) 0.064 (1.63) 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.088 (2.24) 0.054 (1.37) 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.055 (1.40) 0.045 (1.14) 3 4 19 18 20 1 BOTTOM VIEW 14 13 8 9 0.150 (3.81) BSC 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 45° TYP CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) Dimensions shown in inches and (millimeters) Figure 18. AD558 Logic Timing –8– PRINTED IN U.S.A. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20) Dimensions shown in inches and (millimeters) Figure 17. AD558 Settling Characteristic Detail 0 V to 10 V Output Range Full-Scale Step REV. B 022106-A ICC 0.280 0.250 0.240 9 16 PIN 1 INDICATOR 03-07-2014-D mA Data Sheet AD558 ORDERING GUIDE Model AD558JN AD558JNZ AD558JP AD558JP-REEL7 AD558JPZ AD558JPZ-REEL AD558JPZ-REEL7 AD558JD AD558KN AD558KNZ AD558KP AD558KPZ AD558KPZ-REEL7 AD558KD AD558SD AD558TD AD558TCHIPS AD558SD/883B AD558SE/883B AD558TD/883B AD558TE/883B Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C Relative Accuracy Error Max TMIN to TMAX ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/4 LSB ±1/4 LSB ±1/4 LSB ±1/4 LSB ±1/4 LSB ±1/4 LSB ±3/4 LSB ±3/8 LSB ±3/8 LSB ±3/4 LSB ±3/4 LSB ±3/8 LSB ±3/8 LSB 1 Full Scale Error Max TMIN to TMAX ±2.5 LSB ±2.5 LSB ±2.5 LSB ±2.5 LSB ±2.5 LSB ±2.5 LSB ±2.5 LSB ±2.5 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±2.5 LSB ±1 LSB ±1 LSB ±2.5 LSB ±2.5 LSB ±1 LSB ±1 LSB Package Option PDIP (N-16) PDIP (N-16) PLCC (P-20) PLCC (P-20) PLCC (P-20) PLCC (P-20) PLCC (P-20) SBDIP (D-16) PDIP (N-16) PDIP (N-16) PLCC (P-20) PLCC (P-20) PLCC (P-20) SBDIP (D-16) SBDIP (D-16) SBDIP (D-16) Die part SBDIP (D-16) LCC (E-20-1) SBDIP (D-16) LCC (E-20-1) For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD558/883B data sheet. 2 S = Ceramic SBDIP; N = Plastic PDIP; P = Plastic Leaded Chip Carrier. REVISION HISTORY 6/2017—Rev. A to Rev. B Added Bond Pad Coordinates Table............................................... 3 Updated Outline Dimensions .......................................................... 8 Changes to Ordering Guide ............................................................. 9 ©1987–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09374-0-6/17(B) –9–