Sony CXL1506N Cmos-ccd 1h/2h delay line for pal Datasheet

CXL1506M/N
CMOS-CCD 1H/2H Delay Line for PAL
For the availability of this product, please contact the sales office.
Description
The CXL1506M/N is a CMOS-CCD delay line
developed for video signal processing. Usage in
conjunction with an external low pass filter provides
1H and 2H delay signals simultaneously (For PAL
signals).
Features
• Single power supply (5V)
• Low power consumption
• Built-in peripheral circuits
• Built-in tripling PLL circuit
• For PAL signals
• 1 input and 2 outputs
(Outputs for both 1H and 2H delays)
CXL1506M
16 pin SOP (Plastic)
Blook Diagram
CXL1506N
CXL1506N
20 pin SSOP (Plastic)
CXL1506M
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
• Operating temperature Topr
–10 to +60
°C
• Storage temperature
Tstg
–55 to +150
°C
• Allowable power dissipation
PD CXL1506M 400 mW
CXL1506N 300 mW
Recommended Operating Voltage (Ta = 25°C)
VDD
5 ± 0.25
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
VCLK 0.2 to 1.0Vp-p (0.4Vp-p Typ.)
• Input clock frequency
fCLK
4.433619 MHz
• Input clock waveform
sine wave
Input Signal Amplitude
VSIG 575 (Max.) mVp-p (at internal clamp condition)
VSS
AB
16
15
AA
AA
VDD
VCO
IN
PC
OUT
VSS
CLK
VDD
VSS
NC
AB
VDD
VCO
IN
PC
OUT
14
13
12
11
10
9
20
19
18
17
16
15
PLL
Driver
Clamp circuit
CCD (1698bits)
847bits
S/H 1bit
1
2
3
IN
VG1
VG2
4
OUT1
(1H)
847bits
Bias
circuit
Output circuit
Output circuit
5
VSS
6
7
OUT2
VSS
(2H) (VCO OUT)
1
NC
8
VSS
2
IN
3
VG1
CLK
VDD
13
12
11
PLL
Timing
1698bits
Output circuit
S/H 1bit
S/H 1bit
NC
14
CCD (1698bits)
Clamp circuit
1698bits
Output circuit
VSS
Driver
Autobias circuit
Timing
Autobias circuit
AA
AA
4
VG2
Bias
circuit
S/H 1bit
5
OUT1
(1H)
6
VSS
7
OUT2
(2H)
8
NC
9
10
VSS
VSS
(VCO OUT)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E89X22C78-PS
CXL1506M/N
Pin Description (CXL1506M)
Pin No.
Symbol
I/O
Description
IN
I
Signal input
(Non-inverted signal)
VG1
O
Gate bias 1 DC output
VG2
I
Gate bias 2 DC input
4
OUT1
O
1H signal output
(Inverted signal)
5
VSS
—
GND
6
OUT2
O
2H signal output
(Inverted signal)
7
VSS (VCO OUT)
(O)
GND or VCO output (3fsc)
8
VSS
—
GND
9
VDD
—
Power supply (5V)
10
CLK
I
11
VSS
—
GND
12
PC OUT
O
Phase comparator output
13
VCO IN
I
VCO input
14
VDD
—
Power supply (5V)
15
AB
O
Autobias DC output
16
VSS
—
GND
1
2
3
(Note)
Clock input (fsc)
Impedance [Ω]
> 10kΩ (at no clamp)
40 to 500Ω
40 to 500Ω
> 10kΩ
600 to 200kΩ
Note) Description of VG2
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
–2–
CXL1506M/N
Pin Description (CXL1506N)
Pin No.
Symbol
I/O
Description
—
1
NC
—
2
IN
I
Signal input
(Non-inverted signal)
VG1
O
Gate bias 1 DC output
VG2
I
Gate bias 2 DC input
5
OUT1
O
1H signal output
(Inverted signal)
6
VSS
—
GND
7
OUT2
O
2H signal output
(Inverted signal)
8
NC
—
9
VSS (VCO OUT)
(O)
GND or VCO output (3fsc)
10
VSS
—
GND
11
VDD
—
Power supply (5V)
12
CLK
I
13
NC
—
14
VSS
—
GND
15
PC OUT
O
Phase comparator output
16
VCO IN
I
VCO input
17
VDD
—
Power supply (5V)
18
AB
O
Autobias DC output
19
NC
—
20
VSS
—
3
4
(Note)
Impedance [Ω]
> 10kΩ (at no clamp)
40 to 500Ω
40 to 500Ω
—
Clock input (fsc)
> 10kΩ
—
600 to 200kΩ
—
GND
Note) Description of VG2
Control of input signal clamp condition
0V … Sync tip clamp condition
5V … Center bias condition
The input signal is biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ ).
In this mode the input signal is limited to the APL 50% and the maximum input signal amplitude is
at 200mVp-p.
–3–
CXL1506M/N
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 400mVp-p sine wave)
See Electrical Characteristics Test Circuit.
Item
Supply current
Low frequency
gain
Frequency
response
Differential gain
Differential phase
S/N ratio
S/H pulse coupling
Symbol
IDD
GL1
GL2
fR1
fR2
DG1
DG2
DP1
DP2
SN1
SN2
CP1
CP2
Test conditions
(Note 1)
SW conditions
Min.
Typ.
Max.
Unit
Note
b a a
17
27
37
mA
2
a
b a b
–2
0
2
b b b
–2
0
2
dB
3
a
–2.7
–1.7
–0.7
–2.8
–1.8
–0.8
dB
4
%
5
degree
5
dB
6
mVp-p
7
1
2 3 4
—
a
200kHz
500mVp-p sine wave
←c a a b
200kHz →
← 4.434MHz b →
150mVp-p sine wave b →
←c a b b
5 staircase wave
5 staircase wave
No signal input
No signal input
d
b a c
—
5
7
d
b b c
—
5
7
d
b a c
—
5
7
d
b b c
—
5
7
e
b a d
52
56
—
e
b b d
52
56
—
e
b a a
—
—
350
e
b b a
—
—
350
–4–
–5–
SW1
1µ
1M
2
1000P
1
IN
120
0.1µ
0.1µ
a
4
b
SW2
1000P
3
5
7
(See the block diagram and pin configuration. For NC pins, ground them.)
6
8
1000P
a
b
SW4
d
c
b
a
Note 2)
BPF frequency response
Noise meter
Vector scope
Spectrum analyzer
Oscilloscope
0 200
6M 13.3M
f-Frequency [Hz]
–50
–50
6M 13.3M
f-Frequency [Hz]
0
–3
0
[dB]
0
–3
Note 2)
BPF
LPF
Note 1)
[dB]
Note 1)
LPF frequency response
SW3
CLK
fSC (4.433619MHz), 400mVp-p
sine wave
3.3µ
3.3µ 1000P 82k
13
9
12
15
14
10
11
AB VDD VCO PC VSS CLK VDD
IN OUT
Vss
(VCO
VG1 VG2 OUT1 VSS OUT2 OUT) VSS
A
∗ When using CXL1506N, change the connection terminal only.
e
d
c
4.434MHz
150mVp-p
sine wave
5-staircase wave
b
a
200kHz
150mVp-p
sine wave
200kHz
500mVp-p
sine wave
16
VSS
1µ
5V
Electrical Characteristics Test Circuit (CXL1506M)
CXL1506M/N
CXL1506M/N
Notes)
1) By switching SW2, input condition turns out as follows.
SW2 condition
Input condition
a
Center bias condition (approx. 2.1V)
Approx. 2.1V bias is applied internally to the input signal
b
Sync tip and clamp conditions
2) This is the IC supply current value during clock and signal input.
3) GL is the output gain of pin OUT when a 500mVp-p, 200kHz sine wave is fed to pin IN.
GL = 20 log
pin OUT output voltage [mVp-p]
[dB]
500 [mVp-p]
4) Indicates the dissipation at 4.434MHz in relation to 200kHz. From the output voltage at pin OUT when a
150mVp-p, 200kHz sine wave is fed to pin IN, and from the output voltage at pin OUT when a 150mVp-p,
4.434MHz sine wave is fed to same, calculation is made according to the following formula.
fR = 20 log
pin OUT output voltage (4.434MHz) [mVp-p]
[dB]
pin OUT output voltage (200kHz) [mVp-p]
5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure
is fed, are tested with a vector scope:
150mV
275mV
500mV
150mV
1H 64µs
–6–
CXL1506M/N
6) The noise level of the output signal at no-input signal is tested with a video noise meter in the Sub Carrier
Trap mode at BPF 100kHz to 5MHz. (Vn [Vrms])
The signal component is determined either by testing the output voltage (the same testing system as for
noise level) at the input of 350mVp-p, 200kHz, or by utilizing values from GL to calculate according to the
following formula. (Vs [Vp-p])
(Example of Vs calculation)
GL
20
Vs = 0.35 × 10
(Example of SN ratio calculation)
SN = 20 log
Vn (noise component) [Vrms]
[dB]
Vs (signal component) [Vp-p]
7) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
Test value [mVp-p]
fsc (4.433619MHz) sine wave
Clock
400mVp-p
(typ.)
–7–
–8–
1M
Note) When using Pin 7(VCO OUT),
use the circuit as shown below.
When not using it, GND.
Signal input
(Non-inverted signal)
AA
1µ
2
1
V1
12
120
82k
0.1µ
4
6
11
8
9
62P
100
Transistor used
PNP: 2SA1175
1k
470
A
7
10
3.3µ
330k
560k
0.1µ
1000P
(Inverted signal)
0.1µ
62P
100
Delay time
210ns
LPF
Transistor used
PNP: 2SA1175
1k
470
CLK
fSC (4.433619MHz), 400mVp-p
sine wave
2.2k
2.2k
2.2k
Transistor used
NPN: 2SC403
Delay time
230ns
LPF
(Non-inverted signal)
AA
(Non-inverted signal)
2H Output
5V
3fsc OUT
1.8k
2SC403
2.2k
5V
Transistor used
NPN: 2SC403
A
2.2k
2.2k
1.8k
1H Output
5V
7
Note) When VCO OUT is required, use the circuit below.
∗ When using CXL1506N, change the connection terminal only.
(See the block diagram and pin configuration. For NC pins, ground them.)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
560k
0.1µ
330k
5
CXL1506M
13
1000P
3
14
1000P
5V
(Inverted signal)
A
1000P
15
3.3µ
16
1µ
Application Circuit (CXL1506M)
CXL1506M/N
CXL1506M/N
Example of Representative Characteristics
Low frequency gain (1H) vs. Ambient temperature
Supply current vs. Ambient temperature
2
Low frequency gain 1H [dB]
Supply current [mA]
35
25
15
–20
0
20
40
60
1
0
–1
–2
–20
80
0
Low frequency gain (2H) vs. Ambient temperature
Frequency response 1H [dB]
Low frequency gain 2H [dB]
60
80
0
1
0
–1
0
20
40
60
–1
–2
–3
–20
80
0
Ambient temperature [°C]
Frequency response (2H) vs. Ambient temperature
20
40
60
Ambient temperature [°C]
80
Differential gain (1H) vs. Ambient temperature
10
0
8
Differential gain 1H [%]
Frequency response 2H [dB]
40
Frequency response (1H) vs. Ambient temperature
2
–2
–20
20
Ambient temperature [°C]
Ambient temperature [°C]
–1
–2
6
4
2
–3
–20
0
20
40
60
Ambient temperature [°C]
0
–20
80
0
20
40
Ambient temperature [°C]
–9–
60
80
CXL1506M/N
Differential gain (2H) vs. Ambient temperature
Supply current vs. Supply voltage
10
35
Supply current [mA]
Differential gain 2H [%]
8
6
4
25
2
0
–20
0
20
40
60
15
4.75
80
Ambient temperature [°C]
Low frequency gain (1H) vs. Supply voltage
Low frequency gain 2H [dB]
2
1
0
–1
5
1
0
–1
–2
4.75
5.25
5
5.25
Supply voltage [V]
Supply voltage [V]
Frequency response (1H) vs. Supply voltage
Frequency response (2H) vs. Supply voltage
0
0
Frequency response 2H [dB]
Low frequency gain 1H [dB]
Frequency response 1H [dB]
5.25
Low frequency gain (2H) vs. Supply voltage
2
–2
4.75
5
Supply voltage [V]
–1
–2
–3
4.75
5
–1
–2
–3
4.75
5.25
5
Supply voltage [V]
Supply voltage [V]
– 10 –
5.25
CXL1506M/N
Differential gain (2H) vs. Supply voltage
10
8
8
Differential gain 2H [%]
Differential gain 1H [%]
Differential gain (1H) vs. Supply voltage
10
6
4
2
6
4
2
0
4.75
5
0
4.75
5.25
5
Supply voltage [V]
5.25
Supply voltage [V]
Frequency response (1H)
2
Gain [dB]
0
–2
–4
–6
10K
100K
1M
10M
1M
10M
Frequency [Hz]
Frequency response (2H)
2
Gain [dB]
0
–2
–4
–6
10K
100K
Frequency [Hz]
Note) 1H and 2H shown in brackets indicate 1H and 2H outputs.
– 11 –
CXL1506M/N
Unit: mm
CXL1506M
16PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
9.9 – 0.1
16
9
6.9
8
+ 0.1
0.2 – 0.05
1.27
0.45 ± 0.1
0.5 ± 0.2
1
+ 0.2
0.1 – 0.05
7.9 ± 0.4
+ 0.3
5.3 – 0.1
0.15
0.24 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
SONY CODE
SOP-16P-L01
EIAJ CODE
SOP016-P-0300
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
CXL1506N
20PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗6.5 ± 0.1
0.1
11
20
A
1
6.4 ± 0.2
∗4.4 ± 0.1
10
+ 0.05
0.15 – 0.02
0.65
+ 0.1
0.22 – 0.05
0.13 M
0.1 ± 0.1
0.5 ± 0.2
Package Outline
0° to 10°
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-20P-L01
LEAD TREATMENT
SOLDER / PALLADIUM
PLATING
EIAJ CODE
SSOP020-P-0044
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
– 12 –