ICST ICS650-14B Networking system clock Datasheet

PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Description
Features
The ICS650-14B is a low cost, low jitter, high
performance clock synthesizer customized for
networking systems applications. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 25.0 MHz clock or fundamental mode
crystal input to produce multiple output clocks of
one fixed 25.0 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable
clocks. All output clocks are frequency locked
together. The ICS650R-14B outputs
all have 0 ppm synthesis error.
• Packaged in 20 pin (150 mil) SSOP (QSOP)
• 25.00 MHz fundamental crystal or clock input
• One fixed output clock of one 25.0 MHz
• One bank of four frequency selectable
output clocks
• Three frequency selectable clock outputs
• Zero ppm synthesis error in all clocks
• Ideal for networking systems
• Full CMOS output swing
• Advanced, low power, sub-micron CMOS process
• 3.0V to 5.5V operating voltage
• Industrial temperature range available
Block Diagram
SELA 0:1
SELB 0:1
VDD
GND
2
2
2
Output
Buffer
2
Clock Synthesis
and Control
Circuitry
SELC
25.00 MHz
crystal or clock
X1/ICLK
X2
Clock
Buffer/
Crystal
Oscillator
4
CLKA 1:4
Output
Buffer
CLKA5
Output
Buffer
CLKB
Output
Buffer
CLKC
Output
Buffer
25.00 MHz
OE (All outputs)
Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).
1
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
MDS 650-14B A
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Table 1
Pin Assignment
SELB0
X2
X1/ICLK
VDD
SELB1
GND
CLKB
CLKC
CLKA5
25M
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SELC
SELA0
CLKA2
CLKA3
VDD
SELA1
GND
CLKA4
CLKA1
OE
20 pin (150 mil) SSOP
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
SELB0
X2
X1/ICLK
VDD
SELB1
GND
CLKB
CLKC
CLKA5
25M
OE
CLKA1
CLKA4
GND
SELA1
VDD
CLKA3
CLKA2
SELA0
SELC
Type
TI
XO
XI
P
I(Pu)
P
O
O
O
O
I(Pu)
O
O
P
TI
P
O
O
TI
TI
SELA1
0
0
0
M
M
M
1
1
1
SELA0
0
M
1
0
M
1
0
M
1
CLKA1:4
33.33
50
66.67
100
33.33
50
33.33
25
66.67
Table 3
Table 2
SELB1
0
0
0
1
1
1
CLKA5
66.66
75
133.33
33.33
83.33
125
100
75
100
SELB0
0
M
1
0
M
1
CLKB
30
27
48
83.33
19.44
80
SELC
0
M
1
CLKC
CLKB/4
62.5
125
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Description
Select pin for CLKB. See Table 2.
Crystal connection. Connect to 25 MHz crystal or leave unconnected for a clock input.
Crystal connection. Connect to 25 MHz fundamental crystal or clock input.
Connect to +3.3 V or +5 V. Must be same as other VDDs.
Select pin for CLK B. See table 2.
Connect to ground.
Selectable clock output. See Table 2.
Selectable clock output. See Table 3.
Selectable clock output. See Table 1.
25.0 MHz clock output.
Output Enable. Tri-states all output clocks when low. Internal pull-up.
Selectable clock output. See Table 1.
Selectable clock output. See Table 1.
Connect to ground.
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Connect to +3.3V or +5.0V. Must be same as other VDDs.
Selectable clock output. See Table 1.
Selectable clock output. See Table 1.
Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
Select pin for CLKC output. See Table 3.
Key: XI, XO = crystal connections; I = Input; I(Pu) = Input with pull up O = Output; P = power supply connection; TI = tri level input
2
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
MDS 650-14B A
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
7
VDD+0.5
70
85
260
150
V
V
°C
°C
°C
°C
5.5
V
V
V
V
V
V
V
V
V
V
mA
mA
ABSOLUTE MAXIMUM RATINGS (n
note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Referenced to GND
Referenced to GND
Industrial "I" version
Max of 20 seconds
-0.5
0
-40
-65
DC CHARACTERISTICS (VDD = 3.3V
V unless noted)
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH, SEL pins only
Input Low Voltage, VIL, SEL pins only
Input High Voltage, VIH, OE pin only
Input Low Voltage, VIL, OE pin only
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
Clock Input
Clock Input
3
VDD/2 + 1
VDD/2 - 1
VDD - 0.5
0.5
2.0
0.8
IOH=-12mA
IOL=12mA
IOH=-8mA
No Load
Each output
2.4
0.4
VDD-0.4
TBD
±50
AC CHARACTERISTICS (VDD = 3.3V
V unless noted)
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Frequency error
Absolute Jitter, short term
Notes:
25.000
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
All clocks
Variation from mean
45
50
TBD
1.5
1.5
55
0
MHz
ns
ns
%
ppm
ps
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. CMOS level input, nominal trip point is VDD/2 for 3.3 V or 5 V operation.
External Components
The ICS650R-14B requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND on Pins 4 and 6, and Pins 16 and
14, as close to the ICS650R-14B as possible. A series termination resistor of 33 Ω may be used for each
clock output. The 25.00 MHz crystal must be connected as close to the chip as possible. The crystal should
be a fundamental mode (do not use third overtone), parallel resonant. Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to optimize the initial accuracy. The value of these
capacitors is given by the following equation, where CL is the crystal load capacitance: Crystal caps (pF) =
(CL-6) x 2. So for a crystal with 16 pF load capacitance, two 20 pF caps should be used.
3
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
MDS 650-14B A
PRELIMINARY INFORMATION
ICS650-14B
Networking System Clock
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
20 pin SSOP
E1
INDEX
AREA
1
E
2
D
c
A1
e
b
Symbol
A
A1
b
c
D
e
E
E1
L
Inchees
Min
Max
0.053 0.069
0.004 0.010
0.008 0.012
0.007 0.010
0.337 0.344
.025 BSSC
0.228 0.244
0.150 0.157
0.016 0.050
Millim
meters
Min
Max
1.35
1.75
0.10
0.25
0.20
0.30
0.18
0.25
8.55
8.75
0.635 BSC
5.80
6.20
3.80
4.00
0.40
1.27
A
L
Ordering Information for ICS650-14B
Part/Order Number
ICS650R-14
ICS650R-14T
ICS650R-14I
ICS650R-14I
Marking
ICS650R-14
ICS650R-14
ICS650R-14I
ICS650R-14I
Shipping packaging
tubes
tape and reel
tubes
tape and reel
Package
20 pin SSOP
20 pin SSOP
20 pin SSOP
20 pin SSOP
Temperature
0 to +70 °C
0 to +70 °C
-40 to +85 °C
-40 to +85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
4
Revision 082800
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel• www.icst.com
MDS 650-14B A
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