ON MC14013B Dual type d flip-flop Datasheet

MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flip–flop is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each flip–flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register
elements or as type T flip–flops for counter and toggle applications.
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http://onsemi.com
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going
edge of the clock pulse
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Pin–for–Pin Replacement for CD4013B
MARKING
DIAGRAMS
14
PDIP–14
P SUFFIX
CASE 646
MC14013BCP
AWLYYWW
1
14
SOIC–14
D SUFFIX
CASE 751A
14013B
AWLYWW
1
14
TSSOP–14
DT SUFFIX
CASE 948G
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
VDD
Vin, Vout
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Value
Unit
– 0.5 to +18.0
V
– 0.5 to VDD + 0.5
± 10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
SOEIAJ–14
F SUFFIX
CASE 965
MC14013B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
v
1
14
V
Input or Output Current
(DC or Transient) per Pin
Iin, Iout
14
013B
ALYW
v
Device
Package
Shipping
MC14013BCP
PDIP–14
2000/Box
MC14013BD
SOIC–14
55/Rail
MC14013BDR2
SOIC–14
2500/Tape & Reel
MC14013BDT
TSSOP–14
96/Rail
MC14013BDTR2
TSSOP–14 2500/Tape & Reel
MC14013BF
SOEIAJ–14
See Note 1.
MC14013BFEL
SOEIAJ–14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14013B/D
MC14013B
TRUTH TABLE
Inputs
Clock†
Outputs
Data
Reset
Set
Q
Q
0
0
0
0
1
1
0
0
1
0
X
0
0
Q
Q
X
X
1
0
0
1
X
X
0
1
1
0
X
X
1
1
1
1
X = Don’t Care
† = Level Change
PIN ASSIGNMENT
QA
1
14
VDD
QA
2
13
QB
CA
3
12
QB
RA
4
11
CB
DA
5
10
RB
SA
6
9
DB
VSS
7
8
SB
BLOCK DIAGRAM
6
5
D
3
C
S
R
Q
1
Q
2
Q
13
Q
12
4
8
9
D
11
C
S
R
10
VDD = PIN 14
VSS = PIN 7
http://onsemi.com
2
No
Change
MC14013B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
30
60
120
µAdc
IT
5.0
10
15
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink
Total Supply Current (5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (0.75 µA/kHz) f + IDD
IT = (1.5 µA/kHz) f + IDD
IT = (2.3 µA/kHz) f + IDD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
http://onsemi.com
3
µAdc
MC14013B
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SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Clock to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
tPLH
tPHL
VDD
Min
Typ (8.)
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
ns
5.0
10
15
—
—
—
175
75
50
350
150
100
Set to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns
5.0
10
15
—
—
—
175
75
50
350
150
100
Reset to Q, Q
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns
5.0
10
15
—
—
—
225
100
75
450
200
150
Setup Times (9.)
tsu
5.0
10
15
40
20
15
20
10
7.5
—
—
—
ns
Hold Times (9.)
th
5.0
10
15
40
20
15
20
10
7.5
—
—
—
ns
tWL, tWH
5.0
10
15
250
100
70
125
50
35
—
—
—
ns
fcl
5.0
10
15
—
—
—
4.0
10
14
2.0
5.0
7.0
MHz
tTLH
tTHL
5.0
10
15
—
—
—
—
—
15
5.0
4.0
µs
—
tWL, tWH
5.0
10
15
250
100
70
125
50
35
—
—
—
ns
5
10
15
80
45
35
0
5
5
—
—
—
5
10
15
50
30
25
– 35
– 10
–5
—
—
—
Clock Pulse Width
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
Set and Reset Pulse Width
trem
Removal Times
Set
ns
Reset
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
9. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.
LOGIC DIAGRAM (1/2 of Device Shown)
S
C
C
Q
D
C
C
C
C
C
C
C
C
C
R
http://onsemi.com
4
Q
MC14013B
20 ns
20 ns
90%
50%
10%
D
tsu (L)
th
tsu (H)
C
tWH
SET OR
RESET
20 ns
VDD
90%
50%
tw
VSS
10%
trem
20 ns
tPHL
tTLH
VSS
20 ns
90%
50%
CLOCK
90%
50%
10%
Q
20 ns
VSS
20 ns
VDD
90%
50%
10%
tWL
1
fcl
tPLH
VDD
tw
tPLH
tPHL
VOH
VSS
VOH
Q OR Q
VOL
10%
VDD
50%
VOL
tTHL
Inputs R and S low.
Figure 1. Dynamic Signal Waveforms
(Data, Clock, and Output)
Figure 2. Dynamic Signal Waveforms
(Set, Reset, Clock, and Output)
TYPICAL APPLICATIONS
n–STAGE SHIFT REGISTER
1
D
nth
2
D
Q
D
Q
D
Q
C
Q
C
Q
C
Q
Q
CLOCK
BINARY RIPPLE UP–COUNTER (Divide–by–2n)
1
CLOCK
nth
2
D
Q
D
Q
D
Q
C
Q
C
Q
C
Q
Q
T FLIP–FLOP
MODIFIED RING COUNTER (Divide–by–(n+1))
1
nth
2
D
Q
D
Q
D
Q
C
Q
C
Q
C
Q
CLOCK
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5
Q
MC14013B
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
N
C
–T–
SEATING
PLANE
J
K
H
D 14 PL
G
M
0.13 (0.005)
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
–––
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
–––
10_
0.38
1.01
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
B
M
M
R X 45 _
C
F
–T–
SEATING
PLANE
0.25 (0.010)
M
K
D 14 PL
M
T B
S
A
S
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6
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
MC14013B
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
V
S
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
–V–
ÇÇÇ
ÉÉ
ÇÇÇ
ÉÉ
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
G
D
DETAIL E
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965–01
ISSUE O
14
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
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7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
–––
1.20
–––
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60
0.020
0.024
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
1.42
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.056
MC14013B
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
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MC14013B/D