LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET KEY FEATURES DESCRIPTION IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com 12Wx2 @ 4Ω THD+N<1% 16Wx2 @ 4Ω THD+N<10% 25W BTL @ 8Ω THD+N<1% 32W BTL @ 8Ω THD+N<10% High Efficiency: >90% @8Ω Full Audio Band: 20Hz~20KHz Low Distortion: <0.1% @1KHz, 8Ω <0.4% @20~20KHz, 8Ω High Signal-to-Noise Ratio: >85dB non A-Weighted Split/Single Power Supply Wide Supply Voltage Range: ±6V ~ ±15V or 12V ~ 30V Low Quiescent Current <20mA Turn ON/OFF POP Free STANDBY/MUTE Feature Programmable Gain 14/20/26dB Built-in Over Current Protection Built-in Under Voltage Lockout Thermal Shut Down Power Limiting Based on Die Temperature (gain fold back) Synchronization WWW . Microsemi .C OM The LX1725 features Mute and Standby modes, over-current protection, POP-free turn-on and turn-off, undervoltage lockout, over-voltage protection and over-temperature protection. All built-in protection modes allow automatic recovery when the fault condition has been cleared. The gain is pin selectable between 14 / 20 / 26dB to accommodate different signal source amplitudes. Several LX1725s can be easily synchronized together to prevent beat frequency interference in multichannel applications.. The LX1725 comes in a MLPQ 32 pin package with a 7mmx7mm small outline surface mount. The Microsemi LX1725 is part of a new generation of fully integrated stereo class-D amplifiers from Microsemi. The fully integrated halfbridge output for each channel works with both split and single power supply operation. The outputs can be bridged to run in BTL (Bridge Tied Load) mode. In BTL mode, 3-level modulation is used which allow operation without an L-C filter to reduce system cost and area. The LX1725 has >90% efficiency, with typical output power up to 15W+15W in stereo, and 30W BTL into a 4Ω load with less than 1% THD+N. The amplifier operates over a wide supply voltage range of ±6V to ±15V split supply or 12V to 30V single supply, and consumes a very little quiescent current. PRODUCT HIGHLIGHT HIGAIN VCOM +5V IN1P 4.7µF 35V 1µF IN1N APPLICATIONS VCOM 1µF 6 7 C OSC V5V VCOM N.C. OUTREF1 N.C. HIGAIN VNEG2 VREF OUT2 COSC VNEGA 9 IN2N IN1M RILIM VNEG IN2P VNEG1 LX1725 IN2P 8 OUT1 FLAG 10 11 12 13 VPOS2 14 15 STBY 24 VPOS STBY SYNC 25 MASTER 23 22 21 20 22µH 820nF 19 18 820nF VNEG LCD TV, PDP Sets CD/DVD Combo Player Combo DVD 5.1 Amplifier Home Theater System Computer Speaker System Game Machine 22µH VPOS 17 MUTE 1µF 35V 5 26 VPOS1 VNEGA R LIM VCOMA 27 VGND 4 FLAG 28 OUTREF2 Sychronize VPOSA 29 N.C. 3 30 N.C. 2 IN2M VPOS VCOM 31 IN1P 32 1 16 1µF Master / Slave 1µF MUTE / GAIN VCOM VNEGA LX1725 PACKAGE ORDER INFO TJ(°C) LQ Plastic MLPQ 32-PIN RoHS Compliant / Pb-free -40 to +85 LX1725ILQ Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX1725ILQ-TR) Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 1 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET ABSOLUTE MAXIMUM RATINGS PACKAGE PIN OUT N.C. N.C. OUTREF1 HIGAIN V5V VCOM 32 31 30 28 27 26 25 1 24 VCOMA 2 23 STBY VPOS1 SYNC 3 22 OUT1 FLAG 4 21 VNEG1 RILIM VREF 5 20 VNEG2 6 19 OUT2 COSC 7 18 VPOS2 VNEGA 8 17 MASTER 12 13 14 15 16 OUTREF2 VNEGA VGND MUTE IN2M THERMAL DATA 11 N.C. 10 N.C. 9 IN2P Note: Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of specified terminal. LQ 29 VPOSA WWW . Microsemi .C OM IN1P IN1M Supply Voltage (VPOS/VNEG, VPOSA/VNEGA)......................... -0.3V to ±15V or 30V Common Supply Voltage (VCOM, VCOMA)................................. -0.3V to ±15V or 30V Analog Supply Voltage (V5V)..........................................................................-0.3 to 7.0V Input Voltage (IN1P, IN1M, IN2P, IN2M).......................................................-0.3 to 7.0V Standby and Mute Voltage (STBY, MUTE).....................................................-0.3 to 7.0V Synchronization Input Voltage (MASTER, SYNC) .........................................-0.3 to 7.0V Operating Temperature ...............................................................................-40°C to +85°C Maximum Operating Junction Temperature ............................................................. 150°C Storage Temperature................................................................................... -65°C to 150°C Peak Package Solder Reflow Temp.(40 second maximum exposure) ......... 260°C (+0, -5) LQ PACKAGE (Top View) Center Pad is VNEG N.C. – No Internal Connection Plastic MLPQ 32-Pin THERMAL RESISTANCE-JUNCTION TO CASE, θJC 1.12°C/W 15.5°C/W THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA RoHS / Pb-free 100% Matte Tin Lead Finish Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. FUNCTIONAL PIN DESCRIPTION Name Description VPOSA Analog voltage sense for VPOS voltage. Needs to be protected from noise at VPOS1 and VPOS2. Connect to VPOS bus with appropriate filtering. For VPOSA – VNEGA less than 10V, the under voltage lockout circuit will keep the part in sleep mode. Typically 250µA is drawn at this pin. VCOMA Analog voltage sense for VCOM voltage. Typically 150µA is drawn at this pin. Bi-directional clock signal pin. In Master mode, this pin outputs the clock to other slave units. In Slave mode, this pin is a clock input. CMOS logic levels. FLAG Monitor point that indicates a fault has been detected. This pin goes high during the power on reset period, when current limiting is in effect, when the voltage at VPOS – VNEG is less than 10V or greater than 33V, when the V5V voltage is less than 4V, and when an over-temperature condition is detected. CMOS logic levels. RILIM A current limit-programming resistor should be connected between this pin and ground. A 50KΩ resistor will give a 3.75A current limit threshold. This pin may be connected to V5V in which case both current limiting protection and over-voltage protection will be disabled. VREF 2.25V reference voltage, used as a local “gnd” reference. Place a decoupling capacitor greater than 1µF between this pin and VGND. This pin will be prone to instability for capacitor values less than this. In applications where more several LX1725s are synchronized together, the VREF pins should all be tied together so that all units use a common VREF voltage. COSC Place a capacitor between this pin and VGND to generate the PWM triangle wave. A 125pF capacitor will give an oscillation frequency of about 373KHz. In Master mode, this pin serves as the output for the triangle wave. In Slave mode, this pin is an input. The total capacitance on this pin will determine the frequency of oscillation. Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page PACKAGE DATA SYNC 2 LX1725 TM 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION (CONTINUED) Description VNEGA Analog voltage sense for VNEG voltage. Needs to be protected from noise at VNEG1 and VNEG2. Typically, about 180µA is sourced out of this pin. IN2P Positive audio input for channel 2. The input signal should be AC-coupled into this pin. The DC bias voltage will be equal to VREF. The input impedance to VREF will be about 17Kohm. IN2M Negative audio input for channel 2. The input signal should be AC-coupled into this pin. The DC bias voltage will be equal to VREF. The input impedance to VREF will be about 17Kohm. OUTREF2 Negative feedback input pin for channel 2. Normally connected to VCOM. VGND Ground reference return for the analog +5V power supply. This supply is allowed to “float” between VNEG and VCOM. Typical current out of this pin is about 600µA. MUTE Tri-level control pin. When this pin is set to greater than V5V/2, the audio signal path is muted. For voltages between V5V/4 and V5V/2, the audio gain will be set to approximately 5V/V. This allows the “Low Gain” mode to be tested. For voltages less than V5V/4, the normal 10V/V gain is in place. MASTER VPOS2 OUT2 Quad-level control pin. This pin has three thresholds to enable Master/Slave and the “Quick” test mode. Quick mode forces the internal 65224 clock counter to be bypassed in order to speed-up production testing. Here is how the various modes are mapped: V @ Master Mode < V5V/4 Slave, Normal Mode < V5V/2, >V5V/4 Slave, Quick mode < 3*V5V/4, >V5V/2 Master, Quick mode > 3*V5V/4 Master, Normal mode Normally, this pin should be shorted to either V5V or GND. Positive voltage supply to channel 2’s output buffer. In a split supply system, this voltage will range between +5V up to +15V. In a single supply system, this voltage is allowed to be +10V up to +30V. Power supply de-coupling capacitance should be placed between VPOS2 and VNEG2. PWM output for channel 2. This pin drives the L-C low pass filter prior to driving the speaker. VNEG2 Negative voltage supply to channel 2’s output buffer. In a split supply system, this voltage will range between – 5V down to –15V. In a single supply system, this represents the 0V point. VNEG1 Negative voltage supply to channel 1’s output buffer. In a split supply system, this voltage will range between – 5V down to –15V. In a single supply system, this represents the 0V point. OUT1 VPOS1 PWM output for channel 1. This pin drives the L-C low pass filter prior to driving the speaker. Positive voltage supply to channel 1’s output buffer. In a split supply system, this voltage will range between +5V up to +15V. In a single supply system, this voltage is allowed to be +10V up to +30V. Power supply de-coupling capacitance should be placed between VPOS1 and VNEG1. STBY A logic high as this pin forces a zero current standby mode. CMOS logic levels. VCOM Mid-voltage supply for both channel 1 and channel 2. This voltage should be half way between VPOS and VNEG. De-coupling capacitance should be placed between this pin and both VPOS and VNEG. Copyright © 2004 Rev. 1.2, 2005-12-06 Analog +5V supply for the signal processing section. This pin is referenced to VGND. For voltages less than 4V, the under voltage lockout circuit will keep the part in sleep mode. De-coupling capacitance should be placed between this pin and VGND. Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page PACKAGE DATA V5V WWW . Microsemi .C OM Name 3 LX1725 TM 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® P RODUCTION D ATA S HEET FUNCTIONAL PIN DESCRIPTION (CONTINUED) Description HIGAIN High Gain mode control pin. If connected to V5V gives +6dB more gain. OUTREF1 Negative feedback input pin for channel 1, normally connected to VCOM. IN1M Negative audio input for channel 1. The input signal should be AC-coupled into this pin. The DC bias voltage will be equal to VREF. The input impedance to VREF will be about 17Kohm. IN1P Positive audio input for channel 1. The input signal should be AC-coupled into this pin. The DC bias voltage will be equal to VREF. The input impedance to VREF will be about 17Kohm. WWW . Microsemi .C OM Name PACKAGE DATA Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 4 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET Parameter ` Symbol FOSC Voltage Stability Temperature Stability VPOS/VNEG V5V Stand-By Current Operating Current GAIN High Gain Mode GHIGH Normal Gain ` ` ` ` ` ` ` LX1725 Typ Max 160 220 280 KHz 10 5 8 % % % Units Varies with COSC capacitor value, value shown is for default conditions. VPOS-VNEG = 12V to 30V TA = 0°C to 70°C TA = -40°C to 85°C POWER SUPPLY Supply Voltage ` Min OSCILLATOR Oscillator Frequency ` Test Conditions WWW . Microsemi .C OM ELECTRICAL CHARACTERISTICS Notes: Unless otherwise specified, the following specifications apply over the operating ambient temperature TA = -40 ~ +85°C°C except where otherwise noted (typical @ TA = 25°C) and the following test conditions: VPOS = +12V, VNEG = -12V, VGND = 0V, V5V = 5V, VCOM = 0V RILIM = 50Kohm, COSC = 220pF, RL = 8Ω. GNOM Low Gain GLOW Mute Gain OFFSET Output DC Offset INPUT STAGE Input Resistance Common Mode Voltage Common Mode Rejection Ratio OUTPUT STAGE GMUTE Voff VCOM to GND VNEG to GND @ Single Power Supply STBY Enable, TA = 25°C @ V5V STBY Disabled, MUTE Enabled @ V5V POUT = 4W, F = 1kHz, VMUTE = VGND, HIGAIN = V5V Pout=1W, F=1KHz, VMUTE = VGND, HIGAIN = VGND Pout=0.25W, F=1KHz, V5V / 4 < VMUTE < V5V / 2, HIGAIN = VGND Input 2Vpp, F=1KHz, VMUTE = V5V ±6 12 4.5 15 ±15 30 5.5 250 20 µA mA 18 22 26 V/V 9 11 13 V/V 4.5 Measured WRT VCOM ±12 24 5.0 V 5.5 6.5 V/V 0.01 0.045 V/V 100 170 mV 27 KΩ V dB RIN VCM CMRR Single-ended PFET On resistance RDSONp VPOS = 12V, VNEG = -12V, Ids = 0.2A 550 900 mΩ NFET On resistance RDSONn VPOS = 12V, VNEG = -12V, Ids = 0.2A 550 900 mΩ GBNT ** Any 4 out of 5 clock periods 3.75 4 Copyright © 2004 Rev. 1.2, 2005-12-06 2.29 60 VPOS – VNEG A 10 0.38 12 1 3.8 4 V 125 °C 150 °C Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 13.2 1.78 V V Page ELECTRICALS CURRENT LIMIT Current Limit Threshold Ith Pulse Qualification Count Icount VOLTAGE THRESHOLDS AT VPOS – VNEG Under Voltage Threshold Start Threshold Hysteresis UNDER VOLTAGE LOCK-OUT @ V5V Start Threshold Voltage THERMAL Thermal Gain Fold Back Junction Temperature Thermal shut off Junction Temperature 17 5 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET Parameter ` Symbol Test Conditions Min LX1725 Typ Max WWW . Microsemi .C OM ELECTRICAL CHARACTERISTICS (CONTINUED) Notes: Unless otherwise specified, the following specifications apply over the operating ambient temperature TA = -40 ~ 85°C except where otherwise noted (typical @ TA = 25°C) and the following test conditions: VPOS=+12V, VNEG=-12V, VGND = 0V, V5V = 5V, VCOM = 0V RILIM = 50Kohm, COSC = 220pF, RL=8Ω. Units MUTE / STBY / MASTER SECTION MUTE Threshold STBY Threshold STBY To Output Enable Master Threshold Mute Mode @ V5V = 5.0V Low Gain Mode @ V5V = 5.0V Normal Gain Mode @ V5V = 5.0V @ V5V = 5.0V After Power on Reset Pulse, Not Quick Mode Master, Not Quick Mode @ V5V = 5.0V Master, Quick Mode @ V5V = 5.0V Slave, Quick Mode @ V5V = 5.0V Slave, Not Quick Mode @ V5V = 5.0V 2.5 1.25 2.5 1.25 2.85 2.60 65536 3.75 2.50 1.25 3.75 2.50 1.25 V V Clocks V * RDSONP and RDSONN include all bond wires and pad resistance. ** GBNT – Guarantee by design and system, no test. ELECTRICALS Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 6 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET Parameter ` Symbol Test Conditions Min LX1725 Typ Max WWW . Microsemi .C OM SYSTEM MODULE CHARACTERISTICS Notes: Unless otherwise specified, the following specifications apply over the operating ambient temperature TA = 25°C except where otherwise noted and the following test conditions: VPOS=+12V, VNEG=-12V, VGND = 0V, V5V = 5V, VCOM = 0V RILIM = 50Kohm, COSC = 220pF, Output LC filter 47uH/0.68uF, RL=8Ω, Test equipment built-in BPF 10Hz~22KHz. Units AUDIO CHARACTERISTICS RL=8Ω PO Output Power Stereo Output Power BTL RL=4Ω PO RL=8Ω PO RL=8Ω Total Harmonic Distortion Stereo RL=4Ω Total Harmonic Distortion BTL RL=8Ω Power Efficiency RL=8Ω Power Efficiency RL=4Ω Channel Crosstalk THD+N THD+N THD+N η Stereo VXTALK BW HIGH Stage Gain MID GSYS LOW Mute Output VMUTE Signal to Noise Ratio Stereo SNR Output Noise Floor Stereo VN CURRENT LIMIT Current Limit Threshold VPOS/VNEG=±12V; THD+N < 10% 9 VPOS/VNEG=±12V; THD+N < 1% 12 VPOS/VNEG=±12V; THD+N < 10% 16 VPOS-VNEG=±12V; THD+N < 1% 25 VPOS/VNEG=±12V ;Pout=1W, FIN=1KHz 0.05 0.08 0.08 0.1 0.5 VPOS/VNEG=±12V ;Pout=1W, FIN=20~20KHz VPOS/VNEG=±12V ;Pout=1W, FIN=1KHz 0.3 VPOS/VNEG=±12V ;Pout=1W, FIN=20~20KHz 0.05 VPOS-VNEG=±12V;Pout=1W, FIN=1KHz % 0.08 0.3 VPOS/VNEG=±12V, Pout=Max, THD+N<1% 89 91 VPOS/VNEG=±12V, Pout=Max, THD+N<1% 80 85 % Pout=1W, F=1KHz -60 2 Pout=1W, F=20-20KHz RL=8Ω VIN=200mVrms, F=20Hz~20KHz 26 VIN=200mVrms, F=20Hz~20KHz 20 VIN=200mVrms, F=20Hz~20KHz 14 Input short, system muted, stereo -60 Input short, system muted, BTL -60 20-20KHz, non A-Weighted, 8Ω 85 20-20KHz, non A-Weighted, 4Ω 89 Input short, non A-Weighted @ 20-20KHz, 8Ω 400 Input short, non A-weighted @ 20-20KHz, 4Ω 300 3.75 ITH Pulse Qualification Count W 32 VPOS-VNEG=±12V; THD+N < 10% VPOS/VNEG=±12V ;Pout=1W, FIN=20~20KHz Stereo Audio Bandwidth 7 VPOS/VNEG=±12V; THD+N < 1% Any 4 out of 5 clock periods 4 dB 3 dB dB dB dB µVRMS 4.0 A cycles SUPPLY VOLTAGE LIMIT Under Voltage LockOut Split VUVLO Single VUVLO VPOS +5 VNEG -5 VPOS, VNEG tied to GND 10 V ELECTRICALS Note: Characteristics done by system module evaluation. Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET SIMPLIFIED BLOCK DIAGRAM WWW . Microsemi .C OM STBY V5V VREF OVP & OTP & UVLO & Reference VPOS VNEG FAULT FLAG SYNC COSC VPOS OSC High Side Driver MASTER Level Shift MUTE INM VCOM MUTE Mute + INP + ILIMITT - VPOS VNEG Timer - - + VREF RILIM + Fault + ILIMITB + EAOUT OUT + - VCOM VREF Level Shift VGND Low Side Driver VNEG + - VGND VCOM BLOCK DIAGRAM FB Figure 1 – Simplified Block Diagram (half of the circuit) Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 8 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET FUNCTION DESCRIPTION The suggested switching frequency is 250KHz SYNCHRONIZATION Two or more LX1725 oscillators can be configured for synchronous operation. One unit, the master, is programmed for the desired frequency with COSC as usual, also with the MASTER pin tied to V5V. The SYNC pin and the COSC pin of the slave units should be tied to the SYNC pin and the COSC pin of the master unit respectively. The MASTER pin of slave components is tied to GND. In this configuration, the SYNC pins of the slave units begin receiving instead of transmitting clock pulses. Also, the COSC pins quit driving the PWM capacitor in the slave units. Note that for optimum performance, all slave units should be located as close to the master unit as possible (Figure 2). SYNC V5V LX1725 (Master) Cosc Master WWW . Microsemi .C OM OSCILLATOR LX1725 has a fixed PWM modulation frequency, but it is programmable by using an external capacitor connected to COSC pin to GND. The switching frequency is approximately 235KHz with capacitor’s value 220pF. With the capacitor value given, the switching frequency can be calculated as follows: FOSC = 52000 / COSC FOSC in KHz, and COSC in pF. STBY Output PWM err amp 65536 clock cycles FLAG Figure 3 – Power-On-Reset Timing Sequence The MASTER pin, as mentioned in SYNCHRONIZATION, is for multi devices operation. It is also a Quad-level control pin with three thresholds to enable Master/Slave and the “Quick” test mode. Quick mode forces the internal 65536 clock counter to be bypassed in order to speed-up production testing; this is usually for factory production test purposes. V @ Master Mode < V5V/4 Slave, Normal Mode < V5V/2, >V5V/4 Slave, Quick mode < 3*V5V/4, >V5V/2 Master, Quick mode > 3*V5V/4 Master, Normal mode SYNC LX1725 (Slave) Cosc Master Figure 2 – Two Devices Synchronized Block Diagram V5V MUTE 14dB 2R 14dB MUTE DESCRIPTION POWER ON RESET (POR) At start up or upon recovery from a fault condition, an internal “hiccup” counter counts 65536 clock cycles before allowing the outputs to begin switching. See the POR timing sequence in Figure 3. GAIN SELECTION/MUTE The channel gain can be programmed between 26dB and 20dB by setting the HIGAIN pin to V5V or to GND. The MUTE pin is a Tri-level control pin for test purposes. When this pin is set to greater than V5V/2, the audio signal path is muted. For voltages between V5V/4 and V5V/2, the audio gain will be reduced by 6dB. This allows the “Low Gain” mode to be tested. For voltages less than V5V/4, the normal gain is in place (Figure 4). LX1725 (Master) R 20dB Figure 4 – Gain Selection Block Diagram Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 9 LX1725 TM ® 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL P RODUCTION D ATA S HEET FUNCTION DESCRIPTION(CONTINUED) WWW . Microsemi .C OM THERMAL PROTECTION When the junction temperature exceeds 125°C, the gain is reduced by 6dB (gain fold back) to reduce the output power and on-chip power dissipation., when the temperature drops below 110°C the gain will returns to normal. When the temperature exceeds 155°C OVER CURRENT LIMIT the outputs are shut off to force the output current to zero. Again, The LX1725 has built-in over circuit protection. The circuit works when the temperature drops below 130°C the outputs are allowed by monitoring the voltage drop across whichever power FET is to switch and normal operation resumes. active. When this voltage is greater than a certain threshold, an over-current condition is assumed. If this condition occurs during AUDIO INPUT five consecutive clock cycles, then the output transistors are For a high common mode rejection ratio and a maximum immediately disabled. The hiccup counter then counts 65536 clock flexibility in the application, the audio inputs are fully differential. cycles before allowing the outputs to begin switching again. By connecting the inputs anti-parallel the phase of one of the During this period the FLAG pin goes to HIGH to indicate a channels can be inverted, so that a load can be connected between system fault. A “hiccup” condition will be clearly audible if a the two output filters. In this case the system operates as a mono speaker is connected to the outputs. The threshold for the over- BTL amplifier and with the same loudspeaker impedance an current condition is set to 3.75A. approximately four times higher output power can be obtained. The over current circuit hiccup protection can be disabled by The input configuration for a mono BTL application is illustrated pulling the RILIM pin to V5V. in Figure 6. In the stereo single-ended configuration it is also recommended to connect the two differential inputs in anti-phase. UNDER VOLTAGE LOCK-OUT (UVLO) This has advantages for the current handling of the power supply at If the voltage drops below ±5V under dual supply operation or 10V low signal frequencies. under single supply operation, the under voltage lock out circuit is Vref activated and the LX1725 will enter the standby mode. This switch-off will be silent and without pop noise. It will be recovered IN1+ when the supply voltage rises above the threshold level. OUT1 The FLAG pin will go logic HIGH to indicate the system fault. A IN1similar circuit monitors V5V with a threshold of 4V. STAND BY Forcing the STBY pin high puts the LX1725 into a zero current sleep mode. The outputs enter a high impedance mode and all internal bias circuits are disabled. Vref IN2+ OUT2 IN2- LX1725 Figure 6 – Audio Input Block Diagram DESCRIPTION Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 10 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET TEST CIRCUIT SCHEMATIC WWW . Microsemi .C OM V5V V5V C6 0.1µF 35V R100 0 C7 1µF 35V IN1IN1+ V5V VCOM HIGAIN N.C. VPOSA VPOS OUTREF1 N.C. IN1P IN1N C8 1µF 35V VPOS STBY SYNC SYNC FLAG R1 25K FLAG LX1725 RILIM L2 47µH MASTER OUT2+ OUT2- VPOS MUTE N.C. N.C. IN2N IN2P C19 0.68µF 50V C106 C15 + 10µF 35V 0.1µF 35V VPOS2 VNEGA OUT1- VNEG OUT2 COSC OUT1+ C18 0.68µF 50V VNEG2 VGND C11 220pF VNEG VNEG1 VREF VNEGA + C12 1µF 35V C101 0.1µF 35V JP2 L1 47µH OUT1 OUTREF2 C100 0.1µF 35V C14 0.1µF + C103 35V 10µF 35V VPOS1 VCOMA JP1 STBY MASTER C9 1µF 35V IN2IN2+ C10 1µF 35V V5V VNEGA MUTE V5V R104 5K 1% Master V5V + C5 10µF 35V V5V AGND R106 3K 1% R103 6K 1% Master V5 VPOS VPOS C1 470µF 35V C3 0.1µF 35V C2 470µF 35V C4 0.1µF 35V R105 4K 1% PGND V5V VNEG R107 6K 1% R101 10K R102 10K VNEG STBY FLAG SYNC Figure 7 – Test Circuit Schematic (Stereo, Split Supply) APPLICATIONS Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 11 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET JP5 +5V JP3 JP4 VPOS +V GND GND VNEG -V OUT1- IN1- OUT1+ IN1+ IN1+ OUT1+ RL OUT1- GND LX1725 OUT2- IN2- OUT2+ IN2+ RL OUT2+ J2 System One IN1IN2- OUT2- IN2+ Audio Precision TB2 Audio Precision Power Supply TB1 J1 Dual Single AGND GND TB3 GND VCOM CTR NORM TB4 +5V Power Supply WWW . Microsemi .C OM STBY TEST SYSTEM SET-UP System One SQUK SNOR MQUK MNOR 20dB LX1725 Evaluation Module 14dB JP6 MUTE JP7 Oscilloscope Figure 8 – System Test Set-up TEST SYSTEM CONFIGURATION VPOS1 VCOM VPOS1 VCOM VCOMA 1k 1k VPOS VPOS Filterless Filterless BTL VNEG2 VNEG2 Filterless Logic VNEG1 & RL VNEG VNEG Filterless RL Logic RL RL LX1725 VGND VPOS VPOS2 VPOS2 VCOMA LX1725 VGND APPLICATIONS VNEG1 & RL Driver BTL RL Driver VPOS Figure 9 – System Test Configuration Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 12 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET THD+N VS POWER THD+N VS. POWER 10 100 8OHM Load, Fin=1KHz 10Hz~22KHz BPF 8OHM Load, Fin=1KHz 10Hz~22KHz BPF 24V WWW . Microsemi .C OM 100 ±12V 10 ±9V 18V 1 1 0.21647 0.1 0.059 % 29V 0.01 0.01 0.001 0.001 0.0001 60m 100m 200m 500m 1.025 1 4.181 5 2 10 20 ±14.5V 0.21647 0.1 0.059 % 0.0001 50 60m 100m 200m 500m 1.025 1 W THD+N VS POWER 100 50 4.181 5 2 10 20 50 W THD+N VS. POWER 100 50 4OHM Load, Fin=1KHz 10Hz~22KHz BPF 24V 10 10.9991 10 10.9991 4OHM Load, Fin=1KHz 10Hz~22KHz BPF ±12V ±9V 18V 1 0.59672 1 0.59672 29V 0.1 % 0.01 0.01 0.001 0.001 0.0001 60m 100m 200m 500m 1 2 5 10.23 1013.76 20 ±14.5V 0.1 % 0.0001 50 60m 100m 200m 500m 1 2 5 10.23 1013.76 20 50 W W THD+N VS POWER THD+N VS. POWER 100 100 8OHM Load, Fin=1KHz 10Hz~22KHz BPF, BTL ±12V 10 10 8OHM Load , Fin=1KHz 10Hz~22KHz BPF , BTL 24V 20V ±10V 1 1 % ±15V % 30V 0.1 0.1 CHARTS 0.01 0.01 0. 001 0. 001 60m Copyright © 2004 Rev. 1.2, 2005-12-06 200m 500m 1 2 W 5 10 20 50 100 60m 200m 500m 1 2 5 10 20 50 100 W Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 13 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET THD+N VS. FREQUENCY THD+N VS. FREQUENCY 8OHM Load, Po=1W 10Hz~22KHz BPF 10 10 20V 24V % ±12V % 8OHM Load , Po=1W 10Hz~22KHz BPF 1 ±10V 1 30V 0.1 0.1 WWW . Microsemi .C OM 100 dx=0.00000 Hz 100 ±15V 0. 01 0. 01 0. 001 20 0. 001 20 50 100 200 500 1k 2k 5k 50 100 200 10k 20k 500 1k 2k 5k 10k 20k Hz Hz THD+N VS. FREQUENCY 100 50 THD+N VS. FREQUENCY 100 dx=-4.0228 kHz 4OHM Load , Po=1W 10Hz~22KHz BPF 4OHM Load, Po=1W 10Hz~22KHz BPF 10 10 ±10V 1 ±12V % 1 20V 24V 0.1 30V % 0.1 ±15V 0. 01 0. 01 0. 001 20 50 100 200 500 1k 2k 5k 10k 20k 0. 001 20 50 100 200 1k 2k 5k 10k 20k Hz Hz THD+N VS. FREQUENCY THD+N VS. FREQUENCY 100 10 500 100 8OHM Load, Po=1W 10Hz~22KHz BPF , BTL 10 ±10V ±12V 1 8OHM Load , Po=1W 10Hz~22KHz BPF , BTL 20V 24V 1 % % 0.1 30V 0. 01 0. 001 20 0. 01 50 100 200 500 1k 2k 5k 10k 20k 0. 001 Hz Copyright © 2004 Rev. 1.2, 2005-12-06 CHARTS 0.1 ±15V 20 50 100 200 500 1k 2k 5k 10k 20k Hz Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 14 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET GAIN @ 20 – 20KHZ +28 GAIN @ 20 – 20KHZ + 30 8OHM Load , Vin=200mVrms 10Hz~80KHz BPF , +/-12V 4OHM Load , Vin=200mVrms 10Hz~80KHz BPF , +/-12V + 28 26dB +26 + 26 +24 + 24 26dB WWW . Microsemi .C OM +30 Note 1 + 22 +22 20dB +20 20dB + 20 + 18 +18 d +16 B +14 r +12 d + 16 B + 14 r + 12 14dB +10 + 10 +8 +8 +6 +6 14dB +4 +4 +2 +2 -0 -0 20 50 100 200 500 1k 2k 5k 10k 20k 80k 20 50 100 200 500 1k GAIN @ 20 – 20KHZ + 30 + 28 2k 5k 10k 20k 80k Hz Hz GAIN @ 20 – 20KHZ +30 8OHM Load , Vin=200mVrms 10Hz~80KHz BPF , 24V 4OHM Load, Vin=200mVrms 10Hz~80KHz BPF, 24V +27.5 26dB + 26 26dB +25 + 24 +22.5 + 22 20dB + 20 20dB +20 + 18 +17.5 d + 16 B + 14 r + 12 d B r 14dB + 10 +15 14dB +12.5 +10 +8 +6 +7.5 Note 2 +4 +5 +2 +2.5 0 20 50 100 200 500 1k 2k 5k 10k 20k 80k Hz +0 20 50 100 200 500 1k 2k 5k 10k 20k 80k Hz Note 1 – The output LC filter are based on 8OHM design, L=47uH, C=0.68uF, the 4OHM load LC filter design please refer to the application notes. Note 2 – At single supply mode, the output AC coupling capacitor value based on 470uF, for lower cut-off frequency, please refer to the application notes. CHARTS Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 15 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET IQQ VS. SUPPLY VOLTAGE DC OFFSET @SUPPLY WWW . Microsemi .C OM 90 20 70 18 50 30 16 10 -10 Offset Iqq (mA) 14 -30 -50 12 -70 10 -90 -110 8 -130 -150 6 6 6 7 8 9 10 11 12 13 14 8 10 15 12 14 16 Supply Voltage (+/-V) Supply (+/-V) CH1 IPOS IQQ (POS) VS. SW FREQUENCY IQQ (NEG) VS. SW FREQUENCY 30 30 25 25 +15 V 20 Iqq(mA) Iqq(mA) CH2 INEG +12 V 15 20 15 +15V +10 V +12V +10 V +8V 10 10 +6V 5 100 150 200 250 300 350 400 450 +8V 5 100 500 +6V 150 200 250 SW Frequency(Khz) EFFICIENCY @8OHM LOAD 90.00% 90.00% 1400 80.00% 1200 70.00% 60.00% 50.00% 600 40.00% 400 30.00% 20.00% 200 10.00% 0 0.00% 6 7 8 9 10 11 12 13 60.00% 1000 50.00% 800 40.00% 600 30.00% 400 20.00% 200 10.00% 0 0.00% 0.1 0.5 1 2 3 Power (W) Copyright © 2004 Rev. 1.2, 2005-12-06 INEG EFFICIENCY IPOS 4 5 6 7 8 Power (W) INEG Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 9 10 11 12 13 CHARTS IPOS 500 EFFICIENCY @4OHM LOAD 70.00% 800 5 450 1600 80.00% 4 400 100.00% Current (mA) Current (mA) 1000 2 3 350 SW Frequency(Khz) 1200 0.1 0.5 1 300 EFFICIENY Page 16 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET POWER VS. SUPPLY @8OHM POWER VS. SUPPLY @4OHM WWW . Microsemi .C OM 25 16 14 20 10 Power (W) Power (W) 12 8 6 15 10 4 5 2 0 0 6 7 8 9 10 11 12 13 14 15 6 7 8 9 Supply (+/-V) 10 11 1%THD 1%THD 12 13 14 15 Supply (+/-V) 10%THD 10%THD POWER VS. SUPPLY @8OHM BTL SW FREQUENCY VS. COSC 50 500 45 450 40 400 30 SW Freq (Khz) Power (W) 35 25 20 15 10 350 300 250 200 5 150 0 6 7 8 9 10 11 12 13 14 100 100 15 150 200 Supply (+/-V) 1%THD 250 300 350 400 CAP Value (pF) 10%THD NOISE FLOOR @20-20KHZ +0 +/-12V, Gain =20dB, input shorted 10~22KHz BPF , non A-Weighted -20 @8OHM, Noise V N= 400uVrms @4OHM, Noise V N= 290uVrms -40 d -60 B V -80 8OHM -100 CHARTS 4OHM -120 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 17 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET APPLICATION SCHEMATICS WWW . Microsemi .C OM HIGAIN +5V IN1P 4.7µF 35V 1µF VCOM IN1N 1µF 6 7 150 - 220pF VCOM V5V HIGAIN OUTREF1 VNEG1 LX1725 VNEG2 VREF OUT2 COSC VNEGA 9 IN2N N.C. FLAG VNEG IN2P N.C. OUT1 RILIM 10 11 12 13 14 VPOS2 15 STBY 24 VPOS STBY VPOS1 SYNC IN2P 8 25 MASTER 23 22 21 20 22µH 820nF VNEG 820nF 19 18 22µH VPOS 17 MUTE 1µF 35V 5 VCOMA 26 VGND 50K 27 VNEGA 4 FLAG 28 OUTREF2 3 Sychronize 29 N.C. VCOM VPOSA 30 N.C. 2 IN1M VPOS 31 IN2M 1 IN1P 32 16 1µF Master / Slave 1µF MUTE / GAIN VNEGA VPOS 0.1µF 50V Note: This design for Typical 4Ω load, other than 4Ω. Please refer to application notes AN-35 to change L.C. value APPLICATIONS 0.1µF 50V 470µF 35V 470µF 35V VNEG Figure 17 – Application Schematic (Stereo, Split Supply) Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 18 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET APPLICATION SCHEMATICS (CONTINUED) IN1P 4.7µF 35V +5V IN1P 4.7µF 35V 1µF WWW . Microsemi .C OM +5V HIGAIN VCOM VCOM IN1N VCOM IN1N 1µF 32 31 30 29 28 27 26 25 10 11 12 13 14 V5V VCOM N.C. HIGAIN OUTREF1 N.C. LX1725 VNEG2 VREF 10 11 12 13 VPOS2 14 VGND 15 VPOS MASTER 23 22 21 20 VNEG 19 18 VPOS 17 MUTE VNEGA VNEGA OUTREF2 OUT2 COSC 9 VPOS 16 IN1M OUT1 VNEG1 VNEG 820nF 17 MASTER 8 VPOS1 FLAG RILIM STBY 24 STBY SYNC N.C. 7 150 - 220pF 22µH 18 16 IN2P Master / Slave Master / Slave 1µF MUTE / GAIN IN2N 6 19 VPOS2 15 1µF 35V VNEG 5 VCOMA N.C. V5V VCOM N.C. HIGAIN N.C. OUTREF1 IN1P 9 IN2P IN1M VNEGA VNEG 50K 22µH 20 OUT2 COSC IN2P 8 VREF 4 FLAG 21 VNEG2 3 Sychronize 22 VPOSA IN2M 7 RILIM 820nF 23 VNEG1 LX1725 2 VCOM 24 OUT1 FLAG VPOS VPOS STBY SYNC 1 IN2P 6 150 - 220pF 25 VPOS1 VGND 1µF 35V 5 VCOMA 26 MUTE 50K 27 VNEGA 4 FLAG 28 OUTREF2 Sychronize VPOSA 29 N.C. 3 30 N.C. 2 IN2M 1 VPOS VCOM 31 IN1P STBY 32 MUTE / GAIN IN2N 1µF VNEGA VPOS 1.2K VCOM VNEGA VPOS 0.1µF 50V 1000µF 35V 1K VCOM Note: This design for Typical 4Ω load, other than 4Ω. Please refer to application notes AN-35 to change L.C. value 0.1µF 50V VNEG 0.1µF 50V 470µF 35V 470µF 35V VNEG Figure 18 – Application Schematic (Stereo, Single Supply) Figure 19 – Application Schematic (BTL, Split Supply) HIGAIN VCOM +5V IN1P 4.7µF 35V VCOM IN1N 7 8 V5V VCOM HIGAIN N.C. REFOUT1 N.C. IN1M 25 VPOS1 OUT1 FLAG VNEG1 LX1725 RILIM VNEG2 VREF OUT2 COSC VNEGA VNEG 9 10 11 12 13 14 VPOS2 15 STBY 24 VPOS STBY SYNC IN2P 150 - 220pF 26 MASTER 23 22 21 VNEG 20 19 18 VPOS 17 MUTE 6 VCOMA VNEGA 1µF 35V 5 27 VGND 50K 28 REFOUT2 4 FLAG VPOSA 29 N.C. 3 30 N.C. 2 VCOM Sychronize 31 IN2M 1 VPOS IN1P 32 16 IN2P APPLICATIONS Master / Slave MUTE / GAIN IN2N VCOM VNEGA VPOS 1.2 K VCOM 1K 0.1µF 50V 1000µF 35V VNEG Figure 20 – Application Schematic (BTL, Single Supply) Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 19 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET PCB DESIGN GUIDELINES DESIGN OF PCB LAND PATTERN FOR PACKAGE TERMINALS As a general rule, the PCB lead finger pad (Y) should be designed 0.2-0.5mm longer than the package terminal length for good filleting. The pad length should extend 0.05mm towards the centerline of the package. The pad width (X) should be a minimum 0.05mm wider than the package terminal width (0.025mm per side), refer to figure 21. However, the pad width is reduced to the width of the component terminal for lead pitches below 0.65mm. This is done to minimize the risk of solder bridging. WWW . Microsemi .C OM PCB DESIGN GUIDELINES One of the key efforts in implementing the MLP package on a pc board is the design of the land pattern. The MLP has rectangular metallized terminals exposed on the bottom surface of the package body. Electrical and mechanical connection between the component and the pc board is made by screen printing solder paste on the pc board and then reflowing the paste after placement. To guarantee reliable solder joints it is essential to design the land pattern to the MLP terminal pattern, exposed PAD, and Thermal PAD via. There are two basic designs for PCB land pads for the MLP: Copper Defined style (also known as Non Solder Mask Defined (NSMD)) and the Solder Mask Defined style (SMD). The industry has had some debate on the merits of both styles and although Microsemi recommends the Copper Defined style land pad (NSMD), both styles are acceptable for use with the MLP package. NSMD pads are recommended over SMD pads due to the tighter tolerance on copper etching than solder masking. NSDM by definition also provides a larger copper pad area and allows the solder to anchor to the edges of the copper pads thus providing improved solder joint reliability. EXPOSED PAD PCB DESIGN The construction of the Exposed Pad MLP enables enhanced thermal and electrical characteristics. In order to take full advantage of this feature the exposed pad must be physically connected to the PCB substrate with solder. The exposed pad is internally connected to the die substrate potential which is VNEG so it is very important that the PCB substrate potential be connected to VNEG as well. The thermal pad (D2th) should be greater than D2 of the MLP whenever possible; however adequate clearance (Cpl > 0.15mm) must be met to prevent solder bridging. If this clearance cannot be met, then D2th should be reduced in area. The formula would be: D2TH >D2 only if D2TH < Gmin - (2 x Cpl). THERMAL PAD VIA DESIGN There are two types of on-board thermal PAD designs: one is using thermal vias to sink the heat to the other layer with metal traces. Based on the Jedec Specification (JESD 51-5) the thermal vias should be designed like Figure 22. Another one is the no via thermal PAD which is using the same side copper PAD as heat sink, this type of thermal PAD is good for a two layer board, since the bottom side is filled with all other kinds of trace also, it’s hard to use the whole plane for the heat sink. But you still can use vias to sink the heat to the bottom layer by the metal traces, then layout a NMSD on which a metal heat sink is put to sink the heat to the air. Part 0.05mm Y2 Solder PCB Pad PCB 0.20mm Y1 (X1) Min: 0.025mm Per side for lead pitches > 0.65mm Land Pattern for Four Layer Board with Vias APPLICATIONS Micro Lead Quad Package Land Pattern Part Lead Figure 22 – Comparison of land pattern theory Figure 21 – PC Board Land Pattern Geometry for MLP Terminals Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 20 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET PCB DESIGN GUIDELINES (CONTINUED) Zmin= D + aaa + 2(0.2) (where pkg body tolerance aaa=0.15) (where 0.2 is outer pad extension) Gmin= D-2(Lmax)-2(0.05) (where 0.05 is inner pad extension) (Lmax=0.50 for this example) D2th max = Gmin-2(CpL) (where CpL=0.2) WWW . Microsemi .C OM The LX1725 is supplied in an MLPQ-7mmx7mm, 32 pin package. θJA =29.3°C/W for the package by itself in still air. When running at a continuous 20W output power, the on-chip power dissipation will be 3.5W assuming 85% efficiency. With no reduction in the thermal resistance, the die temperature will rise 103 above ambient. θJC is about 4°C/W. If the exposed pad is properly connected to a heat sink, then the temperature rise will be reduced to around 16°C under these condition. So the non-via type thermal PAD is suggested. ~0.85mm ~0.025mm Zmin ~7.45mm D2th ~5.15mm ~0.355mm 1.2mm Gmin ~6.00mm 0.305mm Ø 0.3mm 5.00mm Figure 23 – Recommended Land Pad with Vias for LQ32 (7mm²) APPLICATIONS Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 21 LX1725 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® TM P RODUCTION D ATA S HEET PACKAGE DIMENSIONS WWW . Microsemi .C OM LQ 32-Pin Package Description (Micro Lead Quad Package) D E2 b L D2 E e A A1 Dim A A1 A3 b D D2 E E2 e L MILLIMETERS MIN MAX 0.80 1.00 0 0.05 0.25 REF 0.23 0.38 7.00 BSC 5.00 5.25 7.00 BSC 5.00 5.25 0.65 BSC 0.45 0.65 INCHES MIN MAX 0.031 0.039 0 0.002 0.010 0.009 0.015 0.276 BSC 0.197 0.207 0.276 BSC 0.197 0.207 0.026 0.018 0.026 A3 Note: Dimensions do not include mold flash or protrusions; these shall not exceed 0.155mm(.006”) on any side. Lead dimension shall not include solder coverage. MECHANICALS Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 22 LX1725 TM 15W+15W Stereo Class-D Amplifier Filterless 30W Mono in BTL ® P RODUCTION D ATA S HEET NOTES WWW . Microsemi .C OM NOTES PRODUCTION DATA – Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. Copyright © 2004 Rev. 1.2, 2005-12-06 Microsemi Integrated Products Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 23