LANSDALE ML3356 Wideband fsk receiver Datasheet

ML3356
Wideband FSK Receiver
Legacy Device: Motorola MC3356
P DIP 20 = RP
PLASTIC PACKAGE
CASE 738
The ML3356 includes Oscillator, Mixer, Limiting IF Amplifier,
Quadrature Detector, Audio Buffer, Squelch, Meter Drive, Squelch
Status output, and Data Shaper comparator. The ML3356 is designed
for use in digital data communciations equipment.
• Data Rates up to 500 kilobaud
• Excellent Sensitivity: – 3 dB Limiting Sensitivity
30 µVrms @ 100 MHz
• Highly Versatile, Full Function Device, yet Few External Parts
are Required
• Down Converter Can be Used Independently — Similar to NE602
• Operating Temperature Range TA = –40° to +85°C
SO 20W = -6P
PLASTIC PACKAGE
CASE 751D
(SO–20L)
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SO 20W
MC3356P
MC3356DW
ML3356RP
ML3356-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Figure 1. Representative Block Diagram
RF
VCC
PIN CONNECTIONS
RF
Ground
1
20
2
19
3
18
OSC
4
Mixer
Data Shaping
Comparator
+
5
Ceramic
Filter
6
7
–
Ground
Data
Output
VCC
16
15
Comparator –
+
Meter Current
Limiter
17
RF
Input
14
Squelch
Status
Hysteresis
Buffer
8
13
9
12
10
11
Squelch
Adjust
(Meter)
RF Ground 1
20 RF Input
OSC Emitter 2
19 Ground
OSC Collector 3
18 Data Output
RF VCC 4
17 + Comparator
Mixer Output 5
16 – Comparator
IF VCC 6
15 Squelch Status
Limiter Input 7
14 Squelch Control
Limiter Bias 8
13 Buffered Output
Limiter Bias 9
12 Demodulator
Filter
Quad Bias 10
11 Quad Input
Quadrature Detector
Tank
VCC
Page 1 of 9
www.lansdale.com
Issue A
ML3356
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS
Rating
Power Supply Voltage
Symbol
Value
Unit
VCC(max)
15
Vdc
VCC
3.0 to 9.0
Vdc
RF VCC
3.0 to 12.0
Vdc
Operating Power Supply Voltage Range (Pins 6, 10)
Operating RF Supply Voltage Range (Pin 4)
Junction Temperature
TJ
150
°C
Operating Ambient Temperature Range
TA
– 40 to + 85
°C
Storage Temperature Range
Tstg
– 65 to + 150
°C
Power Dissipation, Package Rating
PD
1.25
W
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, fo = 100 MHz, fosc = 110.7 MHz, ∆f = ±75 kHz, fmod = 1.0 kHz, 50 Ω source,
TA = 25°C, test circuit of Figure 2, unless otherwise noted.)
Characteristics
Min
Typ
Max
Unit
Drain Current Total, RF VCC and VCC
–
20
25
mAdc
Input for – 3 dB limiting
–
30
–
µVrms
–
60
–
µVrms
2.5
–
–
v/v
Mixer Input Resistance, 100 MHz
–
260
–
Ω
Mixer Input Capacitance, 100 MHz
–
5.0
–
pF
Mixer/Oscillator Frequency Range (Note 1)
–
0.2 to 150
–
MHz
IF/Quadrature Detector Frequency Range (Note 1)
–
0.2 to 50
–
MHz
AM Rejection (30% AM, RF Vin = 1.0 mVrms)
–
50
–
dB
Demodulator Output, Pin 13
–
0.5
–
Vrms
Meter Drive
–
7.0
–
µA/dB
Squelch Threshold
–
0.8
–
Vdc
Input for 50 dB quieting
( S N+ N )
Mixer Voltage Gain, Pin 20 to Pin 5
NOTE: 1. Not taken in Test Circuit of Figure 2; new component values required.
Figure 2. Test Circuit
Squelch
Status
Demod
Out
Data Output
100 MHz
RF Input
3.0 k
0.1
0.01
390 k
20
RF Input
L1 – 110.7 MHz, 0.4 µH
L1 – 7T #22, 3/16 Form
L1 – w/slug & can
L2 – 10.7 MHz, 1.5 µH
L2 – 20T #30, 3/16 Form
L2 – w/slug & can
T1 – muRata
T1 – SFE10.7 MA5–Z
or
KYOCERA
T1 – KBF10.7MN–MA
3.3 k
18 k
10 k
0.01
51
19
18
Ground
Data
Output
3.3 k
17
Comp(+)
16
15
Comp(–)
14
Squelch
Status
Squelch
Control
470
pF
18 k
13
12
11
Demod
Out
Demod
Filter
Quad
Input
150 pF
L2
RF
Gnd
OSC
EM.
OSC
COL.
1
2
3
RF
VCC
4
Mixer
Out
Limiter
Input
VCC
6
5
Limiter
Bias
7
8
0.01
5.6 pF
Limiter
Bias
9
Quad
Bias
10
0.01
330
15 pF
VCC
L1
330
Page 2 of 9
130 k
47 k
47 k
T1
0.01
5 Vdc
www.lansdale.com
Issue A
ML3356
LANSDALE Semiconductor, Inc.
Figure 3. Output Components of Signal,
Noise, and Distortion
Figure 4. Meter Current versus Signal Input
10
700
S+N+D
METER CURRENT, PIN 14 (µA)
RELATIVE OUTPUT (dB)
0
fO = 100 MHz
fm = 1.0 kHz
∆f = ± 75 kHz
–10
–20
–30
N+D
–40
N
–50
–60
0.01
0.1
1.0
600
500
400
300
200
100
0
0.010
10
INPUT (mVrms)
GENERAL DESCRIPTION
This device is intended for single and double conversion
VHF receiver systems, primarily for FSK data transmission up
to 500 K baud (250 kHz). It contains an oscillator, mixer, limiting IF, quadrature detector, signal strength meter drive, and
data shaping amplifier.
The oscillator is a common base Colpitts type which can be
crystal controlled, as shown in Figure 1, or L–C controlled as
shown in figure 8. At higher VCC, it has been operated as
high as 200 MHz. A mixer/oscillator voltage gain of 2 up to
approximately 150 MHz, is readily achievable.
The mixer functions well from an input signal of 10 µVrms,
below which the squelch is unpredictable, up to about 10
mVrms, before any evidence of overload. Operation up to 1.0
Vrms input is permitted, but non–linearity of the meter output
is incurred, and some oscillator pulling is suspected. The AM
rejection above 10 mVrms is degraded.
The limiting IF is a high frequency type, capable of being
operated up to 50 MHz. It is expected to be used at 10.7 MHz
in most cases, due to the availability of standard ceramic resonators. The quadrature detector is internally coupled to the
IF, and a 5.0 pF quadrature capacitor is internally provided.
The –3dB limiting sensitivity of the IF itself is approximately
50 µV (at Pin 7), and the IF can accept signals up to 1.0 Vrms
without distortion or change of detector quiescent DC level.
The IF is unusual in that each of the last 5 stages of the 6
state limiter contains a signal strength sensitive, current sinking device. These are parallel connected and buffered to produce a signal strength meter drive which is fairly linear for IF
input signals of 10 µV to 100 mVrms (see Figure 4).
A simple squelch arrangement is provided whereby the
meter current flowing through the meter load resistance flips a
comparator at about 0.8 Vdc above ground. The signal
strength at which this occurs can be adjusted by changing the
Page 3 of 9
0.1
1.0
10
PIN 20 INPUT (mVrms)
100
1000
meter load resistor. The comparator (+) input and output are
available to permit control of hysteresis. Good positive action
can be obtained for IF input signals of above 30 µVrms. The
130 kΩ resistor shown in the test circuit provides a small
amount of hysteresis. Its connection between the 3.3k resistor
to ground and the 3.0 k pot, permits adjustment of squelch
level without changing the amount of hysteresis.
The squelch is internally connected to both the quadrature
detector and the data shaper. The quadrature detector output,
when squelched, goes to a DC level approximately equal to the
zero signal level unsquelched. The squelch causes the data
shaper to produce a high (VCC) output.
The data shaper is a complete ‘‘floating’’ comparator, with
back to back diodes across its inputs. The output of the quadrature detector can be fed directly to either input of this amplifier to produce an output that is either at VCC or VEE,
depending upon the received frequency. The impedance of the
biasing can be varied to produce an amplifier which “follows”
frequency detuning to some degree, to prevent data pulse
width changes.
When the data shaper is driven directly from the demodulator output, Pin 13, there may be distortion at Pin 13 due to the
diodes, but this is not important in the data application. A useful note in relating high/low input frequency to logic state: low
IF frequency corresponds to low demodulator output. If the
oscillator is above the incoming RF frequency, then high RF
frequency will produce a logic low (input to (+) input of Data
Shaper as shown in Figures 1 and 2).
APPLICATION NOTES
The ML3356 is a high frequency/high gain receiver that
requires following certain layout techniques in designing a stable circuit configuration. The objective is to minimize or eliminate, if possible, any unwanted feedback.
www.lansdale.com
Issue A
ML3356
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 5. Application with Fixed Bias on Data Shaper
Car. Det. Out
Data Out
5.0 V
0 V or 4.0 V
18 k
3.3 k
15 k
130 k
RF In
1:2
10 k
0.01
3.0 k
20
19
18
RF Input
Ground
Data
Output
470
pF
0.1
10 k
3.3 k
390 k
17
16
Comp(+)
Comp(–)
15
Squelch
Status
18 k
14
13
12
11
Squelch
Control
Demod
Out
Demod
Filter
Quad
Input
150 pF
ML3356
5.0 V
RF
Gnd
OSC
EM.
1
2
15 pF
OSC
COL.
RF
VCC
4
3
5.6 pF
fO
Mixer
Out
5
0.01
4.0 V
Limiter
Input
Limiter
Bias
7
0.1
0.01
330
Limiter
Bias
8
330
0.01
Bead
+ 5.0 to + 12 V
VCC
6
9
Quad
Bias
10
0.01
0.01
Bead
0.1
Cer. Fil.
10.7 MHz
180
82
APPLICATION NOTES (continued)
Shielding, which includes the placement of input and output
components, is important in minimizing electrostatic or electromagnetic coupling. The ML3356 has its pin connections
such that the circuit designer can place the critical input and
output circuits on opposite ends of the chip. Shielding is normally required for inductors in tuned circuits.
The ML3356 has a separate VCC and ground for the RF and
IF sections which allows good external circuit isolation by
minimizing common ground paths.
Note that the circuits of Figures 1 and 2 have RF, Oscillator,
and IF circuits predominantly referenced to the plus supply
rails. Figure 5, on the other hand, shows a suitable means of
ground referencing. The two methods produce identical results
when carefully executed. It is important to treat Pin 19 as a
ground node for either approach. The RF input should be
‘‘grounded’’ to Pin 1 and then the input and the mixer/oscillator grounds (or RF VCC bypasses) should be connected by a
Page 4 of 9
low inductance path to Pin 19. IF and detector sections should
also have their bypasses returned by a separate path to Pin 19.
VCC and RF VCC can be decoupled to minimize feedback,
although the configuration of Figure 2 shows a successful
implementation on a common 5.0 V supply. Once again, the
message is: define a supply node and a ground node and return
each section to those nodes by separate, low impedance paths.
The test circuit of Figure 2 has a 3 dB limiting level of 30
µV which can be lowered 6 db by a 1:2 untuned transformer at
the input as shown in Figures 5 and 6. For applications that
require additional sensitivity, an RF amplifier can be added,
but with no greater than 20 db gain. This will give a 2.0 to 2.5
µV sensitivity and any additional gain will reduce receiver
dynamic range without improving its sensitivity. Although the
test circuit operates at 5.0 V, the mixer/oscillator optimum performance is at 8.0 V to 12 V. A minimum of 8.0 V is recommended in high frequency applications (above 150 MHz), or in
PLL applications where the oscillator drives a prescaler.
www.lansdale.com
Issue A
ML3356
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Figure 6. Application with Self–Adjusting Bias on Data Shaper
Data
Out
5.0 V
Car. Det. Out
0 V or 4.0 V
130 k
3.3 k
1
15 k
47 k
RF In
47 k
10 k
0.01
3.3 k
1:2
470 k
20
19
18
RF Input
Ground
Data
Output
470
pF
0.1
470 pF
17
Comp(+)
16
15
Comp(–) Squelch
Status
18 k
0.1
14
Squelch
Control
13
12
11
Demod
Out
Demod
Filter
Quad
Input
f = 10.7
150 pF
1.5 µH
APPLICATION NOTES (continued)
Depending on the external circuit, inverted or noninverted
data is available at Pin 18. Inverted data makes the higher frequency in the FSK signal a “one” when the local oscillator is
above the incoming RF. Figure 5 schematic shows the comparator with hysteresis. In this circuit the DC reference voltage at Pin 17 is about the same as the demodulated output
voltage (Pin 13) when no signal is present. This type circuit is
preferred for systems where the data rates can drop to zero.
Some systems have a low frequency limit on the data rate,
such as systems using the MC3850 ACIA that has a start or
Page 5 of 9
stop bit. This defines the low frequency limit that can appear
in the data stream. Figure 5 circuit can then be changed to a
circuit configuration as shown in Figure 6. In Figure 6 the reference voltage for the comparator is derived from the demodulator output through a low pass circuit where τ is much lower
than the lowest frequency data rate. This and similar circuits
will compensate for small tuning changes (or drift) in the
quadrature detector.
Squelch status (Pin 15) goes high (squelch off) when the
input signal becomes greater than some preset level set by the
resistance between Pin 14 and ground. Hysteresis is added to
the circuit externally by the resistance from Pin 14 to Pin 15.
www.lansdale.com
Issue A
Page 6 of 9
www.lansdale.com
19
8
9
7
6
1
20
2
3
4
13
1.0 k
2
14
135
59
5.0 k
1.0 k
1.0 k
58
15
1.0 k
5.0 k
1. 0 k
3
1.0 k
135
5
9
60
1.0 k
330
6
57
17
1.0 k
5.0 k
1.0 k
16
4
13 5
18
1.0 k
3 30
7
61
19
1.0 k
10
8
5
56
135
20
1.0 k
20 pF
1.0 k
1.0 k
62
14
55
21
1.0 k
12
11
5.0 k
135
22
50 k
66
71
63
1 .0 k
69
64
72
1.0 k
1.0 k
68
20 k
20 k
24
67
135
10 k
54
23
1.0 k
50 k
1.0 k
65
5.0 k
25
20 k
73
10 k
27
70
26
15
10 k
28
10 k
10 k
35
75
5.0 pF
11
Figure 7. Internal Schematic
10 k
31
1.0 k
76
29
500
32
53
1.0 k
33
135
81
77
2.0 k
30
10
83
17
10 k
34
84
85
87
86
36
37
41
42
40
89
38
78
2.0 k
43
44
91
52
34
45
46
13
12
82
51
39
92
135
1.0 k
79
2.0 k
50
225
48
90
16
93
80
2.0 k
49
47
2.5 k
94
18
ML3356
LANSDALE Semiconductor, Inc.
Issue A
ML3356
LANSDALE Semiconductor, Inc.
RF IN
P1
C6
15pF
C5
47pF
dataout
C4 1nF
R1 R2
10k 330k
L2
1uH
R3
18k
130k R5 3.3k
R11
10k 40%
C12
R12
.1uF
U1
R14
15k
R15
18k
L3
1uH
C10
.01uF
C8 470pF
C7
150pF
C9
.01uF
V2
5V
+V
U2
C20
.1uF
R8
10k
R7
2.7k
C19
.1uF
V4
5V
+V
J2
SPI
Loop
Filter
cardet
P20 rfin
P19 gnd
P18 dataout
P17 comp+
P16 compP15 sqstatus
P14 sqctrl
P13 bufout
P12 demfil
P11 quadin
R13
3.3k
C1
47pf
330
C11
.01uF
R17
cerfil
U3
R10
10k
C2 10pf
+V
gnd P1
oscemit P2
osccol P3
rfvcc P4
mixout P5
ifvcc P6
limin 7
limbias P
P8
limbias P9
quadbias P10
L1
1uH
R16
330
C21
10pF
D2
MV209
R9
3.3k
C16
27pF
P16Vdd
P15 phsV
P14phsR
P13PDout
P12Vss
P11 LD
P10 Fv
P9 Fr
VCO
C3
.1uF
V3
5V
C15
.1uF +V
XTAL2
1.000MHZ
1Meg
R6
C17
27pF
oscin 1
oscoutP
P2
REFoutP3
Fin P4
Din P5
enb P6
clk P7
DoutP8
R4
10k
5V
V1
C18
1nF
MC145170
ML3356_
Figure 8
Typical Application using a PLL with L.O. less than 185 MHz.
Figure 8 shows a typical application using the MC145170/ML145170 PLL device. The PLL allows the L.O. to be used as a
VCO thus allowing multi - channel operation.
Page 7 of 9
www.lansdale.com
Issue A
ML3356
LANSDALE Semiconductor, Inc.
RF IN
P1
C6
15pF
C5
47pF
dataout
C4 1nF
R1 R2
10k 330k
L2
1uH
R3
18k
130k R5 3.3k
R11
10k 40%
C12
R12
.1uF
U1
R14
15k
R15
18k
L3
1uH
C10
.01uF
C8 470pF
C7
150pF
C9
.01uF
V2
5V
+V
U2
C20
.1uF
R8
10k
R7
2.7k
C19
.1uF
V4
5V
+V
J2
SPI
Loop
Filter
cardet
P20 rfin
P19 gnd
P18 dataout
P17 comp+
P16 compP15 sqstatus
P14 sqctrl
P13 bufout
P12 demfil
P11 quadin
R13
3.3k
C1
47pf
330
C11
.01uF
R17
cerfil
U4
R10
10k
C2 10pf
+V
gnd P1
oscemit P2
osccol P3
rfvcc P4
mixout P5
ifvcc P6
limin P7
limbias P
8
limbias P9
quadbias P10
L1
1uH
R16
330
C21
10pF
D2
MV209
R9
3.3k
C16
27pF
P16 phsR
P15 phsP
P14 Fout
P13 BISW
P 1 2 FC
P 1 1 LE
P10data
P9 clk
C3
.1uF
V3
5V
C15
.1uF +V
XTAL2
1.000MHZ
1Meg
C17R6
27pF
Oscin P1
Oscout P2
Vp P3
Vcc P4
DoP5
gnd P6
LD P 7
Fin P8
VCO
R4
10k
5V
V1
C18
1nF
ML12202
ML3356_
Figure 9
Typical Application using a PLL with L.O. greater than 185 MHz.
Figure 9 shows a typical application using the ML12202 PLL device. The PLL (ML12202) allows the L.O. to be used as a
VCO thus allowing multli-channel operation.
Page 8 of 9
www.lansdale.com
Issue A
ML3356
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML3356RP)
PLASTIC PACKAGE
CASE 738–03
–A
–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION “L” TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION “B” DOES NOT INCLUDE MOLD
FLASH.
5. 738–02 OBSOLETE, NEW STANDARD 738–03.
B
C
–T–
L
K
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
M
T
A
M
SO 20 = -6P
(ML3356-6P)
PLASTIC PACKAGE
CASE 751D–03
(SO–20L)
11
1
10
–B
–
0.25 (0.010)
P
M
B
M
10 PL
G
R X 45°
C
–T–
SEATING
PLANE
M
K
D 20 PL
0.25 (0.010)
M
T
B
S
A
F
T B
M
MILLIMETERS
MIN
MAX
25.66 27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0°
15°
1.01
0.51
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
0°
15°
0.020 0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. 751D–01, AND –02 OBSOLETE, NEW STANDARD
751D–03.
–A
–
20
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
J
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65 12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
0.010 0.012
0.004 0.009
7°
0°
0.395 0.415
0.010 0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 9 of 9
www.lansdale.com
Issue A