AD OP281 Ultralow power, rail-to-rail output operational amplifier Datasheet

Ultralow Power, Rail-to-Rail Output
Operational Amplifiers
OP281/OP481
FEATURES
Low Supply Current: 4 ␮A/Amplifier Max
Single-Supply Operation: 2.7 V to 12 V
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Offset Voltage: 1.5 mV
No Phase Reversal
APPLICATIONS
Comparator
Battery-Powered Instrumentation
Safety Monitoring
Remote Sensors
Low Voltage Strain Gage Amplifiers
GENERAL DESCRIPTION
The OP281 and OP481 are dual and quad ultralow power, singlesupply amplifiers featuring rail-to-rail outputs. Each operates
from supplies as low as 2.0 V and are specified at +3 V and +5 V
single supply as well as ± 5 V dual supplies.
Fabricated on Analog Devices’ CBCMOS process, the
OP281/OP481 features a precision bipolar input and an output
that swings to within millivolts of the supplies and continues to
sink or source current all the way to the supplies.
PIN CONFIGURATIONS
8-Lead SOIC
(R Suffix)
OUT A
–IN A
+IN A
V–
1
8
OP281
4
5
V+
1
OUT B
–IN B
+IN B
4
14-Lead
Narrow-Body SOIC
(R Suffix)
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
1
14
OP481
7
8
8-Lead TSSOP
(RU Suffix)
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
8
OP281
5
14-Lead TSSOP
(RU Suffix)
1
14
OP481
7
8
NOTE: PIN ORIENTATION IS EQUIVALENT FOR
EACH PACKAGE VARIATION
Applications for these amplifiers include safety monitoring,
portable equipment, battery and power supply control, and
signal conditioning and interfacing for transducers in very low
power systems.
The output’s ability to swing rail-to-rail and not increase supply
current, when the output is driven to a supply voltage, enables
the OP281/OP481 to be used as comparators in very low power
systems. This is enhanced by their fast saturation recovery time.
Propagation delays are 250 ms.
The OP281/OP481 are specified over the extended industrial
temperature range (–40∞C to +85∞C). The OP281 dual amplifier
is available in 8-lead SOIC surface-mount and TSSOP packages.
The OP481 quad amplifier is available in narrow 14-lead SOIC
and TSSOP packages.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
OP281/OP481–SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (@ V = 3.0 V, V
S
CM
= 1.5 V, TA = 25ⴗC, unless otherwise noted.*)
Parameter
Symbol
Condition
INPUT CHARACTERISTICS
Offset Voltage
VOS
Note 1
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +85∞C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
IB
IOS
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
⌬VOS /DT
⌬IB /DT
⌬IOS /DT
OUTPUT CHARACTERISTICS
Output Voltage High
CMRR
VOH
Output Voltage Low
VOL
Short Circuit Limit
ISC
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Turn On Time
Turn On Time
Saturation Recovery Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
PSRR
ISY
SR
VCM = 0 V to 2.0 V,
–40∞C £ TA £ +85∞C
RL = 1 MW, VO = 0.3 V to 2.7 V
–40∞C £ TA £ +85∞C
RL = 100 kW to GND,
–40∞C £ TA £ +85∞C
RL = 100 kW to V+,
–40∞C £ TA £ +85∞C
VS = 2.7 V to 12 V,
–40∞C £ TA £ +85∞C
VO = 0 V
–40∞C £ TA £ +85∞C
Typ
3
0.1
0
65
5
2
2.925
Unit
1.5
2.5
10
7
2
mV
mV
nA
nA
V
95
13
10
20
2
dB
V/mV
V/mV
mV/∞C
pA/∞C
pA/∞C
2.96
V
25
± 1.1
76
Max
95
3
75
4
5
mV
mA
dB
mA
mA
RL = 100 kW, CL = 50 pF
AV = 1, VO = 1
AV = 20, VO = 1
25
40
50
65
95
70
V/ms
ms
ms
ms
kHz
Degrees
0.1 Hz to 10 Hz
f = 1 kHz
10
75
<1
mV p-p
nV/÷Hz
pA/÷Hz
GBP
␾o
en p-p
en
in
Min
*VOS is tested under a no load condition.
Specifications subject to change without notice.
–2–
REV. B
OP281/OP481
ELECTRICAL SPECIFICATIONS (@ V = 5.0 V, V
S
CM
= 2.5 V, TA = 25ⴗC, unless otherwise noted.*)
Parameter
Symbol
Condition
INPUT CHARACTERISTICS
Offset Voltage
VOS
Note 1
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +85°C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
IB
IOS
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
⌬VOS /DT
⌬IB /DT
⌬IOS /DT
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
Short Circuit Limit
ISC
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Saturation Recovery Time
Gain Bandwidth Product
Phase Margin
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
PSRR
ISY
SR
VCM = 0 V to 4.0 V,
–40°C ≤ TA ≤ +85°C
RL = 1 MΩ, VO = 0.5 V to 4.5 V
–40°C ≤ TA ≤ +85°C
–40°C to +85°C
RL = 100 kΩ to GND,
–40°C ≤ TA ≤ +85°C
RL = 100 kΩ to V+,
–40°C ≤ TA ≤ +85°C
VS = 2.7 V to 12 V,
–40°C ≤ TA ≤ +85°C
VO = 0 V
–40°C ≤ TA ≤ +85°C
Max
Unit
0.1
1.5
2.5
10
7
4
mV
mV
nA
nA
V
3
0.1
4.925
90
15
10
20
2
dB
V/mV
V/mV
µV/°C
pA/°C
pA/°C
4.96
V
25
± 3.5
76
95
3.2
75
4
5
mV
mA
dB
µA
µA
27
120
100
74
V/ms
µs
kHz
Degrees
0.1 Hz to 10 Hz
f = 1 kHz
10
75
<1
µV p-p
nV/√Hz
pA/√Hz
GBP
␾o
en p-p
en
in
65
5
2
RL = 100 kΩ, CL = 50 pF
*VOS is tested under a no load condition.
Specifications subject to change without notice.
REV. B
Typ
0
CMRR
Output Voltage Low
POWER SUPPLY
Power Supply Rejection Ratio
Min
–3–
OP281/OP481
ELECTRICAL SPECIFICATIONS (@ V = ⴞ5.0 V, T = +25ⴗC, unless otherwise noted.*)
S
A
Parameter
Symbol
Condition
INPUT CHARACTERISTICS
Offset Voltage
VOS
Note 1
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +85∞C
–40∞C £ TA £ +85∞C
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection
IB
IOS
Large Signal Voltage Gain
AVO
Offset Voltage Drift
Bias Current Drift
Offset Current Drift
⌬VOS /DT
⌬IB /DT
⌬IOS /DT
OUTPUT CHARACTERISTICS
Output Voltage Swing
Short Circuit Limit
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
CMRR
VO
ISC
PSRR
ISY
Min
Max
Unit
0.1
1.5
2.5
10
7
+4
mV
mV
nA
nA
V
3
0.1
–5
VCM = –5.0 V to +4.0 V,
–40∞C £ TA £ +85∞C
RL = 1 MW, VO = ± 4.0 V,
–40∞C £ TA £ +85∞C
–40∞C to +85∞C
65
5
2
RL = 100 kW to GND,
–40∞C £ TA £ +85∞C
VS = ± 1.35 V to ± 6 V,
–40∞C £ TA £ +85∞C
VO = 0 V
–40∞C £ TA £ +85∞C
Typ
95
13
10
20
2
dB
V/mV
V/mV
mV/∞C
pA/∞C
pA/∞C
± 4.925
± 4.98
12
V
mA
76
95
3.3
5
6
dB
mA
mA
DYNAMIC PERFORMANCE
Slew Rate
Gain Bandwidth Product
Phase Margin
± SR
GBP
␾o
RL = 100 kW, CL = 50 pF
28
105
75
V/ms
kHz
Degrees
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Voltage Noise Density
Current Noise Density
en p-p
en
en
in
0.1 Hz to 10 Hz
f = 1 kHz
f = 10 kHz
10
85
75
<1
mV p-p
nV/÷Hz
nV/÷Hz
pA/÷Hz
*VOS is tested under a no load condition.
Specifications subject to change without notice.
–4–
REV. B
OP281/OP481
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . GND to VS + 10 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ± 3.5 V
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Junction Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
Model
Temperature
Range
Package
Description
Package
Option
OP281GS
OP281GRU
OP481GS
OP481GRU
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
8-Lead SOIC
8-Lead TSSOP
14-Lead SOIC
14-Lead TSSOP
R-8
RU-8
R-14
RU-14
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposures to absolute maximum rating
conditions for extended periods may affect device reliability.
Package Type
␪JA*
␪JC
Unit
8-Lead SOIC (R)(S)
8-Lead TSSOP (RU)
14-Lead SOIC (R)(S)
14-Lead TSSOP (RU)
158
240
120
240
43
43
36
43
∞C/W
∞C/W
∞C/W
∞C/W
*qJA is specified for the worst-case conditions, i.e., qJA is specified for device
soldered in circuit board for TSSOP and SOIC packages.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
OP281/OP481 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
OP281/OP481–Typical Performance Characteristics
50
VS = 2.7V
TA = 25ⴗC
40
35
QUANTITY – Amplifiers
30
25
20
15
10
35
30
25
20
15
10
5
5
0
0
–1.0 –0.8 –0.6–0.4 –0.2
0
0.2 0.4 0.6 0.8 1.0
–1.0 –0.8 –0.6–0.4 –0.2
INPUT OFFSET VOLTAGE – mV
–2.5
–3.0
–3.5
–4.0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–5.0
–40 –20
–3.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COMMON-MODE VOLTAGE – V
20 40 60 80 100 120
TEMPERATURE – ⴗC
TPC 4. Input Bias Current
vs. Temperature
800
600
400
200
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
OUTPUT VOLTAGE – mV
100
SOURCE
SINK
1.0
1000
TPC 7. Output Voltage to
Supply Rail vs. Load Current
20 40 60 80 100 120
TEMPERATURE – ⴗC
VS = 5V
TA = +25ⴗC
100
SOURCE
10
SINK
1.0
0.1
0
1,000
VS = 5V
TA = 25ⴗC
1,000
20 40 60 80 100 120
TEMPERATURE – ⴗC
TPC 6. Input Offset Current
vs. Temperature
1,000
VS = 3V
TA = 25ⴗC
10
100
LOAD CURRENT – µA
0
VS = 5V
–0.4
–40 –20
TPC 5. Input Bias Current
vs. Common-Mode Voltage
10,000
OUTPUT VOLTAGE – mV
0.0
–4.5
1
1000
0.4
INPUT OFFSET CURRENT – nA
INPUT BIAS CURRENT – nA
INPUT BIAS CURRENT – nA
–2.0
0.1
1200
0.5
VS = 5V
TA = 25ⴗC
0.5
VS = 5V
–1.5
10
1400
TPC 3. Input Offset Voltage
vs. Temperature
1.0
0
VS = 5V
0
–40 –20
0.2 0.4 0.6 0.8 1.0
TPC 2. Input Offset Voltage
Distribution
0
–1.0
0
1600
INPUT OFFSET VOLTAGE – mV
TPC 1. Input Offset Voltage
Distribution
–0.5
1800
OUTPUT VOLTAGE – mV
QUANTITY – Amplifiers
2000
VS = 5V
TA = 25ⴗC
45
INPUT OFFSET VOLTAGE – µV
45
40
1
10
100
LOAD CURRENT – µA
1000
TPC 8. Output Voltage to
Supply Rail vs. Load Current
–6–
100
SOURCE
10
SINK
1.0
0.1
1
10
100
LOAD CURRENT – µA
1000
TPC 9. Output Voltage to
Supply Rail vs. Load Current
REV. B
OP281/OP481
45
20
90
10
135
0
180
–10
225
–20
270
1k
10k
100k
FREQUENCY – Hz
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
1M
TPC 10. Open-Loop Gain
and Phase vs. Frequency
1k
10k
100k
FREQUENCY – Hz
40
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
1M
60
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
100
10k
100k
FREQUENCY – Hz
1k
80
60
50
0
–10
–20
100
40
30
60
40
20
10
0
0
–20
10k
100k
1M
FREQUENCY – Hz
10M
TPC 16. CMRR vs. Frequency
REV. B
–40
10
4k
6k
FREQUENCY – Hz
8k
10k
50
80
20
2k
TPC 15. Voltage Noise Density
vs. Frequency
100
VS = +3V
0
1M
VS = 5V, +5V, +3V, +2.7V
TA = +25ⴗC
RL = INFINITE
120
–10
1k
1k
10k
100k
FREQUENCY – Hz
160
140
VS = +5V
70
10
TPC 14. Closed-Loop Gain vs.
Frequency
TA = +25ⴗC
VS = 5V
20
–40
10
PSRR – dB
90
30
–30
1M
TPC 13. Open-Loop Gain
and Phase vs. Frequency
40
1M
50nV/ Hz/Div
0
CLOSED-LOOP GAIN – dB
40
PHASE SHIFT – Degrees
50
10k
100k
FREQUENCY – Hz
VS = 5V
TA = 25ⴗC
MARKER @ 67nV/ Hz
VS = 5V
TA = 25ⴗC
RL = INFINITE
50
100
1k
10k
100k
FREQUENCY – Hz
TPC 17. PSRR vs. Frequency
–7–
1M
SMALL SIGNAL OVERSHOOT – %
VS = 5V
TA = +25ⴗC
RL = 100k⍀ TO GROUND
60
1k
TPC 12. Open-Loop Gain
and Phase vs. Frequency
TPC 11. Open-Loop Gain
and Phase vs. Frequency
70
OPEN-LOOP GAIN – dB
50
40
OPEN-LOOP GAIN – dB
30
VS = 2.7V
TA = 25ⴗC
RL = 100k⍀
60
PHASE SHIFT – Degrees
0
OPEN-LOOP GAIN – dB
50
40
–30
100
VS = 3V
TA = 25ⴗC
RL = 100k⍀
60
PHASE SHIFT – Degrees
OPEN-LOOP GAIN – dB
50
CMRR – dB
70
70
VS = 5V
TA = 25ⴗC
RL = 100k⍀
60
45
40
VS = +5V
VIN = 50mV
RL = 100k⍀
TA = +25ⴗC
–OS
35
+OS
30
25
20
15
10
5
0
10
100
CAPACITANCE – pF
1000
TPC 18. Small Signal Overshoot
vs. Load Capacitance
PHASE SHIFT – Degrees
70
OP281/OP481
VS = 5V
VIN = 4V p-p
RL = INFINITE
TA = 25ⴗC
3
2
1
100
1k
10k
FREQUENCY – Hz
SUPPLY CURRENT/AMPLIFIER – ␮A
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 –20
0
20 40 60 80 100 120
TEMPERATURE – ⴗC
TPC 22. Supply Current/Amplifier
vs. Temperature
A2
100
90
0mV
VS = 1.35V
AV = 1
RL = 100k⍀
CL = 50pF
TA = +25ⴗC
1
100
1k
10k
FREQUENCY – Hz
3.50
3.25 TA = 25ⴗC
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE – ⴞV
TPC 23. Supply Current/Amplifier
vs. Supply Voltage
A2
VS = 5V
AV = 1
RL = 100k⍀
CL = 50pF
TA = 25ⴗC
2.50V
100
90
VS = 3V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40 –20
100k
TPC 20. Maximum Output
Swing vs. Frequency
4.5
VS = 5V
2
0
10
100k
TPC 19. Maximum Output
Swing vs. Frequency
4.0
VS = 3V
VIN = 2V p-p
RL = INFINITE
TA = 25ⴗC
SUPPLY CURRENT/AMPLIFIER – ␮A
MAXIMUM OUTPUT SWING – V p-p
MAXIMUM OUTPUT SWING – V p-p
4
0
10
SUPPLY CURRENT/AMPLIFIER – ␮A
4.0
3
5
A2
10
50mV
A2
100
90
10
0%
TPC 25. Small Signal Transient
Response
TPC 26. Large Signal Transient
Response
–8–
100µs
TPC 24. Small Signal Transient
Response
10
100µs
VS = 2.5V
AV = 1
RL = 100k⍀
CL = 50pF
TA = +25ⴗC
0%
0%
1V
0mV
100
90
10
100µs
20 40 60 80 100 120
TEMPERATURE – ⴗC
TPC 21. Supply Current/Amplifier
vs. Temperature
0%
50mV
0
500mV
0.50V
VS = 2.75V
AV = 1
RL = 100k⍀
CL = 50pF
TA = 25ⴗC
100µs
TPC 27. Large Signal Transient
Response
REV. B
OP281/OP481
A2
2.50V
VS = 5V
TA = 25ⴗC
A2
0.00V
VS = ⴞ1.35V
RL = ⴥ
VIN = ⴞ1V p-p
AT = 2kHz
A2
100
90
100
90
10
10
10
0%
0%
0%
1V
1V
100
90
500mV
200µs
TPC 28. No Phase Reversal
500mV
50µs
TPC 29. Saturation Recovery Time
120
CHANNEL SEPARATION – dB
105
VS = 5V
TA = 25ⴗC
RL = •
90
75
60
45
30
15
0
–15
–30
100
1k
10k
100k
FREQUENCY – Hz
1M
TPC 31. Channel Separation
vs. Frequency
REV. B
0.00V
–9–
1V
500mV
CIRCUIT = A VOL
VS = ⴞ2.5V
TA = +25ⴗC
RL = ⴥ
100µs
TPC 30. Saturation Recovery Time
OP281/OP481
APPLICATIONS
Theory of Operation
The OPx81 family of op amps is comprised of extremely low
powered, rail-to-rail output amplifiers, requiring less than 4 mA
of quiescent current per amplifier. Many other competitors’
devices may be advertised as low supply current amplifiers but
draw significantly more current as the outputs of these devices
are driven to a supply rail. The OPx81’s supply current remains
under 4 mA even with the output driven to either supply rail.
Supply currents should meet the specification as long as the
inputs and outputs remain within the range of the power supplies.
Figure 1 shows a simplified schematic of a single channel for the
OPx81. A bipolar differential pair is used in the input stage.
PNP transistors are used to allow the input stage to remain
linear with the common-mode range extending to ground. This
is an important consideration for single-supply applications. The
bipolar front end also contributes less noise than a MOS front
end with only nano-amps of bias currents. The output of the op
amp consists of a pair of CMOS transistors in a common source
configuration. This setup allows the output of the amplifier to
swing to within millivolts of either supply rail. The headroom
required by the output stage is limited by the amount of current
being driven into the load. The lower the output current, the
closer the output can go to either supply rail. TPCs 7, 8, and 9
show the output voltage headroom versus load current. This
behavior is typical of rail-to-rail output amplifiers.
This can be done quite easily by placing a resistor in series with
the input to the device. The size of the resistor should be proportional to the lowest possible input signal excursion and can
be found using the following formula:
R=
VEE - VIN , MIN
0.5 ¥ 10 -3
where:
VEE is the negative power supply for the amplifier.
VIN, MIN is the lowest input voltage excursion expected.
For example, a single channel of the OPx81 is to be used with a
single-supply voltage of +5 V where the input signal could possibly
go as low as –1 V. Because the amplifier is powered from a single
supply, VEE is ground, so the necessary series resistance should
be 2 kW.
Input Offset Voltage
The OPx81 family of op amps was designed for low offset
voltages less than 1 mV.
100k
+3V
100k
VOUT
100k
–0.27V
OP281
VIN = 1kHz AT
400mV p-p
100k
–0.1V
VCC
Figure 2. Single OPx81 Channel Configured as
a Difference Amplifier Operating at VCM < 0 V
Input Common-Mode Voltage Range
The OPx81 is rated with an input common-mode voltage range
from VEE to 1 V under VCC. However, the op amp can still operate even with a common-mode voltage that is slightly less than VEE.
Figure 2 shows a single OPx81 channel configured as a difference
amplifier with a single-supply voltage of 3 V. Negative dc voltages
are applied at both input terminals creating a common-mode voltage that is less than ground. A 400 mV p-p input signal is then
applied to the noninverting input. Figure 3 shows the input and
output waves. Notice how the output of the amplifier also drops
slightly negative without distortion.
OUT
+IN
–IN
VEE
Figure 1. Simplified Schematic of a Single OPx81 Channel
0.2ms
Input Overvoltage Protection
The input stage to the OPx81 family of op amps consists of a
PNP differential pair. If the base voltage of either of these input
transistors drops to more than 0.6 V below the negative supply,
the input ESD protection diodes will become forward biased,
and large currents will begin to flow. In addition to possibly
damaging the device, this will create a phase reversal effect at
the output. To prevent these effects from happening, the input
current should be limited to less than 0.5 mA.
VOUT
100
90
0V
VIN
10
0%
0.1V
Figure 3. Input and Output Signals with VCM < 0 V
–10–
REV. B
OP281/OP481
Capacitive Loading
Window Comparator
Most low supply current amplifiers have difficulty driving
capacitive loads due to the higher currents required from the
output stage for such loads. Higher capacitance at the output
will increase the amount of overshoot and ringing in the amplifier’s
step response and could even affect the stability of the device.
However, through careful design of the output stage and its
high phase margin, the OPx81 family can tolerate some degree of
capacitive loading. Figure 4 shows the step response of a single
channel with a 10 nF capacitor connected at the output. Notice
that the overshoot of the output does not exceed more than 10%
with such a load, even with a supply voltage of only 3 V.
The extremely low power supply current demands of the OPx81
family make it ideal for use in long-life battery-powered applications such as a monitoring system. Figure 6 shows a circuit that
uses the OP281 as a window comparator.
3V
3V
3V
R1
5.1k⍀
VH
D1
10k⍀
Q1
A1
R2
VOUT
OP281-A
5.1k⍀
VIN
2k⍀
3V
3V
100
90
R3
D2
VL
A2
OP281-B
R4
10
0%
Figure 6. Using the OP281 as a Window Comparator
Figure 4. Ringing and Overshoot of the Output
of the Amplifier
Micropower Reference Voltage Generator
Many single-supply circuits are configured with the circuit biased
to 1/2 of the supply voltage. In these cases, a false ground reference can be created by using a voltage divider buffered by an
amplifier. Figure 5 shows the schematic for such a circuit.
The two 1 MW resistors generate the reference voltage while
drawing only 1.5 mA of current from a 3 V supply. A capacitor
connected from the inverting terminal to the output of the op amp
provides compensation to allow for a bypass capacitor to be
connected at the reference output. This bypass capacitor helps
to establish an ac ground for the reference output. The entire
reference generator draws less than 5 mA from a 3 V supply source.
The threshold limits for the window are set by VH and VL, provided that VH > VL. The output of A1 will stay at the negative
rail, in this case ground, as long as the input voltage is less than
VH. Similarly, the output of A2 will stay at ground as long the
input voltage is higher than VL. As long as VIN remains between
VL and VH, the outputs of both op amps will be 0 V. With no
current flowing in either D1 or D2, the base of Q1 will stay at
ground, putting the transistor in cutoff and forcing VOUT to the
positive supply rail. If the input voltage rises above VH, the
output of A2 stays at ground, but the output of A1 will go to the
positive rail, and D1 will conduct current. This creates a base
voltage that will turn on Q1 and drive VOUT low. The same
condition occurs if VIN falls below VL with A2’s output going
high, and D2 conducting current. Therefore, VOUT will be high
if the input voltage is between VL and VH, and VOUT will be low
if the input voltage moves outside of that range.
The R1 and R2 voltage divider sets the upper window voltage,
and the R3 and R4 voltage divider sets the lower voltage for the
window. For the window comparator to function properly, VH
must be a greater voltage than VL.
3V TO 12V
10k⍀
R2
R1 + R2
R4
VL =
R3 + R4
VH =
0.022␮F
2
1M⍀
8
OP281
3
4
1
100⍀
1␮F
VREF
1.5V TO 6V
1M⍀
1␮F
The 2 kW resistor connects the input voltage to the input terminals
to the op amps. This protects the OP281 from possible excess
current flowing into the input stages of the devices. D1 and D2 are
small-signal switching diodes (1N4446 or equivalent), and Q1
is a 2N2222 or equivalent NPN transistor.
Figure 5. Single Channel Configured as a Micropower
Bias Voltage Generator
REV. B
–11–
OP281/OP481
Low-Side Current Monitor
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of
prime importance in these designs. Figure 7 shows an example
of a 5 V, single-supply current monitor that can be incorporated
into the design of a voltage regulator with fold-back current
limiting or a high current power supply with crowbar protection.
The design capitalizes on the OPx81’s common-mode range
that extends to ground. Current is monitored in the power supply return path where a 0.1 W shunt resistor, RSENSE, creates a
very small voltage drop. The voltage at the inverting terminal
becomes equal to the voltage at the noninverting terminal through
the feedback of Q1, which is a 2N2222 or equivalent NPN transistor. This makes the voltage drop across R1 equal to the voltage
drop across RSENSE. Therefore, the current through Q1 becomes
directly proportional to the current through RSENSE, and the output
voltage is given by:
Ê R2
ˆ
VOUT = VEE - Á
¥ RSENSE ¥ I L ˜
Ë R1
¯
The voltage drop across R2 increases with IL increasing, so VOUT
decreases with higher supply current being sensed. For the
element values shown, the VOUT transfer characteristic is –2.5 V/A,
decreasing from VEE.
100
90
SCALE 0.1V/DIV
10
SCALE 0.1ms/DIV
0%
Figure 9. Full-Wave Rectified Signal
Amplifier A1 is used as a voltage follower that will track the input
voltage only when it is greater than 0 V. This provides a half-wave
rectification of the input signal to the noninverting terminal of
amplifier A2. When A1’s output is following the input, the inverting terminal of A2 will also follow the input from the virtual
ground between the inverting and noninverting terminals of A2.
With no potential difference across R1, no current flows through
either R1 or R2, therefore the output of A2 will also follow the input.
Now, when the input voltage goes below 0 V, the noninverting
terminal of A2 becomes 0 V. This makes A2 work as an inverting
amplifier with a gain of 1 and provides a full-wave rectified version
of the input signal. A 2 kW resistor in series with A1’s noninverting
input protects the device when the input signal becomes less
than ground.
Battery-Powered Telephone Headset Amplifier
5V
Figure 10 shows how the OP281 can be used as a two-way
amplifier in a telephone headset. One side of the OP281 can be
used as an amplifier for the microphone, while the other side can
be used to drive the speaker. A typical telephone headset uses a
600 W speaker and an electret microphone that requires a supply
voltage and a biasing resistor.
R2
2.49k⍀
VOUT
Q1
5V
0.1␮F
11k⍀
SINGLE
CHANNEL
OPx81
R1
100⍀
0.1⍀
3V
RETURN TO
GROUND
RSENSE
Because of its quick overdrive recovery time, an OP281 can be
configured as a full-wave rectifier for low frequency (<500 Hz)
applications. Figure 8 shows the schematic.
1␮F
1␮F 1M⍀
1␮F 10k⍀
MIC OUT
OP281-A
50k⍀
3V
R2 = 100k⍀
3V
20k⍀
3V
2k⍀
A2
VIN = 2V p-p
A1
OP281-A
3V
ELECTRET 1M⍀
MIC
Low Voltage Half-Wave and Full-Wave Rectifiers
R1 = 100k⍀
3V
2.2k⍀
Figure 7. Low-Side Load Current Monitor
300k⍀
OP281-B
3V
FULL-WAVE
RECTIFIED
OUTPUT
Q1
INPUT 1␮F
3V
HALF-WAVE
RECTIFIED
OUTPUT
1␮F
10k⍀
POT.
OP281-B
Q2
1M⍀
1␮F
Figure 8. Single-Supply Full-Wave and Half-Wave
Rectifiers Using an OP281
1M⍀
20k⍀
600⍀
SPEAKER
Figure 10. Two-Way Amplifier in a Battery-Powered
Telephone Headset
–12–
REV. B
OP281/OP481
The OP281-A op amp provides about 29 dB of gain for audio
signals coming from the microphone. The gain is set by the
300 kW and 11 kW resistors. The gain bandwidth product of the
amplifier is 95 kHz, which, for the set gain of 28, yields a –3 dB
rolloff at 3.4 kHz. This is acceptable since telephone audio is band
limited for 300 kHz to 3 kHz signals. If higher gain is required
for the microphone, an additional gain stage should be used, as
adding any more gain to the OP281 would limit the audio bandwidth. A 2.2 kW resistor is used to bias the electret microphone.
This resistor value may vary depending on the specifications on
the microphone being used. The output of the microphone is accoupled to the noninverting terminal of the op amp. Two 1 MW
resistors are used to provide the dc offset for single-supply use.
The OP281-B amplifier can provide up to 15 dB of gain for the
headset speaker. Incoming audio signals are ac-coupled to a
10 kW potentiometer that is used to adjust the volume. Again,
two 1 MW resistors provide the dc offset with a 1 mF capacitor
establishing an ac ground for the volume control potentiometer.
Because the OP281 is a rail-to-rail output amplifier, it would have
difficulty driving a 600 W speaker directly. Here, a class AB buffer
is used to isolate the load from the amplifier and also provide
the necessary current drive to the speaker. By placing the buffer
in the feedback loop of the op amp, crossover distortion can be
minimized. Q1 and Q2 should have minimum betas of 100. The
600 W speaker is ac-coupled to the emitters to prevent any quiescent current from flowing in the speaker. The 1 mF coupling
capacitor makes an equivalent high-pass filter cutoff at 265 Hz
with a 600 W load attached. Again, this does not pose a problem,
as it is outside the frequency range for telephone audio signals.
The circuit in Figure 10 draws around 250 mA of current. The
class AB buffer has a quiescent current of 140 mA while roughly
100 mA is drawn by the microphone itself. A CR2032 3 V lithium
battery has a life expectancy of 160 mA hours, which means this
circuit could run continuously for 640 hours on a single battery.
SPICE Macro-Model
Single OPx81 Channel SPICE Macro-model
* 9/96, Ver. 1
*
* Copyright 1996 by Analog Devices
*
* Refer to “README.DOC” file for License Statement. Use of this
* model indicates your acceptance of the terms and provisions in the
* License Statement.
*
* Node Assignments
*
noninverting input
*
|
inverting input
*
|
|
positive supply
*
|
|
|
negative supply
*
|
|
|
|
output
*
|
|
|
|
|
*
|
|
|
|
|
.SUBCKT OPx81
1
2
99
50
45
*
* INPUT STAGE
*
Q1
4
1 3
PIX
Q2
6
7 5
PIX
I1
99
8 1.28E-6
REV. B
EOS 7
2 POLY(1) (12, 98) 80E-6 1
IOS
1
2 1E-10
RC1 4 50 500E3
RC2 6 50 500E3
RE1
3
8 108
RE2
5
8 108
V1
99 13 DC .9
V2
99 14 DC .9
D1
3 13 DX
D2
5 14 DX
*
* CMRR 76dB, ZERO AT 1kHz
*
ECM1 11 98 POLY(2) (1, 98) (2, 98) 0 .5 .5
R1
11 12 1.59E6
C1
11 12 100E-12
R2
12 98 283
*
* POLE AT 900kHz
*
EREF 98 0 (90, 0)
1
G1
98 20 (4, 6)
1E-6
R3
20 98 1E6
C2
20 98 177E-15
*
* POLE AT 500kHz
*
E2
21 98 (20, 98)
1
R4
21 22 1E6
C3
22 98 320E-15
*
* GAIN STAGE
*
CF
45 40 8. 5E-12
R5
40 98 65. 65E6
G3
98 40 (22, 98)
4.08E-7
D3
40 41 DX
D4
42 40 DX
V3
99 41 DC 0.5
V4
42 50 DC 0.5
*
* OUTPUT STAGE
*
ISY 99 50 1.375E-6
RS1 99 90 10E6
RS2 90 50 10E6
M1 45 46 99 99
POX L=1.5u W=300u
M2 45 47 50 50
NOX L=1.5u W=300u
EG1 99 46 POLY(1) (98, 40) 0.77 1
EG2 47 50 POLY(1) (40, 98) 0.77 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2, KP=25E-6, VTO=-0.75,
LAMBDA=0.01)
.MODEL NOX NMOS (LEVEL=2, KP=25E-6, VTO=0.75,
LAMBDA=0.01)
.MODEL PIX PNP (BF=200)
.MODEL DX D(IS=1E-14)
.ENDS
–13–
OP281/OP481
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
5
1
1.27 (0.0500)
BSC
0.50 (0.0196)
ⴛ 45ⴗ
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.33 (0.0130)
COPLANARITY
SEATING
0.10
PLANE
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2440)
5.80 (0.2284)
4
0.25 (0.0098)
0.10 (0.0040)
8.75 (0.3445)
8.55 (0.3366)
14
8
1
7
1.75 (0.0689)
1.35 (0.0531)
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.41 (0.0160)
0.19 (0.0075)
6.20 (0.2441)
5.80 (0.2283)
0.51 (0.0201)
0.33 (0.0130)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0197)
ⴛ 45ⴗ
0.25 (0.0098)
8ⴗ
0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.40 (0.0157)
0.19 (0.0075)
COMPLIANT TO JEDEC STANDARDS MS-012AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Dimensions shown in millimeters
5.10
5.00
4.90
3.10
3.00
2.90
8
5
14
4.50
4.40 6.40 BSC
4.30
1
4.50
4.40
4.30
4
6.40
BSC
1
PIN 1
0.15
0.05
8
7
PIN 1
0.65
BSC
1.20
MAX
0.30
COPLANARITY 0.19
0.10
SEATING 0.20
PLANE
0.09
1.05
1.00
0.80
8ⴗ
0ⴗ
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AA
0.30
0.19
0.20
0.09
SEATING COPLANARITY
PLANE
0.10
8ⴗ
0ⴗ
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
–14–
REV. B
OP281/OP481
Revision History
Location
Page
3/03—Data Sheet changed from REV. A to REV. B.
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2/03—Data Sheet changed from REV. 0 to REV. A.
Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted OP181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Updated package options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted OP181 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted Epoxy DIP PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Deleted former Figure 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Deleted Overdrive Recovery Time section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Deleted former Figure 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Deleted 8-Lead and 14-Lead Plastic DIP (N-8 and N-14) OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
REV. B
–15–
–16–
C00291–0–3/03(B)