FSB50550T Smart Power Module (SPM) Features General Description • 500V 3.5A 3-phase FRFET inverter including high voltage integrated circuit (HVIC) FSB50550T is a tiny smart power module (SPM) based on FRFET technology as a compact inverter solution for small power motor drive applications such as fan motors and water suppliers. It is composed of 6 fast-recovery MOSFET (FRFET), and 3 half-bridge HVICs for FRFET gate driving. FSB50550T provides low electromagnetic interference (EMI) characteristics with optimized switching speed. Moreover, since it employs FRFET as a power switch, it has much better ruggedness and larger safe operation area (SOA) than that of an IGBT-based power module or one-chip solution. The package is optimized for the thermal performance and compactness for the use in the built-in motor application and any other application where the assembly space is concerned. FSB50550T is the most solution for the compact inverter providing the energy efficiency, compactness, and low electromagnetic interference. • 3 divided negative dc-link terminals for inverter current sensing applications • HVIC for gate driving and undervoltage protection • 3/5V CMOS/TTL compatible, active-high interface • Optimized for low electromagnetic interference • Isolation voltage rating of 1500Vrms for 1min. • Extended VB pin for PCB isolation Absolute Maximum Ratings Symbol Parameter Conditions Rating Units 500 V VPN DC Link Input Voltage, Drain-source Voltage of each FRFET ID25 Each FRFET Drain Current, Continuous TC = 25°C 1.8 A ID80 Each FRFET Drain Current, Continuous TC = 80°C 1.2 A IDP Each FRFET Drain Current, Peak TC = 25°C, PW < 100µs 3.5 A PD Maximum Power Dissipation TC = 80°C, Each FRFET 4.5 W VCC Control Supply Voltage Applied between VCC and COM 20 V VBS High-side Bias Voltage Applied between VB(U)-U, VB(V)-V, VB(W)-W 20 V VIN Input Signal Voltage Applied between IN and COM -0.3 ~ VCC+0.3 V TJ Operating Junction Temperature -20 ~ 150 °C TSTG Storage Temperature -50 ~ 150 °C RθJC Junction to Case Thermal Resistance Each FRFET under inverter operating condition (Note 1) 8.6 °C/W VISO Isolation Voltage 60Hz, Sinusoidal, 1 minute, Connection pins to heatsink 1500 Vrms ©2006 Fairchild Semiconductor Corporation FSB50550T Rev. A 1 www.fairchildsemi.com FSB50550T Smart Power Module (SPM) September 2006 FSB50550T Smart Power Module (SPM) Pin Descriptions Pin Number Pin Name Pin Description 1 COM IC Common Supply Ground Bias Voltage for U Phase High Side FRFET Driving 2 VB(U) 3 VCC(U) Bias Voltage for U Phase IC and Low Side FRFET Driving 4 IN(UH) Signal Input for U Phase High-side 5 IN(UL) Signal Input for U Phase Low-side 6 NC 7 VB(V) No Connection Bias Voltage for V Phase High Side FRFET Driving 8 VCC(V) Bias Voltage for V Phase IC and Low Side FRFET Driving 9 IN(VH) Signal Input for V Phase High-side 10 IN(VL) 11 NC Signal Input for V Phase Low-side No Connection Bias Voltage for W Phase High Side FRFET Driving 12 VB(W) 13 VCC(W) Bias Voltage for W Phase IC and Low Side FRFET Driving 14 IN(WH) Signal Input for W Phase High-side 15 IN(WL) Signal Input for W Phase Low-side 16 NC 17 P 18 U, VS(U) 19 NU Negative DC–Link Input for U Phase 20 NV Negative DC–Link Input for V Phase 21 V, VS(V) 22 NW 23 W, VS(W) No Connection Positive DC–Link Input Output for U Phase & Bias Voltage Ground for High Side FRFET Driving Output for V Phase & Bias Voltage Ground for High Side FRFET Driving Negative DC–Link Input for W Phase Output for W Phase & Bias Voltage Ground for High Side FRFET Driving (1) COM (2) VB(U) (17) P (3) VCC(U) VCC VB (4) IN(UH) HIN HO (5) IN(UL) LIN VS COM LO (18) U, VS(U) (6) NC (19) NU (7) VB(V) (8) VCC(V) VCC VB (9) IN(VH) HIN HO LIN VS COM LO (10) IN(VL) (20) NV (21) V, VS(V) (11) NC (12) VB(W) (13) VCC(W) VCC VB (14) IN(WH) HIN HO (15) IN(WL) LIN VS COM LO (22) NW (23) W, VS(W) (16) NC Note: Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM. External connections should be made as indicated in Figure 2 and 5. Figure 1. Pin Configuration and Internal Block Diagram (Bottom View) 2 FSB50550T Rev. A www.fairchildsemi.com Inverter Part (Each FRFET Unless Otherwise Specified) Symbol Min Typ 500 - - V Breakdown Voltage TemID = 250µA, Referenced to 25°C perature Coefficient - 0.53 - V IDSS Zero Gate Voltage Drain Current VIN= 0V, VDS = 500V - - 250 µA RDS(on) Static Drain-Source On-Resistance VCC = VBS = 15V, VIN = 5V, ID = 1.2A - 1.3 1.7 Ω VSD Drain-Source Diode Forward Voltage VCC = VBS = 15V, VIN = 0V, ID = -1.2A - - 1.2 V VPN = 300V, VCC = VBS = 15V, ID = 1.2A VIN = 0V ↔ 5V Inductive load L=3mH High- and low-side FRFET switching - 560 - ns - 440 - ns - 130 - ns - 71 - µJ - 11 - µJ BVDSS ∆BVDSS/ ∆TJ Parameter Drain-Source Breakdown VIN= 0V, ID = 250µA (Note 2) Voltage tON tOFF trr Conditions Switching Times EON (Note 3) EOFF RBSOA V = 400V, VCC = VBS = 15V, ID = IDP, REH = 0Ω Reverse-bias Safe Oper- PN VDS=BVDSS, TJ = 150°C ating Area High- and low-side FRFET switching (Note 4) Max Units Full Square Control Part (Each HVIC Unless Otherwise Specified) Symbol IQCC Parameter Quiescent VCC Current Conditions Min Typ Max Units VCC=15V, VIN=0V Applied between VCC and COM - - 160 µA Applied between VB(U)-U, VB(V)-V, VB(W)-W - - 100 µA 7.4 8.0 9.4 V IQBS Quiescent VBS Current VBS=15V, VIN=0V UVCCD Low-side Undervoltage Protection (Figure 6) VCC Undervoltage Protection Detection Level VCC Undervoltage Protection Reset Level 8.0 8.9 9.8 V High-side Undervoltage Protection (Figure 7) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V VIH ON Threshold Voltage Logic High Level 2.9 - - V VIL OFF Threshold Voltage Logic Low Level - - 0.8 V - 10 20 µA - - 2 µA UVCCR UVBSD UVBSR IIH IIL Input Bias Current VIN = 5V Applied between IN and COM Applied between IN and COM VIN = 0V Note: 1. For the measurement point of case temperature TC, please refer to Figure 3 in page 4. 2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM. VPN should be sufficiently less than this value considering the effect of the stray inductance so that VDS should not exceed BVDSS in any case. 3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5. 4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 5 for the RBSOA test circuit that is same as the switching test circuit. Package Marking & Ordering Information Device Marking Device Package Reel Size Tape Width Quantity FSB50550T FSB50550T SPM23AC - - 15 3 FSB50550T Rev. A www.fairchildsemi.com FSB50550T Smart Power Module (SPM) Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified) Symbol Parameter Value Conditions Units Min. Typ. Max. - 300 400 V VPN Supply Voltage Applied between P and N VCC Control Supply Voltage Applied between VCC and COM 13.5 15 16.5 V VBS High-side Bias Voltage Applied between VB and output(U, V, W) 13.5 15 16.5 V 3.0 - VCC V 0 - 0.6 V 1.0 - - µs - 15 - kHz VIN(ON) Input ON Threshold Voltage VIN(OFF) Input OFF Threshold Voltage Applied between IN and COM tdead Blanking Time for Preventing VCC=VBS=13.5 ~ 16.5V, TJ ≤ 150°C Arm-short fPWM PWM Switching Frequency TJ ≤ 150°C These values depend on PWM control algorithm C1 15-V Line R1 P D1 R5 Micom C5 VCC VB HIN HO LIN VS COM LO Inverter Output C3 N 10µF VDC R3 One-Leg Diagram of SPM C2 HIN LIN Output Note 0 0 Z Both FRFET Off 0 1 0 Low-side FRFET On 1 0 VDC High-side FRFET On 1 1 Forbidden Shoot-through Open Open Z Same as (0, 0) * Example of bootstrap paramters: C1 = C2 = 1µF ceramic capacitor, R1 = 56Ω, Note: (1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 600-V rating (2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above. (3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM is compatible with standard CMOS or LSTTL outptus. (4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2 and C3 should have good high-frequency characteristics to absorb high-frequency ripple current. Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters 14.50mm 3.80mm Case Temperature(Tc) Detecting Point MOSFET Note: Attach the thermocouple on top of the heatsink-side of SPM (between SPM and heatsink if applied) to get the correct temperature measurement. Figure 3. Case Temperature Measurement 4 FSB50550T Rev. A www.fairchildsemi.com FSB50550T Smart Power Module (SPM) Recommended Operating Conditions FSB50550T Smart Power Module (SPM) VIN VIN Irr 120% of ID 100% of ID VDS ID 10% of ID ID VDS tON trr tOFF (a) Turn-on (b) Turn-off Figure 4. Switching Time Definition CBS VCC ID RBS VCC VB HIN HO LIN VS COM LO L VDC + VDS - One-leg Diagram of SPM Figure 5. Switching and RBSOA(Single-pulse) Test Circuit (Low-side) Input Signal UV Protection Status Low-side Supply, VCC RESET DETECTION RESET UVCCR UVCCD MOSFET Current Figure 6. Undervoltage Protection (Low-side) Input Signal UV Protection Status High-side Supply, VBS RESET DETECTION RESET UVBSR UVBSD MOSFET Current Figure 7. Undervoltage Protection (High-side) 5 FSB50550T Rev. A www.fairchildsemi.com (1) COM (2) VB(U) R1 (3) VCC(U) R5 (4) IN(UH) (5) IN(UL) C5 C2 (6) NC VCC VB HIN HO LIN VS COM LO (18) U, VS(U) C3 (8) VCC(V) (9) IN(VH) (10) IN(VL) C2 (11) NC VDC (19) N U (7) VB(V) R1 Micom (17) P VCC VB HIN HO LIN VS COM LO VCC VB HIN HO LIN VS COM LO (20) N V (21) V, VS(V) M (12) VB(W) R1 (13) VCC(W) (14) IN(WH) (15) IN(WL) C2 (16) NC (22) N W (23) W, V S(W) For 3-phase current sensing and protection 15-V Supply C4 R4 R3 Figure 8. Example of Application Circuit 6 FSB50550T Rev. A www.fairchildsemi.com FSB50550T Smart Power Module (SPM) C1 FSB50550T Smart Power Module (SPM) Detailed Package Outline Drawings Max 1.00 0.60 ±0.10 (1.165) (1.80) 15*1.778=26.67 ±0.30 13.34 ±0.30 (1.00) 13.34±0.30 #1 #16 R 0. 40 -0.05 13.13±0.30 0.50+0.10 #23 12.23 ±0.30 19.58±0.30 5° 3° 14.00 14.58±0.30 19.00 40 0. 12.00±0.20 R #17 3.10 ±0.20 29.00 ±0.20 6.20±0.20 2x3.90=7.80 ±0.30 (2.275) 1.95 ±0.30 (1.30) (1.80) 4x3.90=15.60 ±0.30 0.60 ±0.10 Max 1.00 7 FSB50550T Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I20