Maxim MAX1169BEUD+ 58.6ksps, 16-bit, 2-wire serial adc in a 14-pin tssop Datasheet

19-2654; Rev 1; 12/09
KIT
ATION
EVALU
E
L
B
A
AVAIL
58.6ksps, 16-Bit,
2-Wire Serial ADC in a 14-Pin TSSOP
The MAX1169 is a low-power, 16-bit successiveapproximation analog-to-digital converter (ADC). The
device features automatic power-down, an on-chip
4MHz clock, a +4.096V internal reference, and an
I2C-compatible 2-wire serial interface capable of both
fast and high-speed modes.
The MAX1169 operates from a single supply and consumes 5mW at the maximum conversion rate of
58.6ksps. AutoShutdown™ powers down the device
between conversions, reducing supply current to less
than 50μA at a 1ksps throughput rate. The option of a
separate digital supply voltage allows direct interfacing
with +2.7V to +5.5V digital logic.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to AVDD.
The four address select inputs (ADD0 to ADD3) allow
up to 16 MAX1169 devices on the same bus.
Features
♦ High-Speed
Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
I2C-Compatible
♦ +4.75V to +5.25V Single Supply
♦ +2.7V to +5.5V Adjustable Logic Level
♦ Internal +4.096V Reference
♦ External Reference: 1V to AVDD
♦ Internal 4MHz Conversion Clock
♦ 58.6ksps Sampling Rate
♦ AutoShutdown Between Conversions
♦ Low Power
5.0mW at 58.6ksps
4.2mW at 50ksps
2.0mW at 10ksps
0.23mW at 1ksps
3µW in Shutdown
♦ Small 14-Pin TSSOP Package
The MAX1169 is packaged in a 14-pin TSSOP and
offers both commercial and extended temperature
ranges. Refer to the MAX1069 data sheet for a 14-bit
device in a pin-compatible package.
Ordering Information
PART
Applications
Hand-Held Portable Applications
PINPACKAGE
TEMP RANGE
INL
(LSB)
MAX1169BCUD+
0°C to +70°C
14 TSSOP
±2
MAX1169BEUD+
-40°C to +85°C
14 TSSOP
±2
+Denotes a lead(Pb)-free/RoHS-compliant package.
Medical Instruments
Pin Configuration
Battery-Powered Test Equipment
Solar-Powered Remote Systems
TOP VIEW
DGND 1
14 ADD3
Received-Signal-Strength Indicators
SCL
2
13 REF
System Supervision
SDA
3
12 REFADJ
ADD2 4
MAX1169
ADD1 5
11 AGNDS
10 AIN
ADD0 6
9
AGND
DVDD 7
8
AVDD
TSSOP
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1169
General Description
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND .........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
AGNDS to AGND...................................................-0.3V to +0.3V
AIN, REF, REFADJ to AGND....................-0.3V to (AVDD + 0.3V)
SCL, SDA, ADD_ to DGND.......................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (TA = +70°C)
14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW
Operating Temperature Ranges
MAX1169_CUD ..................................................0°C to +70°C
MAX1169_EUD ................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
16
Relative Accuracy (Note 2)
INL
MAX1169B
Differential Nonlinearity
DNL
MAX1169B, no missing codes
16-bit
NMC
Offset Error
Offset-Error Temperature
Coefficient
Bits
±2
LSB
0.7
1.7
LSB
2
5
mV
1.0
Gain Error
(Note 3)
±0.25
Gain Temperature Coefficient
ppm/°C
±0.5
%FSR
0.1
ppm/°C
90
dB
DYNAMIC PERFORMANCE (fIN(sine wave) = 1kHz, VIN = VREF(P-P), fSAMPLE = 58.6ksps)
Signal-to-Noise Plus Distortion
SINAD
86
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
SFDR
92
105
dB
Signal-to-Noise Ratio
SNR
87
90
dB
Full-Power Bandwidth
FPBW
-3dB point
4
MHz
SINAD > 81dB
33
kHz
Full-Linear Bandwidth
Up to the 5th harmonic
-102
-90
dB
CONVERSION RATE (Figure 11)
Conversion Time
(SCL Stretched Low)
Throughput Rate (Note 4)
tCONV
f SAMPLE
Internal Clock Frequency
fCLK
Track/Hold Acquisition Time
tACQ
Aperture Delay, Figure 11c
(Note 6)
2
tAD
Fast mode
7.1
7.5
High-speed mode
5.8
6
Fast mode
19
High-speed mode
58.6
4
(Note 5)
1100
μs
ksps
MHz
ns
Fast mode
50
High-speed mode
30
_______________________________________________________________________________________
ns
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Aperture Jitter, Figure 11c
SYMBOL
tAJ
CONDITIONS
MIN
TYP
Fast mode
100
High-speed mode
100
MAX
UNITS
ps
ANALOG INPUT (AIN)
Input Voltage Range
VAIN
On/off-leakage current, VAIN = 0 or AVDD,
no clock, f SCL = 0
Input Leakage Current
Input Capacitance
0
±0.01
CIN
VREF
V
±10
μA
35
pF
INTERNAL REFERENCE (bypass REFADJ with 0.1μF to AGND and REF with 10μF to AGND)
REF Output Voltage
VREF
Reference Temperature
Coefficient
TCREF
Reference Short-Circuit Current
IREFSC
4.056
TA = 0°C to +70°C
±20
TA = -40°C to +85°C
±35
4.136
4.056
For small adjustments, from 4.096V
4.096
V
ppm/°C
10
REFADJ Output Voltage
REFADJ Input Range
4.096
mA
4.136
±60
V
mV
EXTERNAL REFERENCE (REFADJ = AVDD)
Pull REFADJ high to disable the internal
bandgap reference and reference buffer
REFADJ Buffer Disable Voltage
AVDD
- 0.1
V
REFADJ Buffer Enable Voltage
Reference Input Voltage Range
(Note 7)
REF Input Current
VREF = +4.096V, VIN = VREF(P-P),
f IN(sine wave) = 1kHz, f SAMPLE = 58.6ksps
27
VREF = +4.096V, shutdown
0.1
IREF
1.0
AVDD
- 0.4
V
AVDD
V
μA
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Hysteresis
0.7 DVDD
0.3 DVDD
0.1 DVDD
VHYST
Input Current
I IN
Input Capacitance
CIN
Output Low Voltage
VOL
V
V
±10
15
I SINK = 3mA
V
μA
pF
0.4
V
ADDRESS SELECT INPUTS (ADD3, ADD2, ADD1, ADD0)
Input High Voltage
0.7 DVDD
V
0.3 DVDD
Input Low Voltage
Input Hysteresis
0.1 DVDD
V
V
_______________________________________________________________________________________
3
MAX1169
ELECTRICAL CHARACTERISTICS (continued)
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input Current
Input Capacitance
MAX
UNITS
±10
μA
15
pf
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.7
5.5
V
Internal reference
(powered down
between conversions,
R/W = 0)
Analog Supply Current
IAVDD
Internal reference
(always on, R/W = 1)
External reference
(REFADJ = AVDD)
Digital Supply Current
IDVDD
Power-Supply Rejection Ratio
PSRR
fSAMPLE = 58.6ksps
1.8
fSAMPLE = 10ksps
0.7
2.5
fSAMPLE = 1ksps
40
Shutdown
0.4
5
fSAMPLE = 58.6ksps
1.8
2.5
fSAMPLE = 10ksps
1.4
fSAMPLE = 1ksps
1.1
Shutdown
0.4
5
fSAMPLE = 58.6ksps
0.90
1.8
fSAMPLE = 10ksps
0.36
fSAMPLE = 1ksps
40
Shutdown
0.4
5
fSAMPLE = 58.6ksps
260
400
fSAMPLE = 10ksps
65
fSAMPLE = 1ksps
6
Shutdown
AVDD = 5V ±5%, full-scale input (Note 8)
mA
μA
mA
μA
mA
μA
μA
0.2
5
5
16
LSB/V
400
kHz
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)
Serial Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
μs
Hold Time for Start Condition
tHD, STA
0.6
μs
Low Period of the SCL Clock
tLOW
1.3
μs
High Period of the SCL Clock
tHIGH
0.6
μs
Setup Time for a Repeated
START Condition (Sr)
tSU, STA
0.6
μs
Data Hold Time
tHD, DAT
Data Setup Time
tSU, DAT
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
Setup Time for STOP Condition
(Note 9)
0
900
100
ns
tR
(Note 10)
20 + 0.1CB
300
tF
(Note 10)
20 + 0.1CB
300
tSU, STO
ns
0.6
ns
ns
μs
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
4
_______________________________________________________________________________________
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
MHz
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figure 1b and Figure 2)
Serial Clock Frequency
fSCLH
(Note 11)
Hold Time (Repeated) Start
Condition
tHD, STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
Setup Time for a Repeated
START Condition
tSU, STA
160
ns
Data Hold Time
tHD, DAT
Data Setup Time
tSU, DAT
(Note 9)
0
150
10
ns
ns
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
(Note 10)
10
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
(Note 10)
20
160
ns
Fall Time of SCL Signal
tFCL
(Note 10)
20
80
ns
Rise Time of SDA Signal
tRDA
(Note 10)
20
160
ns
tFDA
(Note 10)
20
160
ns
Fall Time of SDA Signal
Setup Time for STOP Condition
tSU, STO
160
ns
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
10
ns
Note 1: DC accuracy is tested at AVDD = +5.0V and DVDD = +3.0V. Performance at power-supply tolerance limits is guaranteed
by power-supply rejection test.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offset have been calibrated.
Note 3: Offset nullified.
Note 4: One sample is achieved every 18 clocks in continuous conversion mode:
⎛ 18 clocks
⎞
fSAMPLE = ⎜
+ t CONV ⎟
f
⎝
⎠
SCL
-1
Note 5: The track/hold acquisition time is two SCL cycles as illustrated in Figure 11:
⎛ 1 ⎞
t ACQ = 2 × ⎜
⎟
⎝ fSCL ⎠
Note 6: A filter on SDA and SCL delays the sampling instant and suppresses noise spikes less than 10ns in high-speed mode and
50ns in fast mode.
Note 7: ADC performance is limited by the converter’s noise floor, typically 225μVP-P.
Note 8:
PSRR =
2N
⎡⎣ VFS (5.25V)-VFS (4.75V) ⎤⎦ ×
VREF
5.25V - 4.75V
where N is the number of bits (16).
_______________________________________________________________________________________
5
MAX1169
ELECTRICAL CHARACTERISTICS (continued)
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to REF, REFADJ = AVDD, CREF = 10μF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
Note 9: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 10: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3 ✕ DVDD and 0.7 ✕ DVDD.
Note 11: fSCL must meet the minimum clock low time plus the rise/fall times.
A. F/S-MODE I2C SERIAL INTERFACE TIMING
tR
tF
SDA
tSU,DAT
tHD,DAT
tLOW
tBUF
tHD,STA
tSU,STA
tSU,STO
SCL
tHD,STA
tHIGH
tR
tF
S
Sr
A
P
B. HS-MODE I2C SERIAL INTERFACE TIMING
S
tFDA
tRDA
SDA
tHD,DAT
tSU,DAT
SCL
tBUF
tHD,STA
tSU,STA
tLOW
tSU,STO
tHIGH
tHD,STA
tRCL
tFCL
tRCL1
S
Sr
A
P
HS-MODE
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 1. I2C Serial Interface Timing
VDD
IOL = 3mA
DIGITAL
I/O
VOUT
400pF
IOH = 0mA
Figure 2. Load Circuit
6
_______________________________________________________________________________________
S
F/S-MODE
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
1.73
DVDD = 3V
820
500
800
790
TA = +85°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = -40°C
1.67
1.65
IAVDD (nA)
IAVDD (μA)
1.69
TA = +85°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = -40°C
780
770
1.63
400
300
4.95
5.05
5.15
5.25
100
0
4.75
4.85
AVDD (V)
4.95
5.05
5.15
4.85
4.95
240
5.15
5.25
DIGITAL SHUTDOWN CURRENT
vs. DIGITAL SUPPLY VOLTAGE
350
MAX1169 toc04
AVDD = 5V
5.05
AVDD (V)
AVDD (V)
280
260
4.75
5.25
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
300
AVDD = 5V
fSAMPLE = 0
R/W = 0
TA = -40°C
250
TA = +85°C
IDVDD (nA)
IDVDD (μA)
220
200
180
TA = 0°C
200
TA = +25°C
150
TA = +70°C
TA = -40°C
160
100
TA = +85°C
140
50
120
0
100
3.1
3.5
3.9
4.3
4.7
5.1
2.7
5.5
3.1
3.5
3.9
4.3
4.7
DVDD (V)
DVDD (V)
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
0.008
MAX1169 toc06
800
600
0.006
GAIN ERROR (% FSR)
400
200
0
-200
5.5
0.004
0.002
0
-0.002
-400
-0.004
-600
-0.006
-800
5.1
MAX1169 toc07
2.7
OFFSET ERROR (μV)
4.85
TA = +85°C
TA = +70°C
TA = +25°C
TA = 0°C
TA = -40°C
200
760
4.75
DVDD = 3V
fSAMPLE = 0
R/W = 0
600
810
1.71
IAVDD (mA)
700
MAX1169 toc03
DVDD = 3V
MAX1169 toc02
830
MAX1169 toc01
1.75
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT vs. ANALOG
SUPPLY VOLTAGE (EXTERNAL REFERENCE)
MAX1169 toc05
ANALOG SUPPLY CURRENT vs. ANALOG
SUPPLY VOLTAGE (INTERNAL REFERENCE)
-0.008
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX1169
Typical Operating Characteristics
(DVDD = +3.0V, AVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to
REF, REFADJ = AVDD, CREF = 10μF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(DVDD = +3.0V, AVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to
REF, REFADJ = AVDD, CREF = 10μF, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. CONVERSION RATE
(HIGH-SPEED MODE, EXTERNAL REFERENCE)
SUPPLY CURRENT vs. CONVERSION RATE
(HIGH-SPEED MODE, INTERNAL REFERENCE)
1200
1000
IAVDD, R/W = 0
800
600
IAVDD, R/W = 1 OR 0
600
500
400
300
IDVDD, R/W = 1 OR 0
100
200
0
0
0
10
20
30
40
50
60
0
70
10
20
30
40
50
60
70
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
SUPPLY CURRENT vs. CONVERSION RATE
(FAST MODE, INTERNAL REFERENCE)
SUPPLY CURRENT vs. CONVERSION RATE
(FAST MODE, EXTERNAL REFERENCE)
IAVDD, R/W = 1
1400
1200
1000
IAVDD, R/W = 0
800
600
600
EXTERNAL REFERENCE, fSCL = 400kHz
500
SUPPLY CURRENT (μA)
INTERNAL REFERENCE, fSCL = 400kHz
1600
MAX1169 toc10
1800
IAVDD, R/W = 1 OR 0
400
300
200
IDVDD, R/W = 1 OR 0
400
IDVDD, R/W = 1 OR 0
200
100
0
0
0
5
10
15
CONVERSION RATE (ksps)
8
700
200
IDVDD, R/W = 1 OR 0
400
MAX1169 toc09
IAVDD, R/W = 1
1400
MAX1169 toc11
SUPPLY CURRENT (μA)
1600
EXTERNAL REFERENCE, fSCL = 1.7MHz
800
SUPPLY CURRENT (μA)
INTERNAL REFERENCE, fSCL = 1.7MHz
1800
900
MAX1169 toc08
2000
SUPPLY CURRENT (μA)
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
20
25
0
5
10
15
20
CONVERSION RATE (ksps)
_______________________________________________________________________________________
25
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
INTERNAL REFERENCE VOLTAGE
vs. REF LOAD
INTERNAL +4.096V REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
TA = +85°C
4.090
TA = +70°C
MAX1169 toc13
DVDD = 3V
4.095
4.20
MAX1169 toc12
4.100
fSCL = 0
INTERNAL REFERENCE MODE
LOAD APPLIED TO REF
4.15
VREF (V)
VREF (V)
4.10
TA = +25°C
4.05
4.085
TA = 0°C
4.00
4.080
3.95
TA = -40°C
3.90
4.075
4.85
4.95
5.05
5.15
1
2
3
4
5
6
AVDD (V)
IREF (mA)
EXTERNAL REFERENCE CURRENT
vs. EXTERNAL REFERENCE VOLTAGE
EXTERNAL REFERENCE CURRENT AND
REFERENCE VOLTAGE vs. VREFADJ
AIN = AGNDS
30
25
20
19ksps
fSCL = 400kHz
15
20
4.20
10
4.15
IREFADJ
4.10
0
4.05
-10
10
4.25
AIN = AGNDS
IREFADJ (μA)
58.6ksps
fSCL = 1.7MHz
MAX1169 toc15
30
MAX1169 toc14
35
IREF (μA)
0
5.25
VREF (V)
4.75
VREF
-20
5
0
4.00
-30
0
1
2
3
VREF (V)
4
5
6
3.95
3.95
4.00
4.05
4.10
4.15
4.20
4.25
VREFADJ (V)
_______________________________________________________________________________________
9
MAX1169
Typical Operating Characteristics (continued)
(DVDD = +3.0V, AVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to
REF, REFADJ = AVDD, CREF = 10μF, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(DVDD = +3.0V, AVDD = +5.0V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external reference applied to
REF, REFADJ = AVDD, CREF = 10μF, TA = +25°C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. FREQUENCY
100
100
1.5
90
80
70
60
50
70
60
50
40
30
40
30
20
10
0
20
10
0
10
-2.0
-2.5
10
100
0
16,384
32,768
FREQUENCY (kHz)
DIGITAL OUTPUT CODE
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
SINAD vs. FREQUENCY
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
100
-30
-40
2.0
1.5
-50
-60
-70
70
60
50
-80
-90
40
30
-100
-110
-120
20
10
0
10
1.0
INL (LSB)
SINAD (dB)
90
80
100
0.5
0
-0.5
-1.0
-1.5
-2.0
1
10
FREQUENCY (kHz)
100
0
16,384
32,768
fSAMPLE = 58.6ksps
fIN(SINE WAVE) = 1kHz
VIN = VREF(P-P)
MAX1169 toc22
FFT
0
-20
-40
-60
-80
-100
-120
-140
0
5.86
11.72
17.56
49,152
DIGITAL OUTPUT CODE
FREQUENCY (kHz)
MAGNITUDE (dB)
65,536
MAX1169 toc21
120
110
MAX1169 toc19
-20
23.44
29.30
FREQUENCY (kHz)
10
49,152
FREQUENCY (kHz)
0
-10
1
0
-1.0
1
100
0.5
-0.5
MAX1169 toc20
1
1.0
DNL (LSB)
SFDR (dB)
90
80
SNR (dB)
2.0
MAX1169 toc17
120
110
MAX1169 toc16
120
110
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1169 toc18
SIGNAL-TO-NOISE RATIO
vs. FREQUENCY
THD (dB)
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
______________________________________________________________________________________
65,536
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
PIN
NAME
FUNCTION
1
DGND
2
SCL
Clock Input
3
SDA
Data Input/Output
4
ADD2
Address Select Input 2
5
ADD1
Address Select Input 1
6
ADD0
Address Select Input 0
7
DVDD
Digital Power Input. Bypass to DGND with a 0.1μF capacitor.
8
AVDD
Analog Power Input. Bypass to AGND with a 0.1μF capacitor.
9
AGND
Analog Ground
10
AIN
11
AGNDS
Analog Signal Ground. Negative reference for analog input. Connect to AGND.
12
REFADJ
Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1μF capacitor.
Connect REFADJ to AVDD to disable the internal bandgap reference and reference-buffer amplifier.
13
REF
14
ADD3
Digital Ground
Analog Input
Reference Buffer Output and External Reference Input. Bypass to AGND with a 10μF capacitor
when using the internal reference.
Address Select Input 3
Detailed Description
The MAX1169 ADC uses successive-approximation
conversion (SAR) techniques and on-chip track-andhold (T/H) circuitry to capture and convert an analog
signal to a serial 16-bit digital output.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to AVDD.
The flexible 2-wire serial interface provides easy connection to microcontrollers (μCs) and supports data
rates up to 1.7MHz. Figure 3 shows the simplified functional diagram for the MAX1169 and Figure 4 shows the
typical application circuit.
Power Supply
To maintain a low-noise environment, the MAX1169
provides separate analog and digital power-supply
inputs. The analog circuitry requires a +5V supply and
consumes only 900μA at sampling rates up to
58.6ksps. The digital supply voltage accepts voltages
from +2.7V to +5.5V to ensure compatibility with low-
voltage ASICs. The MAX1169 wakes up in shutdown
mode when power is applied irrespective of the AVDD
and DVDD sequence.
Analog Input and Track/Hold
The MAX1169 analog input contains a T/H capacitor,
T/H switches, comparator, and a switched capacitor
digital-to-analog converter (DAC) (Figure 5).
As shown in Figure 11c, the MAX1169 acquisition period is the two clock cycles prior to the conversion period. The T/H switches are normally in the hold position.
During the acquisition period, the T/H switches are in
the track position and CT/H charges to the analog input
signal. Before a conversion begins, the T/H switches
move to the hold position retaining the charge on CT/H
as a sample of the analog input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 16-bit resolution. This is equivalent to transferring a charge of 35pF × (VAIN - VAGNDS)
from C T/H to the binary weighted capacitive DAC,
forming a digital representation of the analog input signal. During the conversion period, the MAX1169 holds
SCL low (clock stretching).
______________________________________________________________________________________
11
MAX1169
Pin Description
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
6
5
4
14
3
2
CONTROL
LOGIC
AVDD
AGND
AIN
AGNDS
8
7
DVDD
1
DGND
4MHz
INTERNAL
OSCILLATOR
9
ADD0
ADD1
ADD2
ADD3
SDA
SCL
CLOCK
10
T/H
11
IN
OUTPUT SHIFT
REGISTER
SAR
ADC OUT
REF
AV = 1.0
5kΩ
+4.096V
REFERENCE
MAX1169
12
REFADJ
13
REF
Figure 3. MAX1169 Simplified Functional Diagram
5.0V
8
0.1μF
13
REF
10μF
12
μC
3.0V
AVDD MAX1169
REFADJ
7
DVDD
6
ADD0
5
ADD1
4
ADD2
SDA 3
2
SCL
VDD
0.1μF
RP
RP
SDA
SCL
0.1μF
ANALOG
SOURCE
10
11
AIN
AGNDS
AGND
9
ADD3
14
VSS
DGND
1
I2C ADDRESS IS 0110111.
Figure 4. Typical Application Circuit
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, lengthen the
acquisition time by reducing fSCL. The MAX1169 provides two SCL cycles (tACQ) in which the track-andhold capacitance must acquire a charge representing
the input signal. Minimize the input source impedance
(RSOURCE) to allow the track-and-hold capacitance to
12
charge within the allotted time. RSOURCE should be
less than 11.3kΩ for fSCL = 400kHz and less than 2kΩ
for fSCL = 1.7MHz. RSOURCE is calculated with the following equation:
R SOURCE ≤
2
fSCL × In(2 × 2 N ) × C IN
______________________________________________________________________________________
− RIN
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
To improve the input-signal bandwidth under AC
conditions, drive AIN with a wideband buffer
(>4MHz) that can drive the ADC’s input capacitance
and settle quickly (see the Input Buffer section).
An RC filter at AIN reduces the input track-and-hold
switching transient by providing charge for CT/H.
Analog Input Bandwidth
The MAX1169 features input-tracking circuitry with a
4MHz small-signal bandwidth. The 4MHz input bandwidth makes it possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using undersampling techniques. Use anti-alias filtering to avoid
high-frequency signals being aliased into the frequency
band of interest.
Analog Input Range and Protection
Internal electrostatic discharge (ESD) protection diodes
clamp AIN, REF, and REFADJ to AVDD and AGNDS/
AGND (Figure 6). These diodes allow the analog inputs
to swing from (AGND - 0.3V) to (AVDD + 0.3V) without
causing damage to the device. For accurate conversions, the inputs must not go more than 50mV beyond
their rails.
If the analog inputs exceed 300mV beyond their
rails, limit the current to 2mA.
Internal Clock
The MAX1169 contains an internal 4MHz oscillator that
drives the SAR conversion clock. During conversion, SCL
is held low (clock stretching). An internal register stores
*RSOURCE
HOLD
AIN
HOLD
HOLD
TRACK
TRACK
SDA and SCL require pullup resistors (500Ω or greater,
Figure 4). Optional resistors (24Ω) in series with SDA
and SCL protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX1169. The data on SDA must
remain stable during the high period of the SCL clock
pulse as changes in SDA while SCL is high are control
signals (see the START and STOP Conditions section).
Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is
high (Figure 7). The STOP condition frees the bus and
places all devices in F/S mode (see the Bus Timing
section). Use a repeated START condition (Sr) in place
of a STOP condition to leave the bus active and in its
current timing mode (see the HS Mode section).
MAX1169
TRACK
ANALOG
SIGNAL
SOURCE
Digital Interface
The MAX1169 features an I2C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the
MAX1169 and the master at rates up to 1.7MHz. The
master (typically a microcontroller) initiates data transfer on the bus and generates SCL.
AVDD
REF
CT/H
data when the conversion is in progress. When the
MAX1169 releases SCL, the master reads the conversion
results at any clock rate up to 1.7MHz (Figure 11).
CAPACITIVE
DAC
AIN
MAX1169
REF
REFADJ
AGNDS
AGNDS
*MINIMIZE RSOURCE TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (CT/H) TO
CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (tACQ).
Figure 5. Equivalent Input Circuit
AGND
Figure 6. Internal Protection Diodes
______________________________________________________________________________________
13
MAX1169
where RSOURCE is the analog input source impedance,
fSCL is the maximum system SCL frequency, N is 16
(the number of bits of resolution), CIN is 35pF (the sum
of CT/H and input stray capacitance), and RIN is 800Ω
(the T/H switch resistances).
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
S
Sr
P
SDA
SCL
Figure 7. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
SCL
1
2
8
9
Figure 8. Acknowledge Bits
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX1169 (slave) generate acknowledge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 8). To generate a not acknowledge, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the master should reattempt communication at a later time.
Slave Address
A master initiates communication with a slave device by
issuing a START condition followed by a slave address
byte. As shown in Figure 9, the slave address byte consists of 7 address bits and a read/write bit (R/W). When
idle, the MAX1169 continuously waits for a START condition followed by its slave address. When the
MAX1169 recognizes its slave address, it acquires the
analog input signal and prepares for conversion. The
first 3 bits (MSBs) of the slave address have been factory programmed and are always 011. Connecting
14
ADD3–ADD0 to DVDD or DGND, programs the last 4
bits (LSBs) of the slave address high or low.
Since the MAX1169 does not require setup or configuration, the least significant bit (LSB) of the address byte
(R/W) controls power-down. In external reference mode
(REFADJ = AVDD), R/W is a don’t care. In internal reference mode, setting R/W = 1 places the device in normal operation and setting R/W = 0 powers down the
internal reference following the conversion (see the
Internal Reference Shutdown section).
After receiving the address, the MAX1169 (slave)
issues an acknowledge by pulling SDA low for one
clock cycle.
Bus Timing
At power-up, the MAX1169 bus timing defaults to fast
mode (F/S mode), allowing conversion rates up to
19ksps. The MAX1169 must operate in high-speed
mode (HS mode) to achieve conversion rates up to
58.6ksps. Figure 1 shows the bus timing for the
MAX1169 2-wire interface.
HS Mode
At power-up, the MAX1169 bus timing is set for F/S
mode. The master selects HS mode by addressing all
devices on the bus with the HS mode master code 0000
1XXX (X = don’t care). After successfully receiving the
HS mode master code, the MAX1169 issues a not
acknowledge, allowing SDA to be pulled high for one
clock cycle (Figure 10). After the not acknowledge, the
______________________________________________________________________________________
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
MAX1169
S
0
SDA
1
ADD3
1
ADD2
ADD1
ADD0
R/W
A
ACKNOWLEDGE
1
SCL
2
3
4
5
6
7
8
9
Figure 9. MAX1169 Slave Address Byte
Sr
S
SDA
0
0
0
0
1
X
X
X
A
1
2
3
4
5
6
7
8
9
F/S MODE
HS MODE
Figure 10. F/S-Mode to HS-Mode Transfer
MAX1169 is in HS mode. The master must then send a
repeated START followed by a slave address to initiate
HS mode communication. If the master generates a
STOP condition, the MAX1169 returns to F/S mode.
Data Byte (Read Cycle)
Initiate a read cycle to begin a conversion. A read
cycle begins with the master issuing a START condition
followed by 7 address bits and 1 read bit (R/W). The
standard I2C-compatible interface requires that R/W =
1 to read from a device; however, since the MAX1169
does not require setup or configuration, the read mode
is inherent and R/W controls power-down (see the
Internal Reference Shutdown section). If the address
byte is successfully received, the MAX1169 (slave)
issues an acknowledge and begins conversion.
As seen in Figure 11, the MAX1169 holds SCL low during conversion. When the conversion is complete, SCL
is released and the master can clock data out of the
device. The most significant byte of the conversion is
available first and contains D15 to D8. The least significant byte contains D7 to D0. Data can be continuously
converted as long as the master acknowledges the
conversion results. Issuing a not acknowledge frees the
bus, allowing the master to generate a STOP or repeated START.
Applications Information
Power-On Reset
When power is first applied, internal power-on reset circuitry activates the MAX1169 in shutdown. When the
internal reference is used, allow 12ms for the reference
to settle when CREF = 10μF and CREFADJ = 0.1μF.
Automatic Shutdown
The MAX1169 automatic shutdown reduces the supply
current to less than 0.6μA between conversions. The
MAX1169 I2C-compatible interface is always active.
When the MAX1169 receives a valid slave address, the
device powers up. The device is then powered down
again when the conversion is complete. The automatic
shutdown function does not change with internal or
external reference. When the internal reference is chosen, the internal reference remains active between conversions unless internal reference shutdown is requested
(see the Internal Reference Shutdown section).
Internal Reference Shutdown
The R/W bit of the slave address controls the MAX1169
internal reference shutdown. In external reference
mode (REFADJ = AVDD), R/W is a don’t care. In internal
reference mode, setting R/W = 1 places the device in
normal operation and setting R/W = 0 prepares the
internal reference for shutdown.
______________________________________________________________________________________
15
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION
1
7
1 1
S
SLAVE ADDRESS
R A
CLOCK STRETCH
8
1
8
RESULT
A
RESULT
NUMBER OF BITS
1
1
A P OR Sr
(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)
tCONV
tACQ
B. CONTINUOUS CONVERSIONS
1
7
S
SLAVE ADDRESS
8
1 1
RESULT #1
CLOCK STRETCH
R A
1
8
1
A
RESULT #1
A
CLOCK STRETCH
(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)
tACQ
tCONV
1
RESULT #2
A
CLOCK STRETCH
1
RESULT #2
A
NUMBER OF BITS
(MOST SIGNIFICANT BYTE)
tACQ
8
8
tCONV
8
1
8
1
RESULT #N
A
RESULT #N
NUMBER OF BITS
1
A P OR Sr
(MOST SIGNIFICANT BYTE) (LEAST SIGNIFICANT BYTE)
(LEAST SIGNIFICANT BIT)
tACQ
tCONV
C. ACQUISITION DETAIL
SDA
BIT3
BIT2
BIT1
BIT0
SCL
5
6
7
8
A
9
tACQ
ANALOG INPUT
TRACK AND HOLD
HOLD
TRACK
CLOCK STRETCH
D15
D14
D13
1
2
3
D12
4
tAJ
tAD
tCONV
HOLD
Figure 11. Read Cycle
If the internal reference is used and R/W = 0, shutdown
occurs when the master issues a not-acknowledge bit
while reading the conversion results. The internal reference and internal reference buffer are disabled during
shutdown, reducing the analog supply current to less
than 1μA.
A dummy conversion is required to power up the internal reference. The MAX1169 internal reference begins
powering up from shutdown on the 9th falling edge of a
16
valid address byte. Allow 12ms for the internal reference to settle before obtaining valid conversion results.
Reference Voltage
The MAX1169 provides an internal or accepts an external reference voltage. The ADC input range is from
VAGNDS to VREF. (See the Transfer Function section.)
______________________________________________________________________________________
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
MAX1169
Internal Reference
The MAX1169 contains an internal 4.096V bandgap reference. This bandgap reference is connected to
REFADJ through a 5kΩ resistor. Bypass REFADJ with a
0.1μF capacitor to AGND. The MAX1169 reference
buffer has a unity gain to provide +4.096V at REF.
Bypass REF with a 10μF capacitor to AGND when the
internal reference is used (Figure 12).
REF 13
4.096V
SAR
REF
ADC
10μF
AV = 1.0
REFADJ 12
MAX1169
The internal reference is adjustable to ±1.5% using the
circuit of Figure 13.
0.1μF
5kΩ
4.096V
BANDGAP
REFERENCE
External Reference
For external reference operation, disable the internal
reference by connecting REFADJ to AVDD. During conversion, an external reference at REF must deliver up to
100μA of DC load current and have an output impedance of less than 10Ω.
DGND
1
For optimal performance, buffer the reference through
an op amp and bypass REF with a 10μF capacitor.
Consider the MAX1169’s equivalent input noise
(38μVRMS) when choosing a reference.
AGND
9
Figure 12. Internal Reference
Transfer Function
LSB values. Figure 14 shows the MAX1169 input/output
(I/O) transfer function.
The MAX1169 has a standard unipolar transfer function
with a valid analog input voltage range from VAGNDS to
V REF . Output data coding is binary with 1LSB =
(VREF/2N) where N is the number of bits (16). Code
transitions occur halfway between successive-integer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multiplexed, the input channel should be switched immediately after acquisition, rather than near the end of or
Input Buffer
5.0V
AVDD
8
MAX1169
0.1μF
REF 13
4.096V
SAR
REF
ADC
10μF
AV = 1.0
REFADJ 12
68kΩ
100kΩ
POTENTIOMETER
0.1μF
5kΩ
4.096V
BANDGAP
REFERENCE
150kΩ
DGND
1
AGND
9
Figure 13. Adjusting the Internal Reference
______________________________________________________________________________________
17
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
1...111
1...110
1...101
1...100
VREF
BINARY OUTPUT CODE (LSB)
VREF
V
1LSB = REF
65536
0...011
0...010
0...001
0...000
0 1 2 3
grounds to the star analog ground. Connect the digital
grounds to the star digital ground. Connect the digital
ground plane to the analog ground plane at one point.
For lowest noise operation, make the ground return to
the star ground’s power supply low impedance and as
short as possible.
High-frequency noise in the AV DD power supply
degrades the ADC’s high-speed comparator performance. Bypass AVDD to AGND with a 0.1μF ceramic
surface-mount capacitor. Make bypass capacitor connections as short as possible. If the power supply is
very noisy, connect a 10Ω resistor in series with AVDD
and a 4.7μF capacitor from AVDD to AGND to create a
lowpass RC filter.
Definitions
65533 65535
INPUT VOLTAGE (LSB)
AGNDS
Figure 14. Unipolar Transfer Function
after a conversion. This allows more time for the input
buffer amplifier to respond to a large step-change in
input signal. The input amplifier must have a high
enough slew rate to complete the required output voltage change before the beginning of the acquisition
time. At the beginning of acquisition, the internal sampling capacitor array connects to AIN (the amplifier output), causing some output disturbance.
Ensure that the sampled voltage has settled to within
the required limits before the end of the acquisition
time. If the frequency of interest is low, AIN can be
bypassed with a large enough capacitor to charge the
internal sampling capacitor with very little ripple.
However, for AC use, AIN must be driven by a wideband buffer (at least 4MHz), which must be stable with
the ADC’s capacitive load (in parallel with any AIN
bypass capacitor used) and also settle quickly. Refer to
Maxim’s website at www.maxim-ic.com for application
notes on how to choose the optimum buffer amplifier for
your ADC application.
Layout, Grounding, and Bypassing
Careful printed circuit (PC) board layout is essential for
the best system performance. Boards should have separate analog and digital ground planes and ensure that
digital and analog signals are separated from each
other. Do not run analog and digital (especially clock)
lines parallel to one another, or digital lines underneath
the device package.
Figure 4 shows the recommended system ground connections. Establish an analog ground point at AGND
and a digital ground point at DGND. Connect all analog
18
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function
once offset and gain errors have been nullified. The
MAX1169 INL is measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples (Figure 11).
Aperture Delay
Aperture delay (tAD) is the time from the falling edge of
SCL to the instant when an actual sample is taken
(Figure 11).
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = ((6.02 ✕ N) + 1.76) dB
In reality, noise sources besides quantization noise
exist, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
______________________________________________________________________________________
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
⎛ Signal RMS ⎞
SINAD(db) = 20 × log ⎜
⎟
⎝ Noise RMS ⎠
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
⎛ SINAD - 1.76 ⎞
ENOB = ⎜
⎟⎠
⎝
6. 02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fundamental itself, expressed as:
⎛
THD = 20 × log ⎜
⎜
⎝
Chip Information
TRANSISTOR COUNT: 18,269
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
14 TSSOP
U14-1
21-0066
V2 2 +V3 2 +V4 2 +V5 2 ⎞
⎟
V1
⎟
⎠
______________________________________________________________________________________
19
MAX1169
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals:
MAX1169
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/02
Initial release
1
12/09
Updated Ordering Information and Electrical Characteristics.
DESCRIPTION
PAGES
CHANGED
—
1, 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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