AD ADG790 Low voltage, cmos multimedia switch Datasheet

Low Voltage, CMOS Multimedia Switch
ADG790
Single-chip audio/video/data switching solution
Wide bandwidth section
Rail-to-rail signal switching capability
Compliant with full speed USB 2.0 signaling (3.6 V p-p)
Compliant with high speed USB 2.0 signaling (400 mV p-p)
Supports USB data rates up to 480 Mbps
550 MHz, 3 dB bandwidth
Low RON: 5.9 Ω typical
Excellent matching between channels
Low distortion section
Low RON: 3.9 Ω typical
230 MHz, 3 dB bandwidth (SPDT)
160 MHz, 3 dB bandwidth (4:1 multiplexers)
Single-supply operation: 1.65 V to 3.6 V
Typical power consumption: <0.1 μW
Pb-free packaging: 30-ball WLCSP (3 mm × 2.5 mm)
FUNCTIONAL BLOCK DIAGRAM
ADG790
WIDE
BANDWIDTH
SECTION
LOW
DISTORTION
SECTION
S5A
S5B
S1A
S5C
S1B
S5D
D1
D5
S2A
S6A
S2B
S6B
D2
S6C
S3A
S6D
S3B
D6
D3
S4A
S4B
D4
APPLICATIONS
Cellular phones
PMPs
MP3 players
Audio/video/data/USB switching
DECODER
VDD
IN1
IN2
IN3
S/D GND
06357-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The ADG790 is a single-chip, CMOS switching solution that
comprises four SPDT switches and two 4:1 multiplexers. The
internal architecture of the device provides two switching
sections, a wide bandwidth section and a low distortion section.
The wide bandwidth section contains three SPDT switches that
exhibit low on resistance with excellent flatness and channel
matching. This, combined with wide bandwidth, makes the
three-SPDT-switch configuration ideal for high frequency
signals, such as full speed (12 Mbps) and high speed (480 Mbps)
USB signals and high resolution video signals.
The low distortion section contains a single SPDT switch and
two 4:1 multiplexers that exhibit very low on resistance and
excellent flatness, making these switches ideal for a wide range
of applications, including low distortion audio applications and
low resolution video (CVBS and S-Video) applications.
All switches conduct equally well in both directions when on
and block signals up to the supply rails when off. A 4-wire
parallel interface controls the operation of the device and
allows the user to control switches from both sections simultaneously. This simplifies the design and provides a cost-effective,
single-chip switching solution for portable devices where
multiple signals share a single port connector. The shutdown
(S/D) pin allows the user to disable all four SPDT switches and
force the 4:1 multiplexers into the S5B and S6B positions,
respectively.
The ADG790 is packaged in a compact, 30-ball WLCSP (6 × 5
ball array) with a total area of 7.5 mm2 (3 mm × 2.5 mm). This
tiny package size and its low power consumption make the
ADG790 an ideal solution for portable devices.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADG790
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits..................................................................................... 11
Applications....................................................................................... 1
Theory of Operation ...................................................................... 13
Functional Block Diagram .............................................................. 1
Wide Bandwidth Section........................................................... 13
General Description ......................................................................... 1
Low Distortion Section.............................................................. 13
Revision History ............................................................................... 2
Control Interface ........................................................................ 13
Specifications..................................................................................... 3
Evaluation Board ............................................................................ 14
Absolute Maximum Ratings............................................................ 5
Using the ADG790 Evaluation Board ..................................... 14
ESD Caution.................................................................................. 5
Outline Dimensions ....................................................................... 17
Pin Configuration and Function Descriptions............................. 6
Ordering Guide .......................................................................... 17
Terminology ...................................................................................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
1/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG790
SPECIFICATIONS
VDD = 2.7 V to 3.6 V, GND = 0 V, TA = –40°C to +85°C, all switch sections unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance
On Resistance Flatness
On Resistance Matching
Between Channels 4
Symbol
Test Conditions/Comments
RON
VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18)
Wide bandwidth section 2
Low distortion section 3
VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA (see Figure 18)
Wide bandwidth section2
Low distortion section3
VDD = 2.7 V, VS = 0 V to VDD, IDS = 10 mA
Min
Typ 1
Max
Unit
VDD
V
5.9
3.9
8.8
5.5
Ω
Ω
2.0
0.74
3.6
1.6
Ω
Ω
0.52
0.1
0.3
Ω
Ω
Ω
0
RFLAT(ON)
∆RON
Wide bandwidth section2
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
LEAKAGE CURRENTS
Source Off Leakage
Channel On Leakage
DIGITAL INPUTS (IN1, IN2, IN3, S/D)
Input High Voltage
Input Low Voltage
Input High/Input Low Current
Digital Input Capacitance
DYNAMIC CHARACTERISTICS 5
tON
tOFF
Propagation Delay
Propagation Delay Skew
Break-Before-Make Time Delay
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion
–3 dB Bandwidth
Differential Gain Error
IS (OFF)
ID, IS (ON)
VINH
VINL
IINL, IINH
CIN
tON
tOFF
tD
tSKEW
tBBM
QINJ
THD + N
VDD = 3.6 V, VS = 0 V or 3.6 V, VD = 3.6 V or 0 V
(see Figure 19)
VDD = 3.6 V, VS = VD = 0 V or 3.6 V (see Figure 20)
±10
±10
nA
nA
2.0
0.8
±0.1
V
V
μA
pF
VIN = VINL or VINH
±0.005
6
RL = 50 Ω, CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24)
RL = 50 Ω, CL = 35 pF, VS = VDD/2 or 0 V (see Figure 24)
RL = 50 Ω, CL = 35 pF
Wide bandwidth section2
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
RL = 50 Ω, CL = 35 pF
Wide bandwidth section2
Low distortion section3 (4:1 multiplexers)
RL = 50 Ω, CL = 35 pF, VS1 = VS2 = VDD/2 (see Figure 25)
VS = 0 V, RS = 0 Ω, CL = 1 nF (see Figure 26)
Wide bandwidth section2
Low distortion section3
RL = 50 Ω, CL = 5 pF, f = 1 MHz (see Figure 21)
RL = 50 Ω, CL = 5 pF, f = 1 MHz (see Figure 22)
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p
Wide bandwidth section2
Low distortion section3
RL = 50 Ω, CL = 5 pF (see Figure 23)
Wide bandwidth section2
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
CCIR330 test signal
Wide bandwidth section2
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
20
9
32
15
ns
ns
0.3
0.65
0.4
0.46
0.95
0.65
ns
ns
ns
Rev. 0 | Page 3 of 20
5
20
40
11
ps
ps
ns
–0.57
6.2
–74
–77
pC
pC
dB
dB
1.2
0.65
%
%
550
230
160
MHz
MHz
MHz
0.07
0.08
0.18
%
%
%
ADG790
Parameter
Differential Phase Error
Symbol
Power Supply Rejection Ratio
Source Off Capacitance
PSRR
CS (OFF)
Drain Off Capacitance
CD (OFF)
Source/Drain On Capacitance
CD, CS (ON)
POWER REQUIREMENTS
Supply Voltage
Supply Current
VDD
IDD
Test Conditions/Comments
CCIR330 test signal
Wide bandwidth section2
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
f= 10 kHz, no decoupling capacitors
Wide bandwidth section2
Low distortion section3
Wide bandwidth section2
Low distortion section3 (SPDT)
Wide bandwidth section2
Low distortion section3 (SPDT)
Low distortion section3 (4:1 multiplexers)
Min
Typ 1
0.13
0.08
0.19
–90
3.5
11
5.5
14
8.5
19
32
1.65
VDD = 3.6 V, digital inputs tied to 0 V or 3.6 V
1
Max
0.1
Unit
Degrees
Degrees
Degrees
dB
pF
pF
pF
pF
pF
pF
pF
3.6
1
V
μA
All typical values are at TA = 25°C, VDD = 3.3 V.
Refers to all switches connected to Pin D1, Pin D2, and Pin D3.
3
Refers to all switches connected to Pin D4 (SPDT), Pin D5, and Pin D6 (4:1 multiplexers).
4
Refers to the on resistance matching between the same channels (SxA and SxB, for example) from different multiplexers for the wide bandwidth section and the 4:1
multiplexers from the low distortion section. For the SPDT switch from the low distortion section, it refers to the matching between the S4A and S4B channels.
5
Guaranteed by design; not subject to production test.
2
Rev. 0 | Page 4 of 20
ADG790
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 2.
Parameter
VDD to GND
Analog and Digital Pins1
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Thermal Impedance (θJA)2
Reflow Soldering (Pb Free)
Peak Temperature
Time at Peak Temperature
Rating
–0.3 V to +4.6 V
–0.3 V to VDD + 0.3 V or 10 mA,
whichever occurs first
100 mA (pulsed at 1 ms, 10%
duty cycle maximum)
30 mA
–40°C to +85°C
–65°C to +125°C
150°C
80°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
260°C (+0°C/–5°C)
As per JEDEC J-STD-20
1
Overvoltages at IN, S, or D are clamped by internal diodes. Limit current to
the maximum ratings given.
2
Measured with the device soldered on a 4-layer board.
Rev. 0 | Page 5 of 20
ADG790
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
A
S1A
S5A
D5
S5C
S4A
B
D1
S5B
IN1
S5D
D4
C
S1B
GND
IN2
VDD
S4B
D
S2B
GND
IN3
GND
S3B
E
D2
S6B
S/D
S6D
D3
F
S2A
S6A
D6
S6C
S3A
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
06357-002
BALL A1
CORNER
Figure 2. 30-Ball WLCSP (CB-30-1)
Table 3. Pin Function Descriptions
Ball Name
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
F1
F2
F3
F4
F5
Mnemonic
S1A
S5A
D5
S5C
S4A
D1
S5B
IN1
S5D
D4
S1B
GND
IN2
VDD
S4B
S2B
GND
IN3
GND
S3B
D2
S6B
S/D
S6D
D3
S2A
S6A
D6
S6C
S3A
Description
Source Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 4 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Logic Control Input.
Source Terminal for Mux 5 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 4 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 1 (Wide Bandwidth Section). Can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Most Positive Power Supply Terminal.
Source Terminal for Mux 4 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output.
Ground (0 V) Reference.
Logic Control Input.
Ground (0 V) Reference.
Source Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output.
Drain Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Shutdown Logic Control Input.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 2 (Wide Bandwidth Section). Can be an input or an output.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Drain Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 6 (Low Distortion Section). Can be an input or an output.
Source Terminal for Mux 3 (Wide Bandwidth Section). Can be an input or an output.
Rev. 0 | Page 6 of 20
ADG790
TERMINOLOGY
IDD
tD
Positive supply current.
Signal propagation delay through the switch measured
between the 50% points of the input signal and its corresponding output signal.
VD (VS)
Analog voltage on Terminal D and Terminal S.
tSKEW
RON
Difference in propagation delay between the selected inputs on
the 4:1 multiplexers or any two SPDT switches from the wide
bandwidth section.
Ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
Charge Injection
ΔRON
A measure of the glitch impulse transferred from the digital
input to the analog output during on-off switching.
On resistance match between any two channels.
Off Isolation
IS (OFF)
A measure of unwanted signal coupling through an off switch.
Source leakage current with the switch off.
Crosstalk
ID, IS (ON)
Channel leakage current with the switch on.
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
−3 dB Bandwidth
Maximum input voltage for Logic 0.
The frequency at which the output is attenuated by 3 dB.
VINH
Insertion Loss
Minimum input voltage for Logic 1.
The loss due to the on resistance of the switch.
IINL (IINH)
THD + N
Input current of the digital input.
The ratio of the harmonic amplitudes plus signal noise to the
fundamental.
CS (OFF)
Differential Gain Error
The measure of how much color saturation shift occurs when
the luminance level changes. Both attenuation and amplification
can occur; therefore, the largest amplitude change between any
two levels is specified and expressed in percent.
Off switch source capacitance. Measured with reference
to ground.
CD, CS (ON)
On switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tON
Delay time between the 50% and the 90% points of the digital
input and switch on condition.
Differential Phase Error
The measure of how much hue shift occurs when the luminance
level changes. It can be a negative or a positive value and is
expressed in degrees of subcarrier phase.
tOFF
Delay time between the 50% and the 10% points of the digital
input and switch off condition.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to the other.
Rev. 0 | Page 7 of 20
ADG790
TYPICAL PERFORMANCE CHARACTERISTICS
7.5
4.5
TA = 25°C
IDS = 10mA
7.0
VDD = 3.3V
IDS = 10mA
4.3
4.1
VDD = 2.7V
3.9
3.7
6.0
RON (Ω)
RON (Ω)
6.5
5.5
3.5
TA = +85°C
3.3
VDD = 3.3V
5.0
3.1
2.9
VDD = 3.6V
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
2.7
2.5
3.5
TA = +25°C
TA = –40°C
0
0.5
1.0
1.5
2.0
2.5
06357-042
06357-039
4.5
3.0
VS (V)
VS (V)
Figure 3. On Resistance vs. Source Voltage,
Wide Bandwidth Section
Figure 6. On Resistance vs. Temperature,
Low Distortion Section
6.5
VDD = 3.3V
IDS = 10mA
20
tOFF
18
6.0
16
TA = +85°C
5.0
12
10
tON
8
4.5
06357-040
TA = +25°C
TA = –40°C
4.0
14
0
0.5
1.0
1.5
2.0
2.5
4
–40
3.0
–20
VS (V)
TA = 25°C
IDS = 10mA
VDD = 2.7V
40
60
80
–1
ATTENUATION (dB)
4.0
3.5
VDD = 3.3V
VDD = 3.3V
TA = 25°C
WIDE BANDWIDTH SECTION
–5
LOW DISTORTION SECTION
–7
–9
–11
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
–13
–15
0.01
3.5
VS (V)
06357-029
VDD = 3.6V
06357-041
RON (Ω)
20
Figure 7. tON/tOFF Times vs. Temperature
–3
2.5
0
TEMPERATURE (°C)
Figure 4. On Resistance vs. Temperature,
Wide Bandwidth Section
4.5
VDD = 3.3V
TA = 25°C
RL = 50Ω
CL = 35pF
6
06357-028
tON/tOFF (ns)
RON (Ω)
5.5
0.1
1
10
100
FREQUENCY (MHz)
Figure 5. On Resistance vs. Source Voltage,
Low Distortion Section
Figure 8. On Response vs. Frequency,
Low Distortion Section (SPDT)
Rev. 0 | Page 8 of 20
1000
ADG790
0
–10
–2
VDD = 3.3V
TA = 25°C
–30
ATTENUATION (dB)
–6
–8
–10
–12
–14
–16
–40
–50
–60
–70
–80
1
10
100
06357-033
06357-030
0.1
–100
–110
0.0001
1000
FREQUENCY (MHz)
0.001
0.01
0.1
1
10
100
1000
100
1000
FREQUENCY (MHz)
Figure 12. Off Isolation vs. Frequency
Figure 9. On Response vs. Frequency,
Low Distortion Section (4:1 Multiplexers)
ATTENUATION (dB)
–20
VDD = 3.3V
–30 TA = 25°C
WIDE BANDWIDTH AND
LOW DISTORTION SECTIONS
–40
INPUT SIGNAL = 0dBm
DC BIAS = 0.5V
–50
–60
–70
–80
–90
06357-034
–100
–110
06357-021
–120
0.0001
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
X = 20ns/DIV Y = 835mV/DIV
Figure 13. Crosstalk vs. Frequency
Figure 10. USB 1.1 Eye Diagram
1.3
1.2
WIDE BANDWIDTH SECTION
1.1
THD + N (%)
1.0
VDD = 3.3V
RL = 32Ω
VS = 2V p-p
TA = 25°C
DC BIAS = 1.65V
0.9
0.8
0.7
0.6
0.5
10
LOW DISTORTION SECTION
100
1000
10000
FREQUENCY (Hz)
X = 250ps/DIV Y = 100mV/DIV
Figure 14. THD + N vs. Frequency
Figure 11. USB 2.0 Eye Diagram
Rev. 0 | Page 9 of 20
06357-035
–20
0.01
VDD = 3.3V
TA = 25°C
WIDE BANDWIDTH AND LOW
DISTORTION SECTIONS
–90
–18
06357-022
ATTENUATION (dB)
–4
–20
100000
ADG790
500
0
VDD = 3.3V
TA = 25°C
450
–20
400
–40
300
PSRR (dB)
250
200
–80
150
100
06357-036
–100
50
0
0
0.5
1.0
1.5
2.0
2.5
–120
0.0001
3.0
VIN (V)
LOW DISTORTION
SECTION
6
4
3
VDD = 3.3V
CL = 1nF
TA = 25°C
WIDE BANDWIDTH
SECTION
1
0
06357-037
QINJ (pC)
5
2
0
0.5
1.0
1.5
0.01
0.1
1
10
100
Figure 17. Power Supply Rejection Ratio vs. Frequency
8
7
0.001
FREQUENCY (MHz)
Figure 15. Supply Current vs. Input Logic Level
–1
–60
06357-038
IDD (µA)
350
VDD = 3.3V
TA = 25°C
WIDE BANDWIDTH AND LOW
DISTORTION SECTIONS.
0dBm SIGNAL SUPERIMPOSED
ON SUPPLY VOLTAGE.
NO DECOUPLING CAPACITORS
USED.
2.0
2.5
3.0
VS (V)
Figure 16. Charge Injection vs. Source Voltage
Rev. 0 | Page 10 of 20
1000
ADG790
TEST CIRCUITS
VDD
IDS
0.1µF
NETWORK
ANALYZER
V1
S
VOUT
D
06357-003
RON = V1/IDS
VS
VDD
SxA
RL
50Ω
Dx
SxB
50Ω
VS
RL
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
A
S
D
ID (OFF)
VS
Figure 22. Channel-to-Channel Crosstalk
A
VD
06357-004
VS
VOUT
0.1µF
VDD
NETWORK
ANALYZER
VDD
Figure 19. Off Leakage
SxB
S
NC
D
RL
50Ω
A
06357-005
GND
NC = NO CONNECT
INSERTION LOSS = 20 log
Figure 20. On Leakage
VDD
NETWORK
ANALYZER
VDD
SxA
50Ω
50Ω
VS
Dx
RL
50Ω
GND
VOUT
VS
NC = NO CONNECT
06357-009
OFF ISOLATION = 20 log
VOUT
Figure 21. Off Isolation
Rev. 0 | Page 11 of 20
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 23. –3 dB Bandwidth
0.1µF
SxB
VS
Dx
ID (ON)
VD
NC
50Ω
SxA
06357-011
IS (OFF)
06357-010
Figure 18. On Resistance
ADG790
VDD
0.1µF
VIN
VS
50%
VOUT
Dx
SxB
RL
50Ω
INx
CL
35pF
50%
90%
10%
VOUT
tOFF
tON
GND
06357-006
VDD
SxA
Figure 24. Switching Times (tON, tOFF)
VDD
0.1µF
VDD
SxA
VIN
VOUT
Dx
SxB
VS
RL
50Ω
INx
CL
35pF
50%
0V
VS
50%
80%
80%
VOUT
tBBM
tBBM
06357-007
GND
Figure 25. Break-Before-Make Time Delay (tBBM)
VDD
0.1µF
VDD
Dx
VS
SxB TO Dx ON
SxA
SxB
NC
CL
1nF
INx
VIN
SxB TO Dx OFF
VOUT
VOUT
ΔVOUT
QINJ = CL × ΔVOUT
06357-008
GND
NC = NO CONNECT
Figure 26. Charge Injection
Rev. 0 | Page 12 of 20
ADG790
THEORY OF OPERATION
The ADG790 is a single-chip, CMOS switching solution that
comprises four SPDT switches and two 4:1 multiplexers. The
internal architecture used by the device groups the switches into
two sections, each optimized to provide the best performance in
terms of bandwidth and distortion. The on-chip parallel
interface controls the operation of all switches, allowing the
user to control switches from both sections simultaneously.
resistance and flatness while maintaining a wide bandwidth that
makes them suitable for a wide range of applications, including
low distortion audio and standard definition video signals. The
channels from the 4:1 multiplexers are matched to provide
optimal performance when used with differential signals such
as S-Video.
WIDE BANDWIDTH SECTION
The operation of the ADG790 is controlled via a 4-wire parallel
interface. The logic levels applied to the IN1, IN2, and IN3 pins
control the operation of the switches from both the wide bandwidth and low distortion sections, as shown in Table 4. The
shutdown pin (S/D) allows the user to disable all four SPDT
switches and force the 4:1 multiplexers into the S5B and S6B
positions, respectively. This function can be used to set up a low
speed communication protocol between the circuitry from both
sides of the device, which allows automatic configuration of the
switching function.
The wide bandwidth section contains three SPDT switches
S1A/S1B-D1, S2A/S2B-D2, and S3A/S3B-D3. These switches
use a CMOS topology that ensures, besides low on resistance
and excellent flatness, the ability to switch signals up to the
supply rails. This, combined with the low switch capacitance,
provides the wide bandwidth required when switching high
frequency signals. The three SPDT switches are also optimized
to provide low propagation delay and excellent matching
between the channels, making the ADG790 ideal for applications that use multiple signals, such as universal USB switches
(full and high speed), or RGB video signals, such as VGA.
LOW DISTORTION SECTION
The low distortion section contains a single SPDT switch
(S4A/S4B-D4) and two 4:1 multiplexers (S5A/S5B/S5C/S5D-D5
and S6A/S6B/S6C/S6D-D6, respectively). The switches from
this section also use a CMOS topology that exhibits very low on
CONTROL INTERFACE
For example, in modern handset applications, where a single
connector is used as a multifunction communication port, the
S5B-D5 and S6B-D6 configuration obtained by setting the S/D
pin high can be used to detect the type of peripheral device
connected to the handset. The ADG790 then automatically routes
the required signals to the communication port connector.
Table 4. Truth Table
Logic Control Inputs
S/D
1
0
0
0
0
0
0
0
0
1
IN1
X1
0
0
0
0
1
1
1
1
IN2
X1
0
0
1
1
0
0
1
1
IN3
X1
0
1
0
1
0
1
0
1
Switch Status
S1A-D1
S2A-D2
S3A-D3
S5D-D5
S6D-D6
Off
Off
On
Off
Off
Off
On
Off
Off
S1B-D1
S2B-D2
S3B-D3
Off
On
Off
On
On
On
Off
On
On
S4A-D4
Off
Off
On
On
On
On
Off
Off
Off
X = logic state doesn’t matter.
Rev. 0 | Page 13 of 20
S4B-D4
Off
On
Off
Off
Off
Off
On
On
On
S5A-D5
S6A-D6
Off
Off
Off
Off
Off
On
Off
On
Off
S5B-D5
S6B-D6
On
Off
Off
On
Off
Off
Off
Off
On
S5C-D5
S6C-D6
Off
On
Off
Off
On
Off
Off
Off
Off
ADG790
EVALUATION BOARD
The ADG790 evaluation board allows designers to evaluate the
high performance of the device with a minimum of effort.
The EVAL-ADG790 includes a printed circuit board populated
with the ADG790; it can be used to evaluate the performance of
the device. It interfaces to the USB port of a PC, allowing the user
to easily program the ADG790 through the USB port using the
software provided with the board. Schematics of the evaluation
board are shown in Figure 27 and Figure 28. The software runs
on any PC that has Microsoft® Windows® 2000 or Windows®
XP installed.
USING THE ADG790 EVALUATION BOARD
The ADG790 evaluation board is a test system designed to
simplify the evaluation of the device. Each input/output of the
part comes with a standardized socket to allow connection to
and from USB, CVBS, S-Video, and VGA signal sources. A data
sheet for the ADG790 evaluation board is also available with
full information on setup and operation.
Rev. 0 | Page 14 of 20
Figure 27. EVAL-ADG790 Schematic
USB Controller Section
C1
+ 10µF
R4
100kΩ
DVDD
C2
0.1µF
C3
0.1µF
R5
100kΩ
DVDD
R7
10kΩ
+
40
RDY1/*SLWR
XTALIN 5
XTALOUT
4
C12
12pF
A0
A1
A2
A3
24LC64
C14
0.1µF
8
7
6
5
SHIELD
USB-MINI-B
J14
VBUS
D–
D+
IO
GND
R9
2.2kΩ
R8
2.2kΩ
DVDD DVDD DVDD
C13
12pF
U3
1 A0 V
CC
2
A1 WP
3
SCL
A2
4
VSS SDA
Y1
24MHz
DVDD
C5
C6
C7
C8
C9
C10
C11
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
DVDD
6
AGND
13
IFCLK
14 RESERVED
DMINUS 98
DPLUS
PA7/*FLAGD/SLCS
1
RDY0/*SLRD
2
16
15
18
19
20
21
22
23
24
25
45
46
47
48
49
50
51
52
U2
CY7C68013-56LFC
DVDD
PB0/FD0
PB1/FD1
PB2/FD2
42
PB3/FD3
44 RESET
PB4/FD4
*WAKEUP
PB5/FD5
PB6/FD6
54
CLKOUT
PB7/FD7
PD0/FD8
29
30 CTL0/*FLAGA PD1/FD9
31 CTL1/*FLAGB PD2/FD10
CTL2/*FLAGC PD3/FD11
PD4/FD12
PD5/FD13
33 PA0/ INT0
PD6/FD14
34
PD7/FD15
35 PA1/ INT1
PA2/*SLOE
36
37 PA3/*WU2
38 PA4/FIFOADR0
SDA
39 PA5/FIFOADR1
SCL
PA6/*PKTEND
AVCC
3
C4
2.2µF
R6
0Ω
7
11
17
27
32
43
55
VCC
GND
Rev. 0 | Page 15 of 20
10
12
26
28
41
53
56
DVDD
1
2
3
4
5
+
C15
10µF
5V USB
C16
0.1µF
4
U4
OUT
OUT
SD
ERR
GND NR
1
2
6
3
ADP3303AR-3.3
8
IN
7
IN
5
D1
R10
1kΩ
C17
0.1µF
+
GREEN
DVDD
C19
10µF
ADG790
06357-013
1
BOTTOM
2
TOP
3
J2
BOTTOM
2
TOP
3
GND
1
Figure 28. EVAL-ADG790 Schematic
Switch Section
Rev. 0 | Page 16 of 20
T13
VGAV_I
J7-14
4
3
1
2
3
4
S1A
U1
ADG790
D6
S3B
3
4
J7-8
J7-7
1
SVIDEOY_O
T17
4
3
1
MINI-DIN-4
T32
VDD
SH
SH
GND
D+
D–
T20
BOTTOM
2
TOP
3
MIC/CVBS_O
MIC/CVBS_O
IO1/VGAH/S-VIDEOY/TX_O
IO2/VGAV/S-VIDEOC/RX_O
IO1/VGAH/S-VIDEOY/TX_O
T30
T28
T26
T31
T29
T27
GND
1
CVBS_O
MIC_O
TX_O
RX_O
IO1_O
IO2_O
J5
PHONO_DUAL
J11
USB
USB2.OID
6
5
4
3
2
1
T19
IO1/VGAV/S-VIDEOC/RX_O
IO1/VGAH/S-VIDEOY/TX_O
USB2.OD+/VGAB_O
USB2.OD–/VGAG_O
USB2.OID/VGAR_O
IO2/VGAV/S-VIDEOC/RX_O
USB2.OID/VGAR_O
USBID_I
USB2.OD+/VGAB_O
2
J12
SVIDEOY_I
VBUS
USB2.OD–/VGAG_O
T18
IO2/VGAV/S-VIDEOC/RX_O
IO1/VGAH/S-VIDEOY/TX_O
MIC/CVBS_O
USB2.OID/VGAR_O
USB2.OD+/VGAB_O
USB2.OD–/VGAG_O
SVIDEOC_I
F3
A3
B5
E5
E1
B1
2
IO1/VGAH/S-VIDEOY/TX_O
T16
SVIDEOC_O
R3
75Ω
T15
R2
75Ω
T14
A3 A2 A1 A0
IN1 IN2 IN3 S/D
B3 C3 D3 E3
S6D
S6C
S6B
S6A
S5D
S5C
S5B
S5A
S4B
S4A
D5
D4
S3A
D3
S2A
D2
D1
S2B
S1B
IO2/VGAV/S-VIDEOC/RX_O
2
1
MINI-DIN-4
E4
F4
E2
F2
B4
A4
B2
A2
C5
A5
D5
F5
D1
F1
C1
A1
J7-6
J6
VGAV_I
SVIDEOC_I
IO2_I
RX_I
VGAH_I
SVIDEOY_I
IO1_I
TX_I
CVBS_I
MIC_I
USBID_I
VGAR_I
USB2.OD+_I
VGAB_I
USB2.OD–_I
VGAG_I
T33
DVDD
J7-5
J7-4
VGAH_I
J7-13
VGAB_I
J7-3
T12
VGAG_I
J7-2
T9
T10
T11
USB2.OD+_I
USB2.OD–_I
VBUS
MIC_I
CVBS_I
R1
75Ω
RX_I
TX_I
VGAR_I
6
5
4
3
2
1
T7 T8
BOTTOM
2
TOP
3
T5 T6
T2 T4
IO2_I
IO1_I
J7-1
SH
SH
GND
D+
D–
VDD
J3
PHONO_DUAL
GND
J4
USB
J1
PHONO_DUAL
GND
1
T1 T3
C2
GND
D2
GND
D4
GND
VDD C4
PHONO_DUAL
T24
T25
2
J8
GND
1
2
J9
GND
1
TOP
3
BOTTOM
2
J10
GND
1
PHONO_DUAL
TOP
3
BOTTOM
J13-4
J13-5
J13-6
J13-7
J13-8
J13-14
PHONO_DUAL
TOP
3
BOTTOM
J13-3
J13-2
J13-1
J13-13
PHONO_DUAL
VSYNC_O
HSYNC_O
VGA B_O
VGA G_O
T21
T22
T23
VGA R_O
ADG790
06357-014
ADG790
OUTLINE DIMENSIONS
0.65
0.59
0.53
2.56
2.50
2.44
SEATING
PLANE
5
4
3
2
1
A
BALL A1
CORNER
B
0.36
0.32
0.28
3.06
3.00
2.94
C
D
E
0.50
BALL PITCH
0.28
0.24
0.20
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
092106- A
F
TOP VIEW
Figure 29. 30-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-30-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG790BCBZ-REEL 1
EVAL-ADG790EBZ1
1
Temperature Range
–40°C to +85°C
Package Description
30-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 17 of 20
Package Option
CB-30-1
ADG790
NOTES
Rev. 0 | Page 18 of 20
ADG790
NOTES
Rev. 0 | Page 19 of 20
ADG790
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06357-0-1/07(0)
Rev. 0 | Page 20 of 20