ON MC100H644 68030/040 pecl to ttl clock driver Datasheet

MC10H644, MC100H644
68030/040 PECL to TTL
Clock Driver
The MC10H/100H644 generates the necessary clocks for the
68030, 68040 and similar microprocessors. The device is functionally
equivalent to the H640, but with fewer outputs in a smaller outline
20−lead PLCC package. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of
part−to−part skew, within−part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced
to +5.0 V) for the input clock. TTL clocks are typically used in present
MPU systems. However, as clock speeds increase to 50 MHz and
beyond, the inherent superiority of ECL (particularly differential
ECL) as a means of clock signal distribution becomes increasingly
evident. The H644 also uses differential ECL internally to achieve its
superior skew characteristic.
The H644 includes divide−by−two and divide−by−four stages, both
to achieve the necessary duty cycle and skew to generate MPU clocks
as required. A typical 50 MHz processor application would use an
input clock running at 100 MHz, thus obtaining output clocks at
50 MHz and 25 MHz (see Logic Symbol).
The 10H version is compatible with MECL™ 10H ECL logic levels,
while the 100H version is compatible with 100K levels (referenced
to +5.0 V).
• Generates Clocks for 68030/040
• Meets 68030/040 Skew Requirements
• TTL or PECL Input Clock
• Extra TTL and ECL Power/Ground Pins
• Within Device Skew on Similar Paths is 0.5 ns
• Asynchronous Reset
• Single +5.0 V Supply
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MARKING
DIAGRAM
1
10H644
AWLYYWW
PLCC−20
FN SUFFIX
CASE 775
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC10H644FN
PLCC−20
37 Units/Rail
MC100H644FN
PLCC−20
37 Units/Rail
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q
outputs HIGH.
Synchronized Outputs: The device is designed to have the POS
edges of the ÷2 and ÷4 outputs synchronized.
Select (SEL): LOW selects the PECL input source (DE/DE). HIGH
selects the TTL input source (DT).
The H644 also contains circuitry to force a stable state of the PECL
input differential pair, should both sides be left open. In this case, the
DE side of the input is pulled LOW, and DE goes HIGH.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 6
1
Publication Order Number:
MC10H644/D
MC10H644, MC100H644
GT
19
Q3
Q4
VT
Q5
GT
R
18
17
16
15
14
Table 1. PIN DESCRIPTION
PIN
13
VE
20
12
DE
GT
1
11
VBB
Q2
2
10
DE
GT
3
9
GE
4
5
6
7
8
Q1
VT
Q0
SEL
DT
GT
VT
VE
GE
DE, DE
VBB
DT
Qn, Qn
SEL
R
FUNCTION
TTL Ground (0 V)
TTL VCC (+5.0 V)
ECL VCC (+5.0 V)
ECL Ground (0 V)
ECL Signal Input (positive ECL)
VBB Reference Output
TTL Signal Input
Signal Outputs (TTL)
Input Select (TTL)
Reset (TTL)
*Skews are specified for Identical Edges
Figure 1. Pinout: PLCC−20 (Top View)
TTL OUTPUTS
VBB
Q0
DE
(ECL)
DE
(ECL)
2:1 MUX
÷2
DT
(TTL)
Q1
Q2
Q3
SEL
(TTL)
÷4
R
(TTL)
Q4
Q5
Figure 2. Logic Diagram
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2
MC10H644, MC100H644
Table 2. 10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
Characteristic
Condition
Min
25°C
Max
255
Min
85°C
Max
Max
Unit
175
mA
IINH
IINL
Input HIGH Current
Input LOW Current
VIH*
VIL*
Input HIGH Voltage
Input LOW Voltage
VE = 5.0 V
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
3.55
V
VBB*
Output Reference Voltage
VE = 5.0 V
3.62
3.73
3.65
3.75
3.69
3.81
V
0.5
175
Min
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 3. 100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
Characteristic
Condition
Min
25°C
Max
255
Min
85°C
Max
Max
Unit
175
mA
IINH
IINL
Input HIGH Current
Input LOW Current
VIH*
VIL*
Input HIGH Voltage
Input LOW Voltage
VE = 5.0 V
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
3.835
3.19
4.12
3.525
V
VBB*
Output Reference Voltage
VE = 5.0 V
3.62
3.74
3.62
3.74
3.62
3.74
V
0.5
175
Min
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0 V.
Only corresponds to ECL Clock Inputs.
Table 4. DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
IEE
Characteristic
Power Supply Current
ICC
Condition
Min
25°C
Max
Min
85°C
Max
Min
Max
Unit
ECL
VE Pin
65
65
65
mA
TTL
Total all VT pins
85
85
85
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 5. TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
Characteristic
Condition
Min
2.0
25°C
Max
Min
Max
Min
Unit
Input HIGH Voltage
Input LOW Voltage
IIH
Input HIGH Current
VIN = 2.7 V
VIN = 7.0 V
20
100
20
100
20
100
mA
IIL
Input LOW Current
VIN = 0.5 V
−0.6
−0.6
−0.6
mA
VOH
Output HIGH Voltage
IOH = −3.0 mA
IOH = −24 mA
VOL
Output LOW Voltage
IOL = 24 mA
0.5
0.5
0.5
V
VIK
Input Clamp Voltage
IIN = −18 mA
−1.2
−1.2
−1.2
V
IOS
Output Short Circuit Current
−225
mA
VOUT = 0 V
2.5
2.0
−100
0.8
2.5
2.0
−225
−100
2.0
Max
VIH
VIL
0.8
2.0
85°C
0.8
2.5
2.0
−225
−100
V
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC10H644, MC100H644
Table 6. AC CHARACTERISTICS (VT = VE = 5.0 V ±5%)
0°C
Symbol
Characteristic
All Outputs
25°C
85°C
Condition
Min
Max
Min
Max
Min
Max
Unit
CL = 50 pF
5.8
6.8
5.7
6.7
6.1
7.1
ns
CL = 50 pF
5.7
6.7
5.7
6.7
6.0
7.0
ns
tPLH
Propagation Delay ECL
D to Output
tPLH
Propagation Delay TTL
D to Output
tskwd*
Within−Device Skew
Q0, 1, 4, 5
CL = 50 pF
−
0.5
−
0.5
−
0.5
ns
tskwd*
Within−Device Skew
Q2, Q3
CL = 50 pF
−
0.5
−
0.5
−
0.5
ns
tskwd*
Within−Device Skew
All Outputs
CL = 50 pF
−
1.5
−
1.5
−
1.5
ns
tskp−p*
Part−to−Part Skew
Q0, 1, 4, 5
CL = 50 pF
−
1.0
−
1.0
−
1.0
ns
tPD
Propagation Delay
R to Output
All Outputs
CL = 50 pF
4.3
7.3
4.3
7.3
4.5
7.5
ns
tR
tF
Output Rise/Fall Time
0.8 V − 2.0 V
All Outputs
CL = 50 pF
−
1.6
−
1.6
−
1.6
ns
fmax
Maximum Input Frequency
CL = 50 pF
135
−
135
−
135
−
MHz
TW
Minimum Pulse Width Reset
1.5
−
1.5
−
1.5
−
ns
trr
Reset Recovery Time
1.25
−
1.25
−
1.25
−
ns
TPW
Pulse Width Out High or Low @ fin
= 100 MHz and CL = 50 pF
9.5
10.5
9.5
10.5
9.5
10.5
ns
TS
Setup Time
SEL to DE, DT
2.0
−
2.0
−
2.0
−
TH
Hold Time
SEL to DE, DT
2.0
−
2.0
−
2.0
−
Q0, 1
CL = 50 pF
Relative 1.5 V
ns
ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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MC10H644, MC100H644
PACKAGE DIMENSIONS
PLCC−20
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775−02
ISSUE D
0.007 (0.180) M T L−M
B
Y BRK
−N−
U
N
S
0.007 (0.180) M T L−M
S
S
N
S
D
−L−
−M−
Z
W
20
D
1
V
0.007 (0.180) M T L−M
S
N
S
R
0.007 (0.180) M T L−M
S
N
S
Z
G
J
H
PLANE
F
VIEW S
N
S
N
S
0.007 (0.180) M T L−M
S
N
S
K
0.004 (0.100)
−T− SEATING
VIEW S
S
T L−M
K1
E
G1
0.010 (0.250) S T L−M
S
VIEW D−D
A
C
0.010 (0.250)
G1
X
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS PLASTIC
BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300).
DIMENSIONS R AND U ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS,
GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037 (0.940).
THE DAMBAR INTRUSION(S) SHALL NOT CAUSE
THE H DIMENSION TO BE SMALLER THAN 0.025
(0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
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5
INCHES
MIN
MAX
0.385
0.395
0.385
0.395
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.350
0.356
0.350
0.356
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10 _
0.310
0.330
0.040
−−−
MILLIMETERS
MIN
MAX
9.78
10.03
9.78
10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10 _
7.88
8.38
1.02
−−−
0.007 (0.180) M T L−M
S
N
S
MC10H644, MC100H644
MECL is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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MC10H644/D