IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 1M x 16 HIGH-SPEED LOW POWER ASYNCHRONOUS CMOS STATIC RAM FEATURES • High-speed access times: 25, 35 ns • High-performance, low-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CS1 and OE options • CS1 power-down • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single power supply VDD 1.65V to 2.2V (IS62WV102416ALL) speed = 35ns for VDD 1.65V to 2.2V VDD 2.4V to 3.6V (IS62/65WV102416BLL) speed = 25ns for VDD 2.4V to 3.6V • Packages available: – 48-ball miniBGA (9mm x 11mm) – 48-pin TSOP (Type I) • Industrial and Automotive Temperature Support • Lead-free available • Data control for upper and lower bytes JANUARY 2008 DESCRIPTION The ISSI IS62WV102416ALL/BLL and IS65WV102416BLL are high-speed, 16M-bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The device is packaged in the JEDEC standard 48-pin TSOP Type I and 48-pin Mini BGA (9mm x 11mm). FUNCTIONAL BLOCK DIAGRAM A0-A19 DECODER 1024K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CS1 OE WE UB LB CONTROL CIRCUIT Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 1 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 1Mx16 LOW POWER PIN CONFIGURATIONS 48-Pin mini BGA (9mmx11mm) 1 2 3 4 5 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 A19 A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC PIN DESCRIPTIONS 2 A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1, CS2 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL 48-pin TSOP-I (12mm x 20mm) A4 A3 A2 A1 A0 NC CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A5 A6 A7 A8 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 PIN DESCRIPTIONS A0-A19 Address Inputs I/O0-I/O15 Data Inputs/Outputs CS1 Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 3 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL TRUTH TABLE I/O PIN I/O0-I/O7 I/O8-I/O15 WE CS1 CS2 OE LB UB Not Selected X X X H X X X L X X X X X X H X X H High-Z High-Z High-Z High-Z High-Z High-Z ISB1, ISB2 ISB1, ISB2 ISB1, ISB2 Output Disabled H H L L H H H H L X X L High-Z High-Z High-Z High-Z ICC ICC Read H H H L L L H H H L L L L H L H L L DOUT High-Z DOUT High-Z DOUT DOUT ICC Write L L L L L L H H H X X X L H L H L L DIN High-Z DIN High-Z DIN DIN ICC Mode VDD Current ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL OPERATING RANGE (VDD) (IS62WV102416ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD (35 nS) 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V OPERATING RANGE (VDD) (IS62WV102416BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (25 nS) 2.4V-3.6V 2.4V-3.6V Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. OPERATING RANGE (VDD) (IS65WV102416BLL) Range Automotive Ambient Temperature –40°C to +125°C VDD (25 nS) 2.4V-3.6V Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 5 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 1.8 — V VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V Vcc – 0.4V — V VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V VIH Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V VIL(1) Input LOW Voltage 1.65-2.2V –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Notes: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL AC TEST CONDITIONS (HIGH SPEED) Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0.4V to VDD-0.3V 1.5ns VDD/2 Unit (1.65V-2.2V) 0.4V to VDD-0.2V 1.5ns VDD/2 See Figures 1 and 2 See Figures 1 and 2 AC TEST LOADS 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 5 pF Including jig and scope 353 Ω Figure 2. 7 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions ICC VDD Dynamic Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX VIN = 0.4V or VDD –0.3V -25 Min. Max. Com. Ind. Auto. typ.(2) — — — -35 Min. Max. Unit 30 35 60 — — — 25 30 60 mA 25 ICC1 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 VIN = 0.4V or VDD –0.3V Com. Ind. Auto. — — — 20 30 50 — — — 20 30 50 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CS1 ≥ VIH, f = 0 Com. Ind. Auto. — — — 15 20 40 — — — 15 20 40 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CS1 ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 0.8 1.2 2 — — — 0.8 1.2 2 mA 0.1 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter 25 ns Min. Max. 35 ns Min. Max. Unit tRC Read Cycle Time 25 — 35 — ns tAA Address Access Time — 25 — 35 ns tOHA Output Hold Time 3 — 3 — ns tACS1/tACS2 CS1/CS2 Access Time — 25 — 35 ns tDOE OE Access Time — 12 — 15 ns (2) tHZOE OE to High-Z Output — 8 — 10 ns (2) tLZOE OE to Low-Z Output 5 — 5 — ns tHZCS1/tHZCS2(2) CS1/CS2 to High-Z Output 0 8 0 10 ns tLZCS1/tLZCS2(2) CS1/CS2 to Low-Z Output 10 — 10 — ns tBA LB, UB Access Time — 25 — 35 ns tHZB LB, UB to High-Z Output 0 8 0 10 ns tLZB LB, UB to Low-Z Output 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL) tRC ADDRESS tAA tOHA DQ0-D15 PREVIOUS DATA VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 tOHA DATA VALID 9 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled) tRC ADDRESS tAA tOHA OE tDOE CS1s tHZOE tLZOE tACE1/tACE2 CS2s tLZCE1/ tLZCE2 tHZCS1/ tHZCS1 LBs, UBs tBA tHZB tLZB DOUT HIGH-Z DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = VIL. CS2=WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW transition. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) Symbol tWC 25ns Min. Max. Parameter Write Cycle Time tSCS1/tSCS2 CS1/CS2 to Write End tAW Address Setup Time to Write End 35 ns Min. Max. Unit 25 — 35 — ns 18 — 25 — ns 15 — 25 — ns tHA tSA Address Hold from Write End 0 — 0 — ns Address Setup Time 0 — 0 — ns tPWB tPWE(4) LB, UB Valid to End of Write 18 — 25 — ns WE Pulse Width 18 — 30 — ns tSD tHD Data Setup to Write End 12 — 15 — ns Data Hold from Write End 0 — 0 — ns tHZWE(3) tLZWE(3) WE LOW to High-Z Output — 12 — 20 ns WE HIGH to Low-Z Output 5 — 5 — ns Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 to VDD-0.2V/0.4V to VDD-0.3V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 4. tPWE > tHZWE + tSD when OE is LOW. AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) tWC ADDRESS tHA tSCS1 CS1 tSCS2 CS2 tAW tPWE WE tPWB LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE). Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 11 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT tHZWE tLZWE HIGH-Z DATA UNDEFINED tSD DIN tHD DATA-IN VALID WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle) tWC ADDRESS OE tHA tSCS1 CS1 tSCS2 CS2 tAW t PWE WE LB, UB tSA DOUT DATA UNDEFINED tHZWE tLZWE HIGH-Z tSD DIN 12 tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL WRITE CYCLE NO. 4 (UB/LB Controlled) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CS1 LOW CS2 HIGH t HA t SA WE UB, LB t HA t PBW t PBW WORD 1 WORD 2 t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID UB_CSWR4.eps Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 13 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. VDR VDD for Data Retention See Data Retention Waveform 1.2 IDR Data Retention Current VDD = 1.2V, CS1 ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time See Data Retention Waveform Recovery Time See Data Retention Waveform Com. Ind. Auto. Typ.(1) Max. Unit 3.6 V 0.8 1.2 2 mA 0 — ns tRC — ns — — — 0.1 0.1 0.1 Note: 1. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CS1 Controlled) Data Retention Mode tSDR tRDR VDD 1.65V 1.4V VDR CS1 ≥ VDD - 0.2V CS1 GND DATA RETENTION WAVEFORM (CS2 Controlled) Data Retention Mode 3.0 VDD CE2 2.2V tSDR tRDR VDR 0.4V CS2 ≤ 0.2V GND 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL ORDERING INFORMATION Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 25 Order Part No. Package IS62WV102416BLL-25MI IS62WV102416BLL-25MLI IS62WV102416BLL-25TI IS62WV102416BLL-25TLI 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I) TSOP (Type I), Lead-free Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 35 Order Part No. Package IS62WV102416ALL-35MI IS62WV102416ALL-35MLI IS62WV102416ALL-35TI IS62WV102416ALL-35TLI 48 mini BGA (9mm x 11mm) 48 mini BGA (9mm x 11mm), Lead-free TSOP (Type I) TSOP (Type I), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 25 Order Part No. Package IS65WV102416BLL-25MA3 IS65WV102416BLL-25TA3 48 mini BGA (9mm x 11mm) TSOP (Type I) Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/18/08 15 PACKAGING INFORMATION Plastic TSOP - 48 pins Package Code: T (Type I) A A1 1 N E b e D1 SEATING PLANE D Lα Plastic TSOP (T - Type I) Millimeters Inches Symbol Min Max Min Max Ref. Std. N 48 A — 1.20 — 0.047 A1 0.05 0.15 0.002 0.006 b 0.17 0.27 0.007 0.011 C 0.10 0.21 0.004 0.008 D 19.8 20.2 0.780 0.795 D1 18.2 18.6 0.716 0.732 E 11.8 12.2 0.464 0.480 e 0.50 BSC 0.020 BSC L 0.50 0.70 0.020 0.028 α 0° 5° 0° 5° Integrated Silicon Solution, Inc. PK13197T48 Rev. B 07/17/97 C Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : 08/21/2008