IK Semicon IL6083 Pwm power control ic with interference suppression Datasheet

TECHNICAL DATA
PWM Power Control IC
with Interference Suppression
IL6083
Description
The designed IC is based on bipolar technology for the
control of an N-channel power MOSFET used as a high-side
switch. The IC is ideal for use in brightness control systems
(dimming) of lamps, for example, in dashboard applications.
Features
• Protection Against Short-circuit, Load Dump Overvoltage
and Reverse VS
• Duty Cycle 18 to 100% Continuously
• Internally Reduced Pulse Slope of Lamp's Voltage
• Interference and Damage Protection
• Charge-pump Noise Suppression
• Ground-wire Breakage Protection
IL6083N DIP-8
TA = –40 ~ +110°С
Pin Configuration
Figure 1.
Pin
01
02
03
04
05
06
07
08
Symbol
Vs
GND
Vi
Osc
Delay
Sense
2Vs
Output
Pin Description
Supply voltage
IC ground
Control input (duty cycle)
Oscillator
Short-circuit protection delay
Current sensing
Voltage doubler
Output
Rev. 00
IL6083
Block diagram with External Circuit
Figure 2.
Maximum and Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Parameter,
Symbol, Unit
Maximum Ratings
min
9.0
max
25
Supply voltage Vbatt, V
Storage temperature Tstg, oС
Ambient operation temperature range TA, oC
-40
+110
o
Junction maximum temperature TJ(max), C
Temperature resistance junction – ambient Rth j-a, =120oC/W
Absolute Maximum
Ratings
min
Max
32.5
-55
+125
-55
+125
+150
Rev. 00
IL6083
Functional Description
Pin 1, Supply Voltage, VS or VBatt
Overvoltage Detection
Stage 1
If overvoltages of VBatt > 20 V (typically) occur, the external transistor is switched off, and switched on again
at VBatt < 18.5 V (hysteresis).
Stage 2
If VBatt > 28.5 V (typically), the voltage limitation of the IC is reduced from VS = 26 V to 20 V. The gate of the
external transistor remains at the potential of the IC ground, thus producing voltage sharing between FET
and lamps in the event of overvoltage pulses (e.g. , load dump). The short - circuit protection is not in
operation.
At VBatt approximately < 23 V, the overvoltage detection stage 2 is switched off. Thus, during overvoltage
detection stage 2, the lamp voltage Vlamp is calculated as follows:
VLamp = VBatt - VS - VGS
VS = supply voltage of the IC at overvoltage detection stage 2
VGS = gate - source voltage of the FET
Undervoltage Detection
In the event of voltages of approximately VBatt < 5.0 V, the external FET is switched off and the latch for
short-circuit detection is reset.
A hysteresis ensures that the FET is switched on again at approximately VBatt ≥ 5.4 V.
Pin 2, GND
Ground-wire Breakage
To protect the FET in the case of ground-wire breakage, a 1 MΩ resistor between gate and source is
recommended to provide proper switch-off conditions.
Pin 3, Control Input
The pulse width is controlled by means of an external potentiometer (47 kΩ). The characteristic (angle of
rotation/duty cycle) is linear. The duty cycle can be varied from 18 to 100%. It is possible to further restrict
the duty cycle with the resistors R1 and R2 (see Figure 4).
In order to reduce the power dissipation of the FET and to increase the lifetime of the lamps, the IC
automatically reduces the maximum duty cycle at pin 8 if the supply voltage exceeds V2 = 13 V. Pin 3 is
protected against short-circuit to VBatt and ground (VBatt ≤ 16.5 V).
Pin 4, Oscillator
The oscillator determines the frequency of the output voltage. This is defined by an external capacitor, C2. It
is charged with a constant current, I, until the upper switching threshold is reached. A second current source
is then activated which taps a double current, 2 x I, from the charging current. The capacitor, C2, is thus
discharged at the current, I, until the lower switching threshold is reached. The second source is then
switched off again and the procedure starts once more.
Rev. 00
IL6083
Example for Oscillator
Frequency Calculation
Switching thresholds
VT100 = High switching threshold (100% duty cycle)
VT100 = VS x α 1 = (VBatt - IS x R3) x α 1
VT<100 = High switching threshold (< 100% duty cycle)
VT<100 = VS x α2 = (VBatt - IS x R3) x α 2
VTL = Low switching threshold
VTL = VS x α 3 = (VBatt - IS x R3) x α 3
where
α 1, α 2 and α 3 are fixed values
Calculation Example
The above mentioned threshold voltages are calculated for the following values given in the data sheet.
VBatt = 12 V, IS = 4 mA, R3 = 150 Ω, α 1 = 0.7, α 2 = 0.67 and α 3 = 0.28
VT100 = (12 V - 4 mA x 150 Ω) x 0.7 ≈ 8 V
VT<100 = 11.4 V x 0.67 = 7.6 V
VTL = 11.4 V x 0.28 = 3.2 V
Oscillator Frequency
3 cases have to be distinguished
1. f1 for duty cycle = 100%, no slope reduction with capacitor C4 (see Figure 4)
2. f2 for duty cycle < 100%, no slope reduction with capacitor C4 . For a duty cycle of less than 100%, the
oscillator frequency, f, is as follows:
3. f3 with duty cycle < 100% with slope reduction capacitor C4 (see “Output Slope Control”)
Electrical parameters are given for temperature range from minus 40 to + 110° С and Vbatt. From 9 to 16,5V.
Operation is guaranteed for Vbatt from 6 to 9V. All electrical parameters are specified relatively to “common”
output (02).
By selecting different values of C2 and C4, it is possible to have a range of oscillator frequencies from 10 to
2000 Hz as shown in the data sheet.
Rev. 00
IL6083
Output Slope Control
The slope of the lamp voltage is internally limited to reduce radio interference by limitation of the voltage gain
of the PWM comparator.
Thus, the voltage rise on the lamp is proportional to the oscillator voltage increase at the switchover time
according to the equation.
Via an external capacitor, C4, the slope can be further reduced as follows:
To damp oscillation tendencies, a resistance of 100Ω in series with capacitance C4 is recommended.
Interference Suppression
• “On-board” radio reception according to VDE 0879 part 3/4.81
• Test conditions refering to Figure 3
• Application circuit according to Figure 1 or Figure 4
• Load: nine 4 W lamps in parallel
• Duty cycle = 18%
• VBatt = 12 V
• fOsc = 100 Hz
Figure 3. Voltage Spectrum of On-board Radio Reception
Rev. 00
IL6083
Pins 5 and Pin 6, Short-circuit Protection and Current Sensing
Short-circuit Detection and Time Delay, td
The lamp current is monitored by means of an external shunt resistor. If the lamp current exceeds the
threshold for the short-circuit detection circuit (VT2 ≈ 90 mV), the duty cycle is switched over to 100% and the
capacitor C5 is charged by a current source of Ich - Idis. The external FET again is switched off after the cutoff threshold (VT5) is reached. Switching on the FET again is possible after a power-on reset only. The
current source, Idis, ensures that the capacitor C5 is not charged by parasitic currents.
The time delay, td, is calculated as follows:
Current Limitation
The lamp current is limited by a control amplifier to protect the external power transistor. The voltage drop
across the external shunt resistor acts as the measured variable. Current limitation takes place for a voltage
drop of VT1 ≈ 100 mV. Owing to the difference VT1 - VT2 ≈ 10 mV, it ensures that current limitation occurs only
when the short-circuit detection circuit has responded.
After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the supply voltage
capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is
switched on for the first time.
Pins 7 and 8, Charge Pump and Output
Pin 8 (output) is suitable for controlling a power MOSFET. During the active integration phase, the supply
current of the operational amplifier is mainly supplied by the capacitor C3 (bootstrapping). In addition, a
trickle charge is generated by an integrated oscillator (f7 ≈ 400 kHz) and a voltage doubler circuit. This
permits a gate voltage supply at a duty cycle of 100%.
Rev. 00
IL6083
Table of Electrical Parameters
Tamb = -40°C to +110°C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference
point ground, unless otherwise specified (see Figure 2). All other values refer to pin GND (pin 2).
Parameter
Symbol
Test Conditions
min
Rate
Typ. max
Unit
7.9
mA
25
V
V
Pin 1
Current Consumption
Is
Overvoltage
Detection, stage 1
Stabilized voltage
VS
Is=10mA
Switching on
Level of the lowered battery voltage Vbatt
Switching off
Battery Overvoltage Detection
Switching on
Stage 1
Vbatt
Switching off
Stage 2
Switching on
Vbatt
Detection stage 2
Switching off
Stabilized voltage
VS
Is=30mA
Short- Circuit Protection, Pin 6
short-circuit current limitation
VT1
VT1 = VS-V6
VT2
VT2 = VS-V6
Short circuit voltage
VT2 = VS-V6
VT1 -VT2
Delay Timer Short-circuit Detection, Vbatt = 12.0V,
Switch off threshold
VT5
VT5 = VS-V5
Charge current
Ich
Dicharge current
Idis
Capacitance current
I5
I5 = Ich-Idis
Voltage doubler, Pin 7
Supply voltage
Vbatt
Voltage
V7
Oscillator frequency
f7
Internal voltage limitation
V7
Edge rate
α4
Duty cycle 100%
24.5
4.4
4.8
5.0
5.4
27.0
5.6
6.0
18.3
16.7
25.5
19.5
18.5
20.0
18.5
28.5
23.0
20.0
21.7
20.3
32.5
26.5
21.5
V
V
V
V
85 100 120 mV
75
90 105
mV
3
10
30
Pin 5
10.2 10.4 10.6 V
13
uA
3
uA
5
10
15 mA
2VS
V
280 400 520 kHz
26.0 27.5 30.0
I7=5mA (whichever is lower)
V
VS+14 VS+15 VS+16
dV8/dt =α4 dV4/dt
53
63
72
V/ms
dV8/dtmax
130
Rev. 00
IL6083
Parameter
Voltage
Current,
Duty cycle
Frequency
Threshold cycle
Upper
Lower
Oscillator current
Frequency
Symbol
V8
I8
tpмин /T
Test Conditions
Gate Output , Pin 8
Low level
Vbatt = 16.5V
Tamb = 110° C,
R3=150Ω
High level, duty cycle 100%
V8 = low level
V8 = high level,
I7 >|I8|
Min: С2=68nF
Max: Vbatt ≤12.4V,
Vbatt = 16.5V,
С 2=68nF
Oscillator, Pin 4
Rate
Unit
min Type max
0.35 0.70 0.95
1.5*
V
V7
1.0
mA
-1.0
15
18
21
100
65
%
73
81
f
10
2000 Hz
α1
0.68
α2
0.65 0.67 0.69
α3
0.26 0.28
0.7
0.72
0.3
± IOSC
Vbatt=12.0 V
34
45
54
uA
f
С4 is open,
С2=68nF, duty cycle=50%
56
75
90
Hz
* Reference point is battery ground
Rev. 00
IL6083
Application Circuit
Figure 4. Application Circuit
Rev. 00
IL6083
Package Outline Dimension
DIP-8
N SUFFIX PLASTIC DIP
(MS – 001BA)
A
Dimension, mm
5
8
B
1
4
MIN
MAX
A
8.51
10.16
B
6.1
7.11
5.33
C
L
F
Symbol
C
D
0.36
0.56
F
1.14
1.78
-T- SEATING
PLANE
N
G
K
D
0.25 (0.010) M
M
H
J
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
Rev. 00
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