IDT IDT5V49EE901 Eeprom programmable clock generator Datasheet

DATASHEET
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
Description
Features
The IDT5V49EE901 is a programmable clock generator
intended for high performance data-communications,
telecommunications, consumer, and networking
applications. There are four internal PLLs, each individually
programmable, allowing for four unique non-integer-related
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from one of
the two redundant clock inputs. A glitchless automatic or
manual switchover function allows any one of the redundant
clocks to be selected during normal operation.
•
•
•
•
•
•
The IDT5V49EE901 is in-system, programmable and can
be programmed through the use of I2C interface. An
internal EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it on
power-up.
• Each PLL has a 7-bit reference divider and a 12-bit
Internal non-volatile EEPROM
Fast (400kHz) mode I2C serial interface
Input frequency range: 1 MHz to 200 MHz
Output frequency range: 4.9 kHz to 500 MHz
Reference crystal input with programmable linear load
capacitance
– Crystal frequency range: 8 MHz to 50 MHz
feedback-divider
• 8-bit output-divider blocks
• Fractional division capability on one PLL
• Two of the PLLs support spread spectrum generation
Each of the four PLLs has an 7-bit reference divider and a
12-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation
and/or fractional divides are allowed on two of the PLLs.
capability
• I/O Standards:
– Outputs - 3.3 V LVTTL/ LVCMOS
– Outputs - LVPECL, LVDS and HCSL
– Inputs - 3.3 V LVTTL/ LVCMOS
There are a total of six 8-bit output dividers. Each output
bank can be configured to support LVTTL, LVPECL, LVDS
or HCSL logic levels. Out0 (Output 0) supports 3.3V
single-ended output only. The outputs are connected to the
PLLs via a switch matrix. The switch matrix allows the user
to route the PLL outputs to any output bank. This feature
can be used to simplify and optimize the board layout. In
addition, each output's slew rate and enable/disable
function is programmable.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Four internal PLLs
1
•
•
•
•
Programmable slew rate control
•
•
•
•
•
Individual output enable/disable
Programmable loop bandwidth
Programmable output inversion to reduce bimodal jitter
Redundant clock inputs with glitchless auto and manual
switchover options
Power-down mode
3.3V core VDD
Available in TSSOP and VFQFPN packages
-40 to +85 C Industrial Temp operation
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CLOCK SYNTHESIZER
Functional Block Diagram
S
R
C
0
XIN/REF
XOUT
S
R
C
1
/DIV1
PLL1
S
R
C
2
/DIV2
PLL2
S
R
C
4
/DIV4
S
R
C
3
/DIV3
S
R
C
6
/DIV6
S
R
C
5
/DIV5
PLL0 (SS)
CLKIN
CLKSEL
PLL3 (SS)
SD/OE
SDA
SCL
OUT0
Control
Logic
SEL[2:0]
S1
OUT1
OUT2
OUT4
OUT4
S3
OUT3
OUT6
OUT5
OUT5
1. OUT1 & OUT2, OUT4 & OUT4, OUT3 & OUT6, and OUT5 & OUT5 pairs can be
configured to be LVDS, LVPECL or HCSL, or two single-ended LVTTL outputs.
2. CLKIN, CLKSEL, SD/OE and SEL[2:0] have pull down resistors.
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CLOCK SYNTHESIZER
PIN CONFIGURATION
25
16
VDD
28 pin TSSOP
(Top View)
VDD
15
OUT5
14
OUT5b
OUT4b
OUT5b
OUT5
GND
15
17
16
14
12
13
26
VDD
OUT4
27
SCLK
SDAT
SEL2
18
SEL1
19
11
GND
10
OUT2
13
OUT1
AVDD
28
CLKSEL
SEL0
20
VDD
9
OUT4b
OUT6
GND
11
22
21
12
23
7
8
30
6
VDD
CLKIN
GND
1
2
3
4
5
6
7
8
29
XIN/REF
VDD
XOUT
XIN/REF
VDDx
CLKIN
GND
OUT1
OUT2
OUT0
VDD
OUT3
SD/OE
SEL2
25
24
OUT4
26
4
5
10
3
31
VDD
VDDx
XOUT
GND
SEL1
VDD
SEL0
27
9
28
2
32
1
VDD
SD/OE
OUT0
24
23
22
21
20
19
18
17
OUT3
OUT6
GND
AVDD
CLKSEL
SCLK
SDAT
GND
32 pin VFQFPN
(Top View)
Pin Descriptions
Pin Name
PG28
Pin#
NL32
Pin#
I/O
Pin Type
CLKIN
8
5
I
LVTTL
Input clock. Weak internal pull down resistor.
XOUT
5
2
O
LVTTL
CRYSTAL_OUT -- Reference crystal feedback.
XIN / REF
6
3
I
LVTTL
CRYSTAL_IN -- Reference crystal input or external
reference clock input.
SDAT
18
18
I/O
LVTTL
Bidirectional I2C data.
SCLK
19
19
I
LVTTL
I2C clock.
CLKSEL
20
20
I
LVTTL
Input clock selector. Weak internal pull down resistor.
SEL2
26
26
I
LVTTL
Configuration select pin. Weak internal pull down
resistor.
SEL1
27
27
I
LVTTL
Configuration select pin. Weak internal pull down
resistor.
SEL0
28
28
I
LVTTL
Configuration select pin. Weak internal pull down
resistor.
SD/OE
1
29
I
LVTTL
Enables/disables the outputs or powers down the chip.
The SP bit (0x02) controls the polarity of the signal to be
either active HIGH or LOW. (Default is active HIGH.)
Weak internal pull down resistor.
OUT0
2
30
O
LVTTL
Configurable clock output 0.
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Pin Description
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CLOCK SYNTHESIZER
Pin Name
PG28
Pin#
NL32
Pin#
I/O
Pin Type
Pin Description
OUT1
10
7
O
Adjustable1
Configurable clock output 1. Single-ended or differential
when combined with OUT2.
OUT2
11
8
O
Adjustable1
Configurable clock output 2. Single-ended or differential
when combined with OUT1.
OUT3
24
24
O
Adjustable1
Configurable clock output 3. Single-ended or differential
when combined with OUT6.
OUT4
13
10
O
Adjustable1,2
Configurable clock output 4. Single-ended or differential
when combined with OUT4b.
OUT4b
14
11
O
Adjustable1,2
Configurable clock output 4b. Single-ended or differential
when combined with OUT4.
OUT5
16
14
O
Adjustable1,2
Configurable clock output 5. Single-ended or differential
when combined with OUT5b.
OUT5b
17
15
O
Adjustable1,2
Configurable clock output 5b. Single-ended or differential
when combined with OUT5.
OUT6
23
23
O
Adjustable1
Configurable clock output 6. Single-ended or differential
when combined with OUT3.
VDD
25
1, 9, 12,
16, 25,
32
Power
Device power supply. Connect to 3.3V.
VDDx
7
4
Power
Crystal oscillator power supply. Connect to 3.3V. Use
filtered analog power supply if available.
AVDD
21
21
Power
Device analog power supply. Connect to 3.3V. Use
filtered analog power supply if available.
GND
9, 15,
22,
PAD
6, 13,
17, 22,
31,PAD
Power
Connect to Ground.
1.Outputs are user programmable to drive single-ended 3.3-V LVTTL, or differential LVDS, LVPECL or HCSL interface levels
2. When only an individual single-ended clock output is required, tie OUT# and OUT#b together.
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CLOCK SYNTHESIZER
PLL Features and Descriptions
7-bit
D
VCO
4-bit
12-bit
A
N
Sigm a-Delta
M odulator
PLL0 Block Diagram
7-bit
D
VCO
12-bit
N
PLL1, PLL2 and PLL3 Block Diagram
Pre-Divider
(D)1 Values
Multiplier
(M)2 Values
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
PLL0
1 - 127
10 - 8206
Yes
Yes
PLL1
1 - 127
1 - 4095
Yes
No
PLL2
1 - 127
1 - 4095
Yes
No
PLL3
3 - 127
12 - 4095
Yes
Yes
1.For PLL0, PLL1 and PLL2, D=0 means PLL power down. For PLL3, 0, 1, and 2 are DNU (do not use)
2.For PLL0, M = 2*N + A + 1 (for A > 0); M = 2*N (for A = 0); A < N-1. For PLL1, PLL2 and PLL3, M=N.
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CLOCK SYNTHESIZER
Reference Clock Input Pins and
Selection
internal load capacitance is set.
XTAL load cap = 3.5 pF + XTAL[4:0] * 0.125 pF (Eq. 1)
The IDT5V49EE901 supports up to two clock inputs. One of
the clock inputs (XIN/ REF) can be driven by either an
external crystal or a reference clock. The second clock input
(CLKIN) can only be driven from an external reference
clock. The CLKSEL pin selects the input clock from either
XTAL/REF or CLKIN.
Bits
Step (pF)
Min (pF)
Max (pF)
XTAL
8
0.125
0
4
When using an external reference clock instead of a crystal
on the XTAL/REF pin, the input load capacitors may be
completely bypassed. This allows for the input frequency to
be up to 200 MHz. When using an external reference clock,
the XOUT pin must be left floating, XTAL must be
programmed to the default value of “00h”, and the crystal
drive strength bit, XDRV (0x06), must be set to the default
value of “11h”.
Either clock input can be set as the primary clock. The
primary clock designation is to establish which is the main
reference clock to the PLLs. The non-primary clock is
designated as the secondary clock in case the primary clock
goes absent and a backup is needed. The PRIMSRC bit
(0xBE through 0xC3) determines which clock input will be
selected as primary clock. When PRIMSRC bit is "0",
XIN/REF is selected as the primary clock, and when "1",
CLKIN as the primary clock.
Switchover Modes
The IDT5V49EE901 features redundant clock inputs which
supports both Automatic and Manual switchover mode.
These two modes are determined by the configuration bits,
SM (0xBE through 0xC3). The primary clock source can be
programmed, via the PRIMSRC bit, to be either XIN/REF or
CLKIN. The other clock input will be considered as the
secondary source. Note that the switchover modes are
asynchronous. If the reference clocks are directly routed to
OUTx with no phase relationship, short pulses can be
generated during switchover. The automatic switchover
mode will work only when the primary clock source is
XIN/REF. Switchover modes are not supported for crystal
input configurations.
The two external reference clocks can be manually selected
using the CLKSEL pin. The SM bits (0xBE through 0xC3)
must be set to "0x" for manual switchover which is detailed
in SWITCHOVER MODES section.
Crystal Input (XIN/REF)
The crystal used should be a fundamental mode quartz
crystal; overtone crystals should not be used.
When the XIN/REF pin is driven by a crystal, it is important
to set the internal inverter oscillator drive strength and
tuning/load capacitor values correctly to achieve the best
clock performance. These values are programmable
through I2C interface to allow for maximum compatibility
with crystals from various manufacturers, processes,
performances, and qualities. The internal load capacitors
are true parallel-plate capacitors for ultra-linear
performance. Parallel-plate capacitors were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and
temperature changes. External non-linear crystal load
capacitors should not be used for applications that are
sensitive to absolute frequency requirements. The value of
the internal load capacitors are determined by XTAL[4:0]
bits. The load capacitance can be set with a resolution of
0.125 pF for a total crystal load ranging from 3.5 pF to 7.5
pF. Check with the crystal vendor's load capacitance
specification for the exact setting to tune the internal load
capacitor. The following equation governs how the total
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Parameter
Manual Switchover Mode
When SM[1:0] is "0x", the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to
switch between the primary and secondary clock sources.
As previously mentioned, the primary and secondary clock
source setting is determined by the PRIMSRC bit. During
the switchover, no glitches will occur at the output of the
device, although there may be frequency and phase drift,
depending on the exact phase and frequency relationship
between the primary and secondary clocks.
Automatic Switchover Mode
The redundant inputs are in automatic switchover mode.
Automatic switchover mode has revertive functionality. The
input clock selection will switch to the secondary clock
source when there are no transitions on the primary clock
source for two secondary clock cycles. If both reference
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CLOCK SYNTHESIZER
clocks are at different frequencies, the device will always
remain on the primary clock unless it is absent for two
secondary clock cycles. The secondary clock must always
run at a frequency less than or equal to the primary clock
frequency.
Reference Divider, Feedback Divider, and
Q[6:0]
PM
Output Divider
111 1111
0
Disabled
1
/1
0
/2
1
/((Q[6:0] + 2) * 2)
<111 1111
Output Divider
Each PLL incorporates a 7-bit reference divider (D[6:0]) and
a 12-bit feedback divider (N[11:0]) that allows the user to
generate four unique non-integer-related frequencies. Each
output divide supports 8-bit output-divider (PM and Q[7:0]).
The following equation governs how the output frequency is
calculated.
FOUT = FIN *
(M
)
D
Note that the actual 7-bit Q-divider value has a 2 added to
the integer value Q and the outputs are routed through
another div/2 block. The output divider should never be
disabled unless the output bank will never be used during
normal operation. The output frequency range for LVTTL
outputs are from 4.9KHz to 200MHz. The output frequency
for LVPECL/LVDS/HCSL outputs range from 4.9KHz to
500MHz.
(Eq. 1)
ODIV
Spread Spectrum Generation (PLL0)
Where FIN is the reference frequency, M is the total
feedback-divider value, D is the reference divider value,
ODIV is the total output-divider value, and FOUT is the
resulting output frequency.
PLL0 supports spread spectrum generation capability,
which users have the option of turning on or off. Spread
spectrum profile, frequency, and spread amplitude are fully
programmable. The programmable spread spectrum
generation parameters are TSSC[3:0], NSSC[2:0],
SS_OFFSET[5:0], SD[3:0], DITH, and X2 bits. These bits
are in the memory address from 0xAC to 0xBD for PLL0.
The spread spectrum generation on PLL0 can be
enabled/disabled using the TSSC[3:0] bits. To enable
spread spectrum, set TSSC > '0' and set NSSC[2:0],
SS_OFFSET[5:0], SD[3:0], and the A[3:0] (in the total M
value) accordingly. To disable spread spectrum generation,
set TSSC = '0'.
For PLL0,
M = 2 * N + A + 1 (for A>0)
M = 2 * N (for A = 0)
For PLL1, PLL2 and PLL3,
M=N
TSSC[3:0]
PM and Q[6:0] are the bits used to program the 8-bit
output-dividers for outputs OUT1-6. OUT0 does not have
any output divide along its path. The 8-bit output-dividers
will bypass or divide down the output banks' frequency with
even integer values ranging from 2 to 256.
These bits are used to determine the number of
phase/frequency detector cycles per spread spectrum cycle
(ssc) steps. The modulation frequency can be calculated
with the TSSC bits in conjunction with the NSSC bits. Valid
TSSC integer values for the modulation frequency range
from 5 to 14. Values of 0 - 4 and 15 should not be used.
There is the option to choose between disabling the
output-divider, utilizing a div/1, a div/2, or the 7-bit Q-divider
by using the PM bit. If the output is disabled, it will be driven
High, Low or High Impedance, depending on OEM[1:0].
Each bank, except for OUT0, has a PM bit. When disabled,
no clocks will appear at the output of the divider, but will
remain powered on. The output divides selection table is
shown below.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
NSSC[2:0]
These bits are used to determine the number of
delta-encoded samples used for a single quadrant of the
spread spectrum waveform. All four quadrants of the spread
spectrum waveform are mirror images of each other. The
modulation frequency is also calculated based on the NSSC
bits in conjunction with the TSSC bits. Valid NSSC integer
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CLOCK SYNTHESIZER
SDK is the delta-encoded sample out of a possible 12.
values range from 1 to 6. Values of 0 and 7 should not be
used.
Amplitude = ((2*N[11:0] + A[3:0] + 1) * Spread% / 100) /2
(Eq. 5)
SS_OFFSET[5:0]
These bits are used to program the fractional offset with
respect to the nominal M integer value. For center spread,
the SS_OFFSET is set to '0' so that the spread spectrum
waveform is centered about the nominal M (Mnom) value.
For down spread, the SS_OFFSET > '0' such the spread
spectrum waveform is centered about the (Mideal -1
+SS_Offset) value. The downspread percentage can be
thought of in terms of center spread. For example, a
downspread of -1% can also be considered as a center
spread of ±0.5% but with Mnom shifted down by one and
offset. The SS_OFFSET has integer values ranging from 0
to 63.
if 1 < Amplitude < 2, then set X2 bit to '1'.
Modulation frequency:
FPFD = FIN / D (Eq. 6)
FVCO = FPFD * MNOM (Eq. 7)
FSSC = FPFD / (4 * Nssc * Tssc) (Eq. 8)
Spread:
Σ∆ = SD0 + SD1 + SD2 + …+ SD11
SD[3:0]
the number of samples used depends on the NSSC value
These bits are used to shape the profile of the spread
spectrum waveform. These are delta-encoded samples of
the waveform. There are twelve sets of SD samples. The
NSSC bits determine how many of these samples are used
for the waveform. The sum of these delta-encoded samples
(sigma delta- encoded samples) determine the amount of
spread and should not exceed (63 - SS_OFFSET). The
maximum spread is inversely proportional to the nominal M
integer value.
Σ∆< 63 - SS_OFFSET
±Spread% = (Σ∆ * 100)/(64 * (2*N[11:0] + A[3:0] + 1) (Eq. 9)
±Max Spread% / 100 = 1 / MNOM or 2 / MNOM (X2=1)
DITH
This bit is used for dithering the sigma-delta-encoded
samples. This will randomize the least-significant bit of the
input to the spread spectrum modulator. Set the bit to '1' to
enable dithering.
X2
This bit will double the total value of the
sigma-delta-encoded-samples which will increase the
amplitude of the spread spectrum waveform by a factor of
two. When X2 is '0', the amplitude remains nominal but if set
to '1', the amplitude is increased by x2. The following
equations govern how the spread spectrum is set:
TSSC = TSSC[3:0] + 2 (Eq. 2)
NSSC = NSSC[2:0] * 2 (Eq. 3)
SD[3:0]K = SJ+1(unencoded) - SJ(unencoded) (Eq. 4)
where SJ is the unencoded sample out of a possible 12 and
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CLOCK SYNTHESIZER
Profile:
to enhance the profile of the spread spectrum waveform.
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ,
SS_OFFSET + SDJ+1, etc.
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Spread Spectrum Using Sinusoidal Profile
Nssc * Tssc = 192
Use Eq.10 to determine the value of the
sigma-delta-encoded samples.
±2% = (Σ∆ * 100)/(64 * 48)
Σ∆ = 61.4
Either round up or down to the nearest integer value.
Therefore, we end up with 61 or 62 for sigma-delta-encoded
samples. Since the sigma-delta-encoded samples must not
exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within
the limits. It is the discretion of the user to define the shape
of the profile that is better suited for the intended application.
Using Eq. 9 again, the actual spread for the
sigma-delta-encoded samples of 56 and 57 are ±1.99% and
±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Example
Amplitude = 48 * (1.99 or 2.02) / 100/2 = 0.48 < 1
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center
spread of ±2%. Find the necessary spread spectrum
register settings.
Therefore, the X2 = '0 '. The dither bit is left to the discretion
of the user.
The example above was of a center spread using spread
spectrum. For down spread, the nominal M value can be set
one integer value lower to 47.
Since the spread is center, the SS_OFFSET can be set to
'0'. Solve for the nominal M value; keep in mind that the
nominal M should be chosen to maximize
Note that the IDT5V49EE901 should not be programmed
with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to
prevent an unstable state in the modulator.
the VCO. Start with D = 1, using Eq.6 and Eq.7.
MNOM = 1200MHz / 25MHz = 48
The PLL loop bandwidth must be at least 10x the
modulation frequency along with higher damping (larger
ωuz) to prevent the spread spectrum from being filtered and
reduce extraneous noise. Refer to the LOOP FILTER
section for more detail on ωuz. The A[3:0] must be used for
spread spectrum, even if the total multiplier value is an even
integer.
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we
have the nominal M value, we can determine TSSC and
NSSC by using Eq.8.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 2 and Eq.3, we find that the closest
value is when TSSC = 14 and NSSC = 6. Keep in mind to
maximize the number of samples used
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CLOCK SYNTHESIZER
Spread Spectrum Generation (PLL3)
Zero capacitor (Cz) = 196 pF + CZ* 217 pF
PLL3 support spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The technique is different from
that used in PLL0. The programmable spread spectrum
generation parameters are SS_D3[7:0], SSVCO[15:0],
SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the
memory address range of 0x4C to 0x85 for PLL3. The
spread spectrum generation on PLL3 can be
enabled/disabled using the SSENB bit. To enable spread
spectrum, set SSENB = '1'.
Pole capacitor (Cp) = 15 pF
Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA
VCO gain (KVCO) = 900 MHz/V * 2π
The following equations govern how the loop filter is set for
PLL3:
For Non-Spread Spectrum Operation:
Resistor(Rz) =
For Spread Enabled:
Spread spectrum is configured using SS_D3(spread
spectrum reference divide)
SS_D3 =
FIN
4 * FMOD
(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
kOhms (Eq. 12)
* RZ[0] + 6*(1 – RZ[0])
For Spread Spectrum Operation:
(Eq. 10)
Resistor(Rz) =
(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
kOhms (Eq. 13)
* RZ[0] + 6*(1 – RZ[0])
and SSVCO (spread spectrum loop feedback counter).
SSVCO = [0.5 *
FVCO
FMOD
Zero capacitor (Cz) = 250 pF
* ( 1 + SS/400) + 5] (Eq. 11)
Pole capacitor (Cp) = 15 pF
For Non-Spread Spectrum Operation:
SS is the total Spread Spectrum amount (I.e. center spread
+0.5% has a total spread of 1.0% and down spread -0.5%
has a total spread of 0.5%.)
24 * (1 + (2 * IP[0]) + (4 * IP[1]) + (8 * IP[2])) A (Eq. 14)
Charge
=
pump (Ip)
3 + (5 * IP[3]) + (11 * IP[4])
Loop Filter
For Spread Spectrum Operation:
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low-jitter
frequency generation. The specific loop filter components
that can be programmed are the resistor via the RZ[3:0] bits,
zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and
the charge pump current via the IP[2:0] bits (for PLL0, PLL1
and PLL2) or IP[3:0] (for PLL3).
12 * (1 + (2 * IP[0]) + (4 * IP[1]) + (8 * IP[2])) A (Eq. 14)
Charge
=
pump (Ip)
27 + (5 * IP[3]) + (11 * IP[4])
VCO gain (KVCO) = 900 MHz/V * 2π
The following equations govern how the loop filter is set for
PLL0 - PLL2:
Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0
kOhm
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CLOCK SYNTHESIZER
PLL Loop Bandwidth:
Charge pump gain (Kφ⎞) = Ip / 2π
VCO gain (KVCO) = 900 MHz/V * 2π
M = Total multiplier value (See the Reference Divider,
Feedback Divider and Output Divider section for more
detail)
ωc = (Rz * Kφ * KVCO * Cz)/(M * (Cz + Cp))
Fc = ωc / 2π
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce the phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (φm)
needs to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = (Cz + Cp)/(Rz * Cz * Cp)
φm = (360 / 2π) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
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CLOCK SYNTHESIZER
SEL[2:0] Function
pins. Alternatively, users may use I2C interface to configure
these registers on-the-fly.
The IDT5V49EE901 can support up to six unique
configurations. Users may pre-programmed all these
configurations, and select the configurations using SEL[2:0]
SEL2
SEL1
SEL0
Configuration Selections
0
0
0
Select CONFIG0
0
0
1
Select CONFIG1
0
1
0
Select CONFIG2
0
1
1
Select CONFIG3
1
0
0
Select CONFIG4
1
0
1
Select CONFIG5
1
1
0
Reserved (Do not use)
1
1
1
Reserved (Do not use)
SD/OE Pin Function
I2C Programming
The polarity of the SD/OE signal pin can be programmed to
be either active HIGH or LOW with the SP bit (0x02). When
SP is “0” (default), the pin becomes active HIGH and when
SP is “1”, the pin becomes active LOW. The SD/OE pin can
be configured as either to shutdown the PLLs or to
enable/disable the outputs.
The IDT5V49EE901 is programmed through an I2C-Bus
serial interface, and is an I2C slave device. The read and
write transfer formats are supported. The first byte of data
after a write frame to the correct slave address is interpreted
as the register address; this address auto-increments after
each byte written or read.
The frame formats are shown in the following illustration.
SP
O E M ode1
S D /O E
SD M ode2
SH
1 Assert to disable the outputs whose OE bits are set
2 Assert to shut down power, on the outputs and 3-level pins
Configuration OUTx IO Standard
Framing
Users can configure the individual output IO standard from
a single 3.3V power supply. Each output can support 3.3V
LVTTL. Each output pair can support LVDS, LVPECL or
HCSL. OUT0 can only be 3.3V single-ended output.
Programming the Device
I2C may be used to program the IDT5V49EE901.
– Device (slave) address = 7'b1101010
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CLOCK SYNTHESIZER
Each frame starts with a “Start Condition” and ends with an
“End Condition”. These are both generated by the Master
device.
MSB
1
LSB
1
0
1
0
1
0
R/W
7-bit slave address
R/W
0 – Slave will be written by master
1 – Slave will be read by master
ACK from Slave
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a “1” bit.
First Byte Transmitted on I2C Bus
External I2C Interface Condition
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition
Progwrite
S
Address
R/W
ACK
Command Code
ACK
Register
ACK
Data
ACK
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
8-bits
1-bit
P
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
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CLOCK SYNTHESIZER
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
S
Address
R/W
ACK
Command Code
ACK
Register
ACK
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
P
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
S
Address
R/W
ACK
ID Byte
ACK
Data_1
ACK
Data_2
ACK
7-bits
1
1-bit
8-bits
1-bit
8-bits
1-bit
8-bits
1-bit
Data_last NACK
8-bits
P
1-bit
Progread Command Frame
Progsave
S
Address
R/W
ACK
Command Code
ACK
7-bits
0
1-bit
8-bits: xxxx xx01
1-bit
P
Note:
PROGWRITE is for writing to the IDT5V49EE901 registers.
PROGREAD is for reading the IDT5V49EE901 registers.
PROGSAVE is for saving all the contents of the IDT5V49EE901 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM contents to the IDT5V49EE901 registers.
Progrestore
S
Address
R/W
ACK
Command Code
ACK
7-bits
0
1-bit
8-bits: xxxx xx10
1-bit
P
EEPROM Interface
The IDT5V49EE901 can also store its configuration in an internal EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by issuing a save instruction (ProgSave) and can be loaded back to
the internal programming registers by issuing a restore instruction (ProgRestore).
To initiate a save or restore using I2C, only two bytes are transferred. The Device Address is issued with the read/write bit
set to “0”, followed by the appropriate command code. The save or restore instruction executes after the STOP condition is
issued by the Master, during which time the IDT5V49EE901 will not generate Acknowledge bits. The IDT5V49EE901 will
acknowledge the instructions after it has completed execution of them. During that time, the I2C bus should be interpreted
as busy by all other users of the bus.
On power-up of the IDT5V49EE901, an automatic restore is performed to load the EEPROM contents into the internal
programming registers. The IDT5V49EE901 will be ready to accept a programming instruction once it acknowledges its 7-bit
I2C address.
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I2C Bus DC Characteristics
Symbol
Parameter
VIH
Input HIGH Level
VIL
Input LOW Level
VHYS
IIN
Conditions
Min
Typ
0.7xVDD
0.3xVDD
Hysteresis of Inputs
Output LOW Voltage
Unit
V
0.05xVDD
V
V
Input Leakage Current
VOL
Max
IOL = 3 mA
±1.0
µA
0.4
V
I2C Bus AC Characteristics for Standard Mode
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
100
kHz
Bus free time between STOP and START
4.7
µs
tSU:START
Setup Time, START
4.7
µs
tHD:START
Hold Time, START
4
µs
tSU:DATA
Setup Time, data input (SDA)
250
ns
tHD:DATA
Hold Time, data input (SDA) 1
0
µs
tOVD
Output data valid from clock
3.45
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDAT, SCLK)
1000
ns
tF
Fall Time, data and clock (SDAT, SCLK)
300
ns
tHIGH
HIGH Time, clock (SCLK)
4
µs
tLOW
LOW Time, clock (SCLK)
4.7
µs
4
µs
tSU:STOP
Setup Time, STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDAT signal (referred to the VIH(MIN)
of the SCLK signal) to bridge the undefined region of the falling edge of SCLK.
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CLOCK SYNTHESIZER
I2C Bus AC Characteristics for Fast Mode
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
400
kHz
Bus free time between STOP and START
1.3
µs
tSU:START
Setup Time, START
0.6
µs
tHD:START
Hold Time, START
0.6
µs
100
ns
0
µs
tSU:DATA
Setup Time, data input (SDA)
tHD:DATA
Hold Time, data input (SDA)
1
tOVD
Output data valid from clock
0.9
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tF
Fall Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tHIGH
HIGH Time, clock (SCL)
0.6
µs
tLOW
LOW Time, clock (SCL)
1.3
µs
Setup Time, STOP
0.6
µs
tSU:STOP
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN)
of the SCL signal) to bridge the undefined region of the falling edge of SCL.
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CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V49EE901. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Symbol
VDD
VI
Description
Min
Max
Unit
-0.5
+4.6
V
-0.5
+4.6
V
-0.5
VDD+0.5
V
150
°C
150
°C
Internal Power Supply Voltage
1
Input Voltage
VO
Output Voltage (not to exceed 4.6
TJ
Junction Temperature
TSTG
Storage Temperature
V)1
-65
1.Input negative and output voltage ratings may be exceeded if the input and output current ratings are observed.
Recommended Operation Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Power supply voltage for VDD pins supporting core and
outputs
3.135
3.3
3.465
V
VDDX
Power supply voltage for crystal oscillator. Use filtered
analog power supply if available.
3.135
3.3
3.465
V
AVDD
Analog power supply voltage. Use filtered analog
power supply if available.
3.135
3.3
3.465
V
+85
°C
15
pF
MHz
TA
Operating temperature, ambient
-40
CLOAD_OUT Maximum load capacitance (3.3V LVTTL only)
FIN
tPU
External reference crystal
8
50
External reference clock CLKIN
1
200
0.05
5
Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
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CLOCK SYNTHESIZER
Capacitance (TA = +25 °C)
Symbol
Parameter
CIN
Min
Input Capacitance (CLKIN, CLKSEL, SD/OE,
SDA, SCL, SEL[2:0])
Pull-down
Resistor
CLKIN, CLKSEL, SD/OE, SEL[2:0]
Typ
Max
Unit
3
7
pF
180
kΩ
Crystal Specifications
XTAL_FREQ
Crystal frequency
8
XTAL_MIN
Minimum crystal load capacitance
XTAL_MAX
Maximum crystal load capacitance
XTAL_VPP
Voltage swing (peak-to-peak, nominal)
50
MHz
3.5
pF
1.5
2.3
35.5
pF
3.2
V
DC Electrical Characteristics for 3.3-V LVTTL 1
Symbol
Parameter
Test Conditions
Min
Typ
Unit
VDD
V
0.4
V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
Output Leakage Current 3-state outputs. VO = VDD or GND,
VDD = 3.6V
10
µA
IOZDD
2.4
Max
2
V
Note 1: See “Recommended Operating Conditions” table.
Power Supply Characteristics for PLLs and LVTTL Outputs
Total Supply Current Vs PLL Frequency
Supply current Vs Output Frequency
140
120
60
Supply Current(mA)
Total Supply Current(mA)
70
50
40
30
20
10
0
0
200
400
600
800
1000
PLL0+PLL1 On IDD(mA)
PLL0+PLL1+PLL2 on IDD(mA)
All Plls ON IDD(mA)
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
80
60
40
20
0
1200
0
PLL Frequency(MHz)
PLL0 ON IDD(mA)
100
18
25
50
75
100
125
150
175
No outputs
Output
Frequency(MHz)
REF
output
on
2 outputs on
3 outputs on
4 outputs on
6 outputs on
9 outputs on
8 outputs on
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CLOCK SYNTHESIZER
DC Electrical Characteristics for LVDS
Symbol
Parameter
Min
Typ
Max
Unit
VOT (+)
Differential Output Voltage for the TRUE binary state
247
454
mV
VOT (-)
Differential Output Voltage for the FALSE binary state
-247
-454
mV
50
mV
1.375
V
50
mV
VOT
VOS
Change in VOT between Complimentary Output States
Output Common Mode Voltage (Offset Voltage)
VOS
1.125
1.2
Change in VOS between Complimentary Output States
IOS
Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD
9
24
mA
IOSD
Differential Outputs Short Circuit Current, VOUT+ = VOUT-
6
12
mA
Power Supply Characteristics for LVDS Outputs 1
Symbol
Test Conditions 2
Parameter
Typ
Max
Unit
IDDQ
Quiescent VDD Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68
90
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD = Max., CL = 0pF
30
45
µA/MHz
ITOT
Total Power VDD Supply
Current
FREFERENCE CLOCK = 100 MHz, CL = 5 pF
86
130
mA
FREFERENCE CLOCK = 200 MHz, CL = 5 pF
100
150
FREFERENCE CLOCK = 400 MHz, CL = 5 pF
122
190
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for LVPECL
Symbol
Parameter
Min
Typ
Max
Unit
VOH
Output Voltage HIGH, terminated through 50Ω tied to VDD-2 V
VDD-1.2
VDD-0.9
V
VOL
Output Voltage LOW, terminated through 50Ω tied to VDD-2 V
VDD-1.95
VDD-1.61
V
0.55
0.93
V
VSWING
Peak-to-Peak Output Voltage Swing
Power Supply Characteristics for LVPECL Outputs 1
Symbol
Test Conditions 2
Parameter
Typ
Max
Unit
IDDQ
Quiescent VDD Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
86
110
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD = Max., CL = 0pF
35
50
µA/MHz
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Symbol
ITOT
CLOCK SYNTHESIZER
Test Conditions 2
Parameter
Total Power VDD Supply
Current
Typ
Max
Unit
FREFERENCE CLOCK = 100 MHz, CL = 5 pF
120
180
mA
FREFERENCE CLOCK = 200 MHz, CL = 5 pF
130
190
FREFERENCE CLOCK = 400 MHz, CL = 5 pF
140
210
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
DC Electrical Characteristics for HCSL
Symbol
Parameter
Min
Typ
Max
Unit
VOH
Output Voltage HIGH
660
700
850
mV
VOL
Output Voltage LOW
-150
0
27
mV
250
350
550
mV
Crossing Absolute
Point
Voltage
Power Supply Characteristics for HCSL Outputs 1
Symbol
Test Conditions 2
Parameter
Typ
Max
Unit
IDDQ
Quiescent VDD Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
68
90
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD = Max., CL = 0pF
30
45
µA/MHz
ITOT
Total Power VDD Supply
Current
FREFERENCE CLOCK = 100 MHz, CL = 5 pF
86
130
mA
FREFERENCE CLOCK = 200 MHz, CL = 5 pF
100
150
FREFERENCE CLOCK = 400 MHz, CL = 5 pF
122
190
Note 1: Output banks 4 and 5 are toggling. Other output banks are powered down.
Note 2: The termination resistors are excluded from these measurements.
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CLOCK SYNTHESIZER
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol
fIN 1
1 / t1
Parameter
Input Frequency
Output Frequency
Test Conditions
Min.
Typ.
Max.
Units
Input frequency limit (CLKIN)
1
200
MHz
Input frequency limit (XIN/REF)
8
100
MHz
Single ended clock output limit (LVTTL)
0.001
200
MHz
Differential cock output limit (LVPECL/
LVDS/HCSL)
0.001
500
fVCO
VCO Frequency
VCO operating frequency range
100
1300
MHz
fPFD
PFD Frequency
PFD operating frequency range
0.5 1
100
MHz
fBW
Loop Bandwidth
Based on loop filter resistor and capacitor
values
0.01
10
MHz
t2
Input Duty Cycle
Duty Cycle for input
40
60
%
t3
Output Duty Cycle
Measured at VDD/2, all outputs except
Reference output
45
55
%
Measured at VDD/2, Reference output
40
60
%
t4
2
t5
Slew Rate, SLEW[1:0] = 00
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 15 pF)
3.5
Slew Rate, SLEW[1:0] = 01
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 15 pF)
2.75
Slew Rate, SLEW[1:0] = 10
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 15 pF)
2
Slew Rate, SLEW[1:0] = 11
Single-ended 3.3V LVCMOS output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 15 pF)
1.25
Rise Times
LVDS, 20% to 80%
600
Fall Times
LVDS, 80% to 20%
600
Rise Times
LVPECL, 20% to 80%
600
Fall Times
LVPECL, 80% to 20%
600
Rise Times
HCSL, From 0.175 V to 0.525 V
175
400
700
Fall Times
HCSL, From 0.525 V to 0.175 V
175
400
700
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
21
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ps
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Symbol
t7
Clock Jitter
t8
t9 4
t10
Parameter
5
CLOCK SYNTHESIZER
Test Conditions
Typ.
Max.
Units
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVTTL outputs
80
100
ps
Peak-to-peak period jitter, all 4 PLLs on,
LVTTL outputs3
200
270
ps
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVPECL, LVDS
or HCSL outputs
60
80
ps
Peak-to-peak period jitter, all 4 PLLs on,
LVPECL, LVDS or HCSL outputs
120
160
ps
75
ps
20
ms
2
ms
Output Skew
Skew between output to output on the same
bank
Lock Time
PLL lock time from power-up
Lock Time
PLL lock time from shutdown mode
Min.
10
1.Practical lower frequency is determined by loop filter settings.
2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3.Jitter measured with clock outputs of 27 MHz, 48 MHz, 24.576 MHz, 74.25 MHz and 25 MHz.
4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
5.Actual PLL lock time depends on the loop configuration.
Spread Spectrum Generation Specifications
Symbol
Parameter
Description
fIN 1
Input Frequency Input Frequency Limit
fMOD
Mod Frequency
Modulation Frequency
Spread Value
fSPREAD
Min
Typ
1
Max
Unit
400
MHz
33
kHz
Amount of Spread Value (programmable) - Down Spread
Programmable
%fOUT
Amount of Spread Value (programmable) - Center Spread
Programmable
1.Practical lower frequency is determined by loop filter settings.
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CLOCK SYNTHESIZER
Test Circuits and Conditions
VDDOx
VDD
0.1µF
CLKOUT
OUTx
0.1µF
CL
GND
Test Circuits for DC Outputs
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CLOCK SYNTHESIZER
Other Termination Scheme (Block Diagram)
5 pF
CLKOUT
OUTx
OUTx
CLKOUT
5 pF
CLKOUT
5 pF
GND
GND
LVDS: 100Ω between differential outputs
LVTTL: 5 pF for each output
VDD-2V
49.9 Ohm
49.9 Ohm
5 pF
33 Ohm
CLKOUT
CLKOUT
OUTx
OUTx
CLKOUT
5 pF
33 Ohm
GND
CLKOUT
49.9 Ohm
49.9 Ohm
GND
GND
VDD-2V
LVPECL
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
GND
HCSL
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CLOCK SYNTHESIZER
Programming Registers Table
Default
Register
Addr
Hex
Value
Bit #
7
0x00
00
0x01
00
0x02
02
SP
0x03
02
Reserved
0x04
0F
SH
0x05
04
0x06
00
0x07
00
0x08
00
6
5
4
3
2
1
Reserved
HW/SW
Reserved
OE6
OE5
SEL[2:0]
OE4
OE3
OE2
OE1
OS*[6:0]
Reserved
Reserved
Description
0
XTCLKSEL
Hardware/Software Mode control
HW/SW - 0=HW, 1=SW
SEL[2:0] - selects configuration in
SW mode
OE0
OEx=Output Power Suspend
function for OUTx (‘1’=OUTx will
be suspended on SD/OE pin.
Disable mode is defined by
OEMx bits), ‘0’=outputs enabled
and no association with OE pin
(default).
OS*[6:0] - output suspend, active
low. Overwrites OE setting.
PLLS*[3:0]
PLLS*[3:0] - PLL Suspend, active
low
SH - shutdown/OE configuration
Reserved
XTCLKSEL - crystal/clock select.
0=Crytal, 1=ICLK
Reserved
Reserved
XTAL[4:0]
XTAL[4:0] - crystal cap
Reserved
0x09
00
0x0A
10
CZ0_CFG4
IP0[2:0]_CFG4
RZ0[3:0]_CFG4
0x0B
10
CZ0_CFG5
IP0[2:0]_CFG5
RZ0[3:0]_CFG5
0x0C
10
CZ0_CFG0
IP0[2:0]_CFG0
RZ0[3:0]_CFG0
0x0D
10
CZ0_CFG1
IP0[2:0]_CFG1
RZ0[3:0]_CFG1
0x0E
10
CZ0_CFG2
IP0[2:0]_CFG2
RZ0[3:0]_CFG2
0x0F
10
CZ0_CFG3
IP0[2:0]_CFG3
0x10
00
Reserved
D0[6:0]_CFG0
0x11
00
Reserved
D0[6:0]_CFG1
0x12
00
Reserved
D0[6:0]_CFG2
0x13
00
Reserved
D0[6:0]_CFG3
0x14
00
Reserved
D0[6:0]_CFG4
0x15
00
Reserved
0x16
01
N0[7:0]_CFG4
0x17
01
N0[7:0]_CFG5
0x18
01
N0[7:0]_CFG0
0x19
01
N0[7:0]_CFG1
0x1A
01
N0[7:0]_CFG2
0x1B
01
0x1C
00
A0[3:0]_CFG0
N0[11:8]_CFG0
0x1D
00
A0[3:0]_CFG1
N0[11:8]_CFG1
0x1E
00
A0[3:0]_CFG2
N0[11:8]_CFG2
0x1F
00
A0[3:0]_CFG3
N0[11:8]_CFG3
0x20
00
A0[3:0]_CFG4
N0[11:8]_CFG4
0x21
00
A0[3:0]_CFG5
0x22
10
CZ1_CFG4
IP1[2:0]_CFG4
RZ1[3:0]_CFG4
0x23
10
CZ1_CFG5
IP1[2:0]_CFG5
RZ1[3:0]_CFG5
0x24
10
CZ1_CFG0
IP1[2:0]_CFG0
RZ1[3:0]_CFG0
0x25
10
CZ1_CFG1
IP1[2:0]_CFG1
RZ1[3:0]_CFG1
0x26
10
CZ1_CFG2
IP1[2:0]_CFG2
RZ1[3:0]_CFG2
0x27
10
CZ1_CFG3
IP1[2:0]_CFG3
RZ1[3:0]_CFG3
Reserved
PLL0 loop parameter
RZ0[3:0]_CFG3
PLL0 input divider and input sel
D0[6:0] - 127 step Ref Div
D0 = 0 means power down.
D0[6:0]_CFG5
N - Feedback Divider
2 - 4095 (values of “0” and “1” are
not allowed) Total feedback with
A, using provided calculation
N0[7:0]_CFG3
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
N0[11:8]_CFG5
25
PLL1 Loop Parameter
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
CLOCK SYNTHESIZER
Bit #
7
6
5
4
3
2
1
0x28
00
Reserved
D1[6:0]_CFG0
0x29
00
Reserved
D1[6:0]_CFG1
0x2A
00
Reserved
D1[6:0]_CFG2
0x2B
00
Reserved
D1[6:0]_CFG3
0x2C
00
Reserved
D1[6:0]_CFG4
0x2D
00
Reserved
0x2E
01
N1[7:0]_CFG4
0x2F
01
N1[7:0]_CFG5
0x30
01
N1[7:0]_CFG0
0x31
01
N1[7:0]_CFG1
0x32
01
N1[7:0]_CFG2
0x33
01
0x34
00
N3[11:8]_CFG0
N1[11:8]_CFG0
0x35
00
N3[11:8]_CFG1
N1[11:8]_CFG1
0x36
00
N3[11:8]_CFG2
N1[11:8]_CFG2
0x37
00
N3[11:8]_CFG3
N1[11:8]_CFG3
0x38
00
N3[11:8]_CFG4
N1[11:8]_CFG4
0x39
00
N3[11:8]_CFG5
0x3A
00
CZ2_CFG4
IP2[2:0]_CFG4
RZ2[3:0]_CFG4
0x3B
00
CZ2_CFG5
IP2[2:0]_CFG5
RZ2[3:0]_CFG5
0x3C
00
CZ2_CFG0
IP2[2:0]_CFG0
RZ2[3:0]_CFG0
0x3D
00
CZ2_CFG1
IP2[2:0]_CFG1
RZ2[3:0]_CFG1
0x3E
00
CZ2_CFG2
IP2[2:0]_CFG2
RZ2[3:0]_CFG2
0x3F
00
CZ2_CFG3
IP2[2:0]_CFG3
0x40
00
Reserved
D2[6:0]_CFG0
0x41
00
Reserved
D2[6:0]_CFG1
0x42
00
Reserved
D2[6:0]_CFG2
0x43
00
Reserved
D2[6:0]_CFG3
0x44
00
Reserved
D2[6:0]_CFG4
0x45
00
Reserved
0x46
01
N2[7:0]_CFG4
0x47
01
N2[7:0]_CFG5
0x48
01
N2[7:0]_CFG0
0x49
01
N2[7:0]_CFG1
0x4A
01
N2[7:0]_CFG2
0x4B
01
0x4C
80
SSENB_CFG0
0
0
IP3[4]_CFG0
N2[11:8]_CFG0
0x4D
80
SSENB_CFG1
0
0
IP3[4]_CFG1
N2[11:8]_CFG1
0x4E
80
SSENB_CFG2
0
0
IP3[4]_CFG2
N2[11:8]_CFG2
0x4F
80
SSENB_CFG3
0
0
IP3[4]_CFG3
N2[11:8]_CFG3
0x50
80
SSENB_CFG4
0
0
IP3[4]_CFG4
N2[11:8]_CFG4
0x51
80
SSENB_CFG5
0
0
IP3[4]_CFG5
N2[11:8]_CFG5
0x52
00
Reserved
0x53
00
Reserved
0x54
00
Reserved
0x55
00
Reserved
0
Description
PLL1 input divider and input sel
D1[6:0] - 127 step Ref Div
D1 = 0 means power down.
D1[6:0]_CFG5
N - Feedback Divider
2 - 4095 (value of “0” is not
allowed) Total feedback with A,
using provided calculation
N1[7:0]_CFG3
PLL3 Feedback Divider
N1[11:8]_CFG5
PLL2 Loop Parameter
RZ2[3:0]_CFG3
PLL2 Reference Divide and Input
Select
D2[6:0] - 127 step Ref Div
D2 = 0 means power down.
D2[6:0]_CFG5
N2[7:0] - PLL2 Feedback Divider
2 - 4095 (value of “0” is not
allowed).
(See Addr 0x4C:0x51 for
N2[15:8])
N2[7:0]_CFG3
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
26
N2[11:8] - PLL2 Feedback Divide
PLL3 Spread Spectrum
SSENB - Spread Spectrum
Enable
SSENB = 1 means ON
IP3[4:0] - PLL3 Charge Pump
Current.
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
CLOCK SYNTHESIZER
Bit #
7
6
5
4
3
2
1
0x56
00
IP3[3:0]_CFG4
RZ3[3:0]_CFG4
0x57
00
IP3[3:0]_CFG5
RZ3[3:0]_CFG5
0x58
00
IP3[3:0]_CFG0
RZ3[3:0]_CFG0
0x59
00
IP3[3:0]_CFG1
RZ3[3:0]_CFG1
0x5A
00
IP3[3:0]_CFG2
RZ3[3:0]_CFG2
0x5B
00
IP3[3:0]_CFG3
0x5C
03
Reserved
D3[6:0]_CFG0
0x5D
03
Reserved
D3[6:0]_CFG1
0x5E
03
Reserved
D3[6:0]_CFG2
0x5F
03
Reserved
D3[6:0]_CFG3
0x60
03
Reserved
D3[6:0]_CFG4
0x61
03
Reserved
0x62
0C
N3[7:0]_CFG4
0x63
0C
N3[7:0]_CFG5
0x64
0C
N3[7:0]_CFG0
0x65
0C
N3[7:0]_CFG1
0x66
0C
N3[7:0]_CFG2
0x67
0C
N3[7:0]_CFG3
0x68
00
SSVCO[7:0]_CFG0
0x69
00
SSVCO[7:0]_CFG1
0x6A
00
SSVCO[7:0]_CFG2
0x6B
00
SSVCO[7:0]_CFG3
0x6C
00
SSVCO[7:0]_CFG4
0x6D
00
SSVCO[7:0]_CFG5
0x6E
00
SS_D3[7:0]_CFG4
0x6F
00
SS_D3[7:0]_CFG5
0x70
00
SS_D3[7:0]_CFG0
0x71
00
SS_D3[7:0]_CFG1
0x72
00
SS_D3[7:0]_CFG2
0x73
00
SS_D3[7:0]_CFG3
0x74
01
0x75
03
OEM0[1:0]
SLEW0[1:0]
0x76
00
OEM1[1:0]
SLEW1[1:0]
0
Description
PLL3 Loop Parameter
RZ3[3:0]_CFG3
PLL3 Reference Divide and input
sel
D3[6:0] - 127 step Ref Div
D3 = 0 means power down.
D3[6:0]_CFG5
N - Feedback Divider
12 - 4095 (values of “0” through
“11” are not allowed)
SSVCO[7:0] - PLL3 Spread
Spectrum Loop Feedback
Counter
See Addr 0x80:0x85 for
SSVCO[15:8]
SS_D[7:0] - PLL3 Spread
Spectrum Reference Divide
Reserved
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Reserved
INV0
Reserved
INV1[1:0]
27
S1
S3
LVL1[1:0]
Output Controls
S1=1 - OUT1/OUT2 are from
DIV1/DIV2 respectively
S1=0 - Both from DIV2
S3 =1 - OUT3/OUT6 are from
DIV3/DIV6
S3=0 - Both from DIV6
SLEW# - LVTTL only
OEM#–output enable mode
x0 - tristated
01 - park low
11 - park high
OEM0 controls OUT0 only
Output Controls
LVL1[1:0] - output pair
OUT1/OUT2
[00] - LVTTL
[01] - LVDS
[10] - LVPECL
[11] - HCSL
INV1 [CLK1, CLK2]
[0] - normal
[1] - invert clock
OEM1 controls OUT1/OUT2
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
CLOCK SYNTHESIZER
Bit #
7
6
5
4
3
2
SLEW2[1:0]
Description
1
0
CMEN3
CMEN1
0x77
00
0x78
00
OEM3[1:0]
SLEW3[1:0]
INV3[1:0]
LVL3[1:0]
OEM3 controls OUT3 and OUT6
0x79
00
OEM4[1:0]
SLEW4[1:0]
INV4[1:0]
LVL4[1:0]
OEM4 controls OUT4 and
OUT4b
0x7A
00
OEM5[1:0]
SLEW5[1:0]
INV5[1:0]
LVL5[1:0]
OEM5 controls OUT5 and
OUT5b
SLEW6[1:0]
CMEN5
0x7B
00
0x7C
00
Reserved
0x7D
00
Reserved
0x7E
00
Reserved
0x7F
00
Reserved
0x80
00
SSVCO[15:8]_CFG0
0x81
00
SSVCO[15:8]_CFG1
0x82
00
SSVCO[15:8]_CFG2
0x83
00
SSVCO[15:8]_CFG3
0x84
00
SSVCO[15:8]_CFG4
0x85
00
SSVCO[15:8]_CFG5
0x86
00
Reserved
0x87
00
Reserved
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
28
CMEN# - common mode enable
Set to 1 for LVDS
Set to 0 for LVTTL, LVPECL,
HCSL
CMEN4
PLL3 Spread Spectrum
Feedback Counter
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
CLOCK SYNTHESIZER
Bit #
7
6
5
4
3
2
1
0x88
FF
PM1_CFG0
Q1[6:0]_CFG0
0x89
FF
PM1_CFG1
Q1[6:0]_CFG1
0x8A
FF
PM1_CFG2
Q1[6:0]_CFG2
0x8B
FF
PM1_CFG3
Q1[6:0]_CFG3
0x8C
FF
PM1_CFG4
Q1[6:0]_CFG4
0x8D
FF
PM1_CFG5
Q1[6:0]_CFG5
0x8E
7F
PM2_CFG4
Q2[6:0]_CFG4
0x8F
7F
PM2_CFG5
Q2[6:0]_CFG5
0x90
7F
PM2_CFG0
Q2[6:0]_CFG0
0x91
7F
PM2_CFG1
Q2[6:0]_CFG1
0x92
7F
PM2_CFG2
Q2[6:0]_CFG2
0x93
7F
PM2_CFG3
Q2[6:0]_CFG3
0x94
7F
PM3_CFG0
Q3[6:0]_CFG0
0x95
7F
PM3_CFG1
Q3[6:0]_CFG1
0x96
7F
PM3_CFG2
Q3[6:0]_CFG2
0x97
7F
PM3_CFG3
Q3[6:0]_CFG3
0x98
7F
PM3_CFG4
Q3[6:0]_CFG4
0x99
7F
PM3_CFG5
Q3[6:0]_CFG5
0x9A
7F
PM4_CFG4
Q4[6:0]_CFG4
0x9B
7F
PM4_CFG5
Q4[6:0]_CFG5
0x9C
7F
PM4_CFG0
Q4[6:0]_CFG0
0x9D
7F
PM4_CFG1
Q4[6:0]_CFG1
0x9E
7F
PM4_CFG2
Q4[6:0]_CFG2
0x9F
7F
PM4_CFG3
Q4[6:0]_CFG3
0xA0
7F
PM5_CFG0
Q5[6:0]_CFG0
0xA1
7F
PM5_CFG1
Q5[6:0]_CFG1
0xA2
7F
PM5_CFG2
Q5[6:0]_CFG2
0xA3
7F
PM5_CFG3
Q5[6:0]_CFG3
0xA4
7F
PM5_CFG4
Q5[6:0]_CFG4
0xA5
7F
PM5_CFG5
Q5[6:0]_CFG5
0xA6
7F
PM6_CFG4
Q6[6:0]_CFG4
0xA7
7F
PM6_CFG5
Q6[6:0]_CFG5
0xA8
7F
PM6_CFG0
Q6[6:0]_CFG0
0xA9
7F
PM6_CFG1
Q6[6:0]_CFG1
0xAA
7F
PM6_CFG2
Q6[6:0]_CFG2
0xAB
7F
PM6_CFG3
0xAC
00
TSSC[3:0]_CFG0
NSSC[3:0]_CFG0
0xAD
00
TSSC[3:0]_CFG1
NSSC[3:0]_CFG1
0xAE
00
TSSC[3:0]_CFG2
NSSC[3:0]_CFG2
0xAF
00
TSSC[3:0]_CFG3
NSSC[3:0]_CFG3
0xB0
00
TSSC[3:0]_CFG4
NSSC[3:0]_CFG4
0xB1
00
TSSC[3:0]_CFG5
0xB2
00
DITH_CFG4
X2_CFG4
SSOFFSET[5:0]_CFG4
0xB3
00
DITH_CFG5
X2_CFG5
SSOFFSET[5:0]_CFG5
0xB4
00
DITH_CFG0
X2_CFG0
SSOFFSET[5:0]_CFG0
0xB5
00
DITH_CFG1
X2_CFG1
SSOFFSET[5:0]_CFG1
0xB6
00
DITH_CFG2
X2_CFG2
SSOFFSET[5:0]_CFG2
0xB7
00
DITH_CFG3
X2_CFG3
SSOFFSET[5:0]_CFG3
0xB8
11
SD1[3:0]_CFG0
SD0[3:0]_CFG0
0xB9
11
SD1[3:0]_CFG1
SD0[3:0]_CFG1
0xBA
11
SD1[3:0]_CFG2
SD0[3:0]_CFG2
0
Description
Output Divides
for Q<>111111,
PM=0 - Divide by 2
PM=1, (Q+2)*2
for Q=1111111
PM=0, disable the output divider
PM=1, bypass the output divide,
(divide by 1)
Q6[6:0]_CFG3
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
PLL0 Spread Spectrum Control
NSSC[3:0]_CFG5
29
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
Default
Register
Addr
Hex
Value
CLOCK SYNTHESIZER
Bit #
7
6
5
4
3
2
1
Description
0
0xBB
11
SD1[3:0]_CFG3
SD0[3:0]_CFG3
0xBC
11
SD1[3:0]_CFG4
SD0[3:0]_CFG4
0xBD
11
SD1[3:0]_CFG5
0xBE
AE
SRC1[1:0]_CFG4
SRC0[1:0]_CFG4
PDPL3_CFG4
SM[1:0]_CFG4
PRIMSRC_CFG4 Output Divide Source Selection
0xBF
AE
SRC1[1:0]_CFG5
SRC0[1:0]_CFG5
PDPL3_CFG5
SM[1:0]_CFG5
PRIMSRC_CFG5 PRIMSRC - primary source -
SD0[3:0]_CFG5
crystal or ICLOCK
0 = crystal/REFIN
1 = CLKIN
0xC0
AE
SRC1[1:0]_CFG0
SRC0[1:0]_CFG0
PDPL3_CFG0
SM[1:0]_CFG0
PRIMSRC_CFG0 SM = switch mode
0x = manual
10 = reserved
11 = auto-revertive
0xC1
AE
SRC1[1:0]_CFG1
SRC0[1:0]_CFG1
PDPL3_CFG1
SM[1:0]_CFG1
PRIMSRC_CFG1 PDPL3 - PLL3 shutdown
0 = normal
1 = shut down
0xC2
AE
SRC1[1:0]_CFG2
SRC0[1:0]_CFG2
PDPL3_CFG2
SM[1:0]_CFG2
PRIMSRC_CFG2 SRC = MUX control bit prior to
DIV#
SRC0[1:0]
00 - DIV1
01 - DIV3
10 - Reference input
SRC1[1:0]_CFG3
SRC0[1:0]_CFG3
PDPL3_CFG3
SM[1:0]_CFG3
PRIMSRC_CFG3
0xC3
AE
0xC4
24
SRC4[0]_CFG0
SRC3[2:0]_CFG0
SRC2[2:0]_CFG0
SRC1[2]_CFG0 SRC1/SRC2/SRC3..SRC5
0xC5
24
SRC4[0]_CFG1
SRC3[2:0]_CFG1
SRC2[2:0]_CFG1
SRC1[2]_CFG1 000 - DIV1
0xC6
24
SRC4[0]_CFG2
SRC3[2:0]_CFG2
SRC2[2:0]_CFG2
0xC7
24
SRC4[0]_CFG3
SRC3[2:0]_CFG3
SRC2[2:0]_CFG3
SRC1[2]_CFG2 010 - Reference input
SRC1[2]_CFG3 011 - Reserved
0xC8
24
SRC4[0]_CFG4
SRC3[2:0]_CFG4
SRC2[2:0]_CFG4
SRC1[2]_CFG4
0xC9
24
SRC4[0]_CFG5
SRC3[2:0]_CFG5
SRC2[2:0]_CFG5
SRC1[2]_CFG5 110 - PLL2
0xCA
49
SRC6[2:0]_CFG4
SRC5[2:0]_CFG4
SRC4[2:1]_CFG4
0xCB
49
SRC6[2:0]_CFG5
SRC5[2:0]_CFG5
SRC4[2:1]_CFG5
0xCC
49
SRC6[2:0]_CFG0
SRC5[2:0]_CFG0
SRC4[2:1]_CFG0
0xCD
49
SRC6[2:0]_CFG1
SRC5[2:0]_CFG1
SRC4[2:1]_CFG1
0xCE
49
SRC6[2:0]_CFG2
SRC5[2:0]_CFG2
SRC4[2:1]_CFG2
0xCF
49
SRC6[2:0]_CFG3
SRC5[2:0]_CFG3
SRC4[2:1]_CFG3
001 - DIV3
100 - PLL0
101 - PLL1
111 - PLL3
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
30
SRC6
000 - Reserved
001 - Reserved
010 - Reference input
011 - Reserved
100 - Reserved
101 - PLL1
110 - Reserved
111 - Reserved
Quiet MUX
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Marking Diagram (NLG32)
Marking Diagram (PGG28)
28
IDT5V4
9EE901
NLGI
#YYWW$
15
IDT5V49EE
901PGGI
#YYWW$
14
1
Notes:
1. “#” is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “$” is the assembly mark code.
4. “G” after the two-letter package code designates RoHS compliant package.
5. “I” at the end of part number indicates industrial temperature range.
6. Bottom marking: country of origin if not USA.
Thermal Characteristics 28-pin TSSOP
Parameter
Thermal Resistance Junction to
Ambient
Symbol
Conditions
Min.
Typ.
Max. Units
θJA
Still air
83
° C/W
θJA
1 m/s air flow
75
° C/W
θJA
3 m/s air flow
61
° C/W
60
° C/W
4.5
° C/W
Typ.
Max. Units
Thermal Resistance Junction to Case
θJC
Thermal Resistance Junction to Top
of Case
ΨJT
Still air
Thermal Characteristics 32-pin VFQFPN
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
Symbol
Conditions
Min.
θJA
Still air
34
° C/W
θJA
1 m/s air flow
29
° C/W
θJA
3 m/s air flow
27
° C/W
32
° C/W
θJC
31
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (28-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
28
Symbol
E1
INDEX
AREA
A
A1
A2
b
C
D
E
E1
e
L
α
aaa
E
1 2
D
Min
Inches
Max
Min
-1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
9.60
9.80
6.40 BASIC
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
-0.10
Max
-0.047
0.002
0.006
0.032
0.041
0.007
0.012
0.0035 0.008
0.378
0.386
0.252 BASIC
0.169
0.177
0.0256 Basic
0.018
0.030
0°
8°
-0.004
A
A2
A1
c
- Ce
b
SEATING
PLANE
aaa C
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
32
L
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Package Outline and Package Dimensions (32-pin VFQFPN, 0.50mm pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
5V49EE901PGGI
5V49EE901PGGI8
5V49EE901NLGI
5V49EE901NLGI8
See page 30
See page 30
See page 30
See page 30
Tubes
Tape and Reel
Tubes
Tape and Reel
28pin TSSOP
28pin TSSOP
32pin VFQFPN
32pin VFQFPN
Temperature
-40 to +85°
-40 to +85°
-40 to +85°
-40 to +85°
C
C
C
C
“G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
33
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
Revision History
Rev.
Originator
Date
Description of Change
A
R.Willner
4/22/09
Advance Information.
B
R.Willner
5/04/09
Identified VDDX (crystal oscillator power) and AVDD (analog power) on device.
C
R.Willner
6/04/09
Add default configurations, pull-down resistor values on input pins.
Released Datasheet from Advanced Information.
D
R.Willner
06/10/09
Updates: crystal load specs; “Output Duty Cycle” specs; addresses 0x07, 0x02 and 0xBF
in “Programming Registers” table.
E
R.Willner
7/21/09
Corrected 32VFQFPN marking to be consistant with manufacturing.
F
R.Willner
08/26/09
Updated 32-pin VFQFPN thermal data
G
R.Willner
10/05/09
Changed IP3[3:0] to IP3[4:0] ; updated “Programming Registers Table”.
H
R.Willner
12/07/09
Updated VDD min/max specs in Recommended Operation Conditions
I
R.Willner
12/09/09
Increased max VCO frequency to 1300 MHz.
J
R.Willner
02/23/10
Updated Recommended Operation Conditions to include Vddx and AVdd parameters.
IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR
34
IDT5V49EE901
REV J 022310
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR
CLOCK SYNTHESIZER
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© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks of Integrated
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