M25PX16 16-Mbit, dual I/O, 4-Kbyte subsector erase, serial Flash memory with 75 MHz SPI bus interface Features SPI bus compatible serial interface 75 MHz (maximum) clock frequency 2.3 V to 3.6 V single supply voltage Dual input/output instructions resulting in an equivalent clock frequency of 150 MHz: – Dual Output Fast Read instruction – Dual Input Fast Program instruction VFQFPN8 (MP) 6 × 5 mm 16 Mbit Flash memory – Uniform 4-Kbyte subsectors – Uniform 64-Kbyte sectors Additional 64-byte user-lockable, one-time programmable (OTP) area SO8W (MW) 208 mils Erase capability – Subsector (4-Kbyte) granularity – Sector (64-Kbyte) granularity – Bulk Erase (16 Mbit) in 15 s (typical) Write protections – Software write protection applicable to every 64-Kbyte sector (volatile lock bit) – Hardware write protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2) SO8 (MN) 150 mils Deep Power-down mode: 5 µA (typical) Electronic signature – JEDEC standard two-byte signature (7115h) – Unique ID code (UID) with16 bytes readonly, available upon customer request TBGA24 (ZM) 6x8 mm More than 100 000 write cycles per sector More than 20 year data retention Packages – RoHS compliant Automotive certified parts available March 2010 Rev 8 1/65 www.numonyx.com 1 Contents M25PX16 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Serial Data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Serial Data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Write Protect/Enhanced Program supply voltage (W/VPP) . . . . . . . . . . . . . 9 2.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Dual Input Fast Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Subsector Erase, Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . 13 4.4 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 14 4.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 4.7.1 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.7.2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 15 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/65 6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 M25PX16 Contents 6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.4 TB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4.5 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.7 Read Data Bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . 30 6.8 Dual Output Fast Read (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.9 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.10 Read OTP (ROTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.11 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.12 Dual Input Fast Program (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.13 Program OTP instruction (POTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.14 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.15 Subsector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.16 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.17 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.18 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.19 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3/65 List of tables M25PX16 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. 4/65 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity) . . . . . . . . . . . . . . . 16 Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 TBGA 6x8 mm 24-ball package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 M25PX16 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 BGA 6x8 24 ball ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 25 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 27 Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 30 Read Data Bytes at higher speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Dual Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Read Lock Register (RDLR) instruction sequence and data-out sequence . . . . . . . . . . . . 33 Read OTP (ROTP) instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Dual Input Fast Program (DIFP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Program OTP (POTP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 How to permanently lock the 64 OTP bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Subsector Erase (SSE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 44 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Write Protect Setup and Hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 53 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead, 6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SO8W 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . . . 57 SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 58 TBGA, 6x8 mm, 24 ball package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5/65 Description 1 M25PX16 Description The M25PX16 is a 16 Mbit (2 Mb x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX16 supports two new, high-performance dual input/output instructions: Dual Output Fast Read (DOFR) instruction used to read data at up to 75 MHz(1) by using both pin DQ1 and pin DQ0 as outputs Dual Input Fast Program (DIFP) instruction used to program data at up to 75 MHz(1) by using both pin DQ1 and pin DQ0 as inputs These new instructions double the transfer bandwidth for read and program operations. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 32 sectors that are further divided into 16 subsectors each (512 subsectors in total). The memory can be erased a 4-Kbyte subsector at a time, a 64-Kbyte sector at a time, or as a whole. It can be Write Protected by software using a mix of volatile and non-volatile protection features, depending on the application needs. The protection granularity is of 64 Kbytes (sector granularity). The M25PX16 has 64 one-time-programmable bytes (OTP bytes) that can be read and programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP (POTP), respectively. These 64 bytes can be permanently locked by a particular Program OTP (POTP) sequence. Once they have been locked, they become read-only and this state cannot be reverted. Further features are available as additional security options. More information on these security features is available, upon completion of an NDA (nondisclosure agreement), and are, therefore, not described in this datasheet. For more details of this option contact your nearest Numonyx Sales office. 1. 75 MHz operation is available only on the VCC range 2.7 V - 3.6 V 6/65 M25PX16 Description Figure 1. Logic diagram VCC DQ0 DQ1 C M25PX16 S W/VPP HOLD VSS Table 1. AI14228 Signal names Signal name Function Direction C Serial Clock Input DQ0 Serial Data input I/O(1) DQ1 Serial Data output I/O(2) S Chip Select Input W/VPP Write Protect/Enhanced Program supply voltage Input HOLD Hold Input VCC Supply voltage VSS Ground 1. Serves as an output during Dual Output Fast Read (DOFR) instructions. 2. Serves as an input during Dual Input Fast Program (DIFP) instructions. Figure 2. VFQFPN and SO8 connections M25PX16 S 1 DQ1 2 W/VPP 3 VSS 4 8 7 6 5 VCC HOLD C DQ0 AI13720b 1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1. 7/65 Description M25PX16 Figure 3. Note: 8/65 BGA 6x8 24 ball ballout 1 NC = No Connection 2 See Section 11: Package mechanical. M25PX16 Signal descriptions 2 Signal descriptions 2.1 Serial Data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the Dual Input Fast Program (DIFP) instruction, pin DQ1 is used as an input. It is latched on the rising edge of the Serial Clock (C). 2.2 Serial Data input (DQ0) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). During the Dual Output Fast Read (DOFR) instruction, pin DQ0 is used as an output. Data are shifted out on the falling edge of the Serial Clock (C). 2.3 Serial Clock (C) This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (DQ0) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (DQ1) changes after the falling edge of Serial Clock (C). 2.4 Chip Select (S) When this input signal is High, the device is deselected and Serial Data output (DQ1) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low enables the device, placing it in the Active Power mode. After power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction. 2.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data input (DQ0) and Serial Clock (C) are Don’t care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect/Enhanced Program supply voltage (W/VPP) W/VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. 9/65 Signal descriptions M25PX16 If the W/VPP input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input signal is used to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register. See Table 9). If VPP is in the range of VPPH (as defined in Table 15) it acts as an additional power supply.(2) 2.7 VCC supply voltage VCC is the supply voltage. 2.8 VSS ground VSS is the reference for the VCC supply voltage. 2. Avoid applying VPPH to the W/VPP pin during Bulk Erase. 10/65 M25PX16 3 SPI modes SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5, is the clock polarity when the bus master is in Standby mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 4. Bus Master and memory devices on the SPI bus VSS VCC R SDO SPI interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C SPI Bus Master R CS3 VCC C VCC C DQ1DQ0 VSS DQ1 DQ0 VSS DQ1DQ0 SPI memory device R SPI memory device R SPI memory device VSS CS2 CS1 S W HOLD S W HOLD S W HOLD AI13725b 1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data output (DQ1) line at a time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure that the M25PX16 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and C do not become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is 100 kΩ, assuming that the time constant R*Cp (Cp = parasitic capacitance of the bus line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance. 11/65 SPI modes M25PX16 Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA 0 0 C 1 1 C DQ0 DQ1 MSB MSB AI13730 12/65 M25PX16 Operating features 4 Operating features 4.1 Page programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP) and Table 18: AC characteristics). 4.2 Dual Input Fast Program The Dual Input Fast Program (DIFP) instruction makes it possible to program up to 256 bytes using two input pins at the same time (by changing bits from 1 to 0). For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see Section 6.12: Dual Input Fast Program (DIFP)). 4.3 Subsector Erase, Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a subsector at a time, using the Subsector Erase (SSE) instruction, a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSSE, tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. 4.4 Polling during a Write, Program or Erase cycle A further improvement in the time to Write Status Register (WRSR), Program OTP (POTP), Program (PP), Dual Input Fast Program (DIFP) or Erase (SSE, SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSSE, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. 13/65 Operating features 4.5 M25PX16 Active Power, Standby Power and Deep Power-down modes When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down (RDP) instruction) is executed. While in the Deep Power-down mode, the device ignores all Write, Program and Erase instructions (see Deep Power-down (DP)), this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. 4.6 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits. 4.7 Protection modes There are protocol-related and specific hardware and software protection modes. They are described below. 14/65 M25PX16 4.7.1 Operating features Protocol-related protections The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX16 features the following data protection mechanisms: Power On Reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: 4.7.2 – Power-up – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Write to Lock Register (WRLR) instruction completion – Program OTP (POTP) instruction completion – Page Program (PP) instruction completion – Dual Input Fast Program (DIFP) instruction completion – Subsector Erase (SSE) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection, as all Write, Program and Erase instructions are ignored. Specific hardware and software protection There are two software protected modes, SPM1 and SPM2, that can be combined to protect the memory array as required. The SPM2 can be locked by hardware with the help of the W input pin. SPM1 and SPM2 The first software protected mode (SPM1) is managed by specific Lock Registers assigned to each 64 Kbyte sector. The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector: the Write Lock bit and the Lock Down bit. – Write Lock bit: The Write Lock bit determines whether the contents of the sector can be modified (using the Write, Program or Erase instructions). When the Write Lock bit is set to ‘1’, the sector is write protected – any operations that attempt to change the data in the sector will fail. When the Write Lock bit is reset to ‘0’, the sector is not write protected by the Lock Register, and may be modified. – Lock Down bit: The Lock Down bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down bit is set, ‘1’, further 15/65 Operating features M25PX16 modification to the Write Lock and Lock Down bits cannot be performed. A powerup, is required before changes to these bits can be made. When the Lock Down bit is reset, ‘0’, the Write Lock and Lock Down bits can be changed. The definition of the Lock Register bits is given in Table 9: Lock Register out. Table 2. Software protection truth table (Sectors 0 to 63, 64 Kbyte granularity) Sector Lock Register Protection status Lock Down bit Write Lock bit 0 0 Sector unprotected from Program/Erase/Write operations, protection status reversible 0 1 Sector protected from Program/Erase/Write operations, protection status reversible 1 0 Sector unprotected from Program/Erase/Write operations, Sector protection status cannot be changed except by a power-up. 1 1 Sector protected from Program/Erase/Write operations, Sector protection status cannot be changed except by a Power-up. the second software protected mode (SPM2) uses the Block Protect bits (see Section 6.4.3: BP2, BP1, BP0 bits) and the Top/Bottom bit (see Section 6.4.4: TB bit) to allow part of the memory to be configured as read-only. Table 3. Protected area sizes Status Register contents Memory content TB BP BP BP bit bit 2 bit 1 bit 0 16/65 Protected area Unprotected area 0 0 0 0 none All sectors(1) (32 sectors: 0 to 31) 0 0 0 1 Upper 32nd (Sector 31) Lower 31/32nds (31 sectors: 0 to 30) 0 0 1 0 Upper 16th (2 sectors: 30 and 31) Lower 15/16ths (30 sectors: 0 to 29) 0 0 1 1 Upper 8th (4 sectors: 28 to 31) Lower 7/8ths (28 sectors: 0 to 27) 0 1 0 0 Upper 4th (8 sectors: 24 to 31) Lower 3/4ths (24 sectors: 0 to 23) 0 1 0 1 Upper half (16 sectors: 16 to 31) Lower half (16 sectors: 0 to 15) 0 1 1 0 All sectors (32 sectors: 0 to 31) none 0 1 1 1 All sectors (32 sectors: 0 to 31) none 1 0 0 0 none All sectors(1) (32 sectors: 0 to 31) 1 0 0 1 Lower 32nd (sector 0) Upper 31/32nds (31 sectors: 1 to 31) 1 0 1 0 Lower 16th (2 sectors: 0 and 1) Upper 15/16ths (30 sectors: 2 to 31) 1 0 1 1 Lower 8th (4 sectors: 0 to 3) Upper 7/8ths (28 sectors: 4 to 31) 1 1 0 0 Lower 4th (8 sectors: 0 to 7) Upper 3/4ths (24 sectors: 8 to 31) 1 1 0 1 Lower half (16 sectors: 0 to 15) Upper half (16 sectors: 16 to 31) M25PX16 Operating features Table 3. Protected area sizes Status Register contents Memory content TB BP BP BP bit bit 2 bit 1 bit 0 Protected area Unprotected area 1 1 1 0 All sectors (32 sectors: 0 to 31 none 1 1 1 1 All sectors (32 sectors: 0 to 31 none 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. As a second level of protection, the Write Protect signal (applied on the W/VPP pin) can freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) are protected. For more details, see Section 6.5: Write Status Register (WRSR). 4.8 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select (S) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 6). The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 6). During the Hold condition, the Serial Data output (DQ1) is high impedance, and Serial Data input (DQ0) and Serial Clock (C) are Don’t care. Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. 17/65 Operating features Figure 6. M25PX16 Hold condition activation C HOLD Hold Condition (standard use) Hold Condition (non-standard use) AI02029D 18/65 M25PX16 Memory organization The memory is organized as: 2 097 152 bytes (8 bits each) 512 subsectors (4 Kbytes each) 32 sectors (64 Kbytes each) 8192 pages (256 bytes each) 64 OTP bytes located outside the main memory array Each page can be individually programmed (bits are programmed from 1 to 0). The device is Subsector, Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Figure 7. Block diagram HOLD W/VPP High Voltage Generator Control Logic 64 OTP bytes S C DQ0 I/O Shift Register DQ1 Address Register and Counter Status Register 256 Byte Data Buffer 1FFFFFh Y Decoder 5 Memory organization 00000h 000FFh 256 bytes (page size) X Decoder AI13722a-1 19/65 Memory organization Table 4. Sector M25PX16 Memory organization Subsector 20/65 ... ... ... ... ... 140FFFh 495 1EF000h 1EFFFFh 319 13F000h 13FFFFh ... ... ... ... ... ... 19 480 1E0000h 1E0FFFh 304 130000h 130FFFh 479 1DF000h 1DFFFFh 303 12F000h 12FFFFh ... ... ... ... ... ... 18 464 1D0000h 1D0FFFh 288 120000h 120FFFh 463 1CF000h 1CFFFFh 287 11F000h 11FFFFh ... ... ... ... ... ... 17 448 1C0000h 1C0FFFh 272 110000h 110FFFh 447 1BF000h 1BFFFFh 271 10F000h 10FFFFh ... ... ... ... ... ... 16 432 1B0000h 1B0FFFh 256 100000h 100FFFh 431 1AF000h 1AFFFFh 255 FF000h FFFFFh ... ... ... ... ... 15 416 1A0000h 1A0FFFh 240 F0000h F0FFFh 415 19F000h 19FFFFh 239 EF000h EFFFFh ... ... ... ... ... 14 400 190000h 190FFFh 224 E0000h E0FFFh 399 18F000h 18FFFFh 223 DF000h DFFFFh ... ... ... ... ... 13 384 180000h 180FFFh 208 D0000h D0FFFh 383 17F000h 17FFFFh 207 CF000h CFFFFh ... ... ... ... 12 368 170000h 170FFFh 192 C0000h C0FFFh 367 16F000h 16FFFFh 191 BF000h BFFFFh ... ... ... 11 ... 21 140000h 352 160000h 160FFFh 176 B0000h B0FFFh 351 15F000h 15FFFFh 175 AF000h AFFFFh 160 A0000h A0FFFh ... 22 320 ... 23 1F0FFFh ... 24 1F0000h ... 25 496 ... 26 14FFFFh ... 27 20 14F000h ... 28 335 Address range ... 29 Subsector ... 30 1FFFFFh ... 31 1FF000h Sector ... 511 Address range 336 150000h 150FFFh 10 M25PX16 Memory organization Subsector ... ... ... ... ... 90FFFh 48 30000h 30FFFh 143 8F000h 8FFFFh 47 2F000h 2FFFFh ... ... ... ... ... ... 2 128 80000h 80FFFh 32 20000h 20FFFh 127 7F000h 7FFFFh 31 1F000h 1FFFFh ... ... ... 16 10000h 10FFFh 111 6F000h 6FFFFh 15 0F000h 0FFFFh ... ... 70FFFh ... ... 70000h 96 60000h 60FFFh 4 04000h 04FFFh 95 5F000h 5FFFFh 3 03000h 03FFFh 02000h 02FFFh 0 ... ... ... 1 112 2 80 50000h 50FFFh 1 01000h 01FFFh 79 4F000h 4FFFFh 0 00000h 00FFFh ... 4 3FFFFh ... 5 3 3F000h 90000h ... 6 63 Address range 144 ... 7 Subsector ... 8 9FFFFh ... 9 9F000h Sector ... 159 Address range ... Sector Memory organization (continued) ... Table 4. 64 40000h 40FFFh 21/65 Instructions 6 M25PX16 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 5. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ), Dual Output Fast Read (DOFR), Read OTP (ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Identification (RDID) or Release from Deep Power-down (RDP) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program (DIFP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write to Lock Register (WRLR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 5. Instruction Description One-byte instruction Address Dummy code bytes bytes Data bytes WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 1001 1111 9Fh 0 0 1 to 20 RDID Read Identification 1001 1110 9Eh 0 0 1 to 3 RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞ WRSR Write Status Register 0000 0001 01h 0 0 1 WRLR Write to Lock Register 1110 0101 E5h 3 0 1 RDLR Read Lock Register 1110 1000 E8h 3 0 1 READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞ Read Data Bytes at higher speed 0000 1011 0Bh 3 1 1 to ∞ Dual Output Fast Read 0011 1011 3Bh 3 1 1 to ∞ FAST_READ DOFR 22/65 Instruction set M25PX16 Instructions Table 5. One-byte instruction Address Dummy code bytes bytes Data bytes Instruction Description ROTP Read OTP (Read 64 bytes of OTP area) 0100 1011 4Bh 3 1 1 to 65 POTP Program OTP (Program 64 bytes of OTP area) 0100 0010 42h 3 0 1 to 65 Page Program 0000 0010 02h 3 0 1 to 256 DIFP Dual Input Fast Program 1010 0010 A2h 3 0 1 to 256 SSE Subsector Erase 0010 0000 20h 3 0 0 SE Sector Erase 1101 1000 D8h 3 0 0 BE Bulk Erase 1100 0111 C7h 0 0 0 DP Deep Power-down 1011 1001 B9h 0 0 0 Release from Deep Powerdown 1010 1011 ABh 0 0 0 PP RDP 6.1 Instruction set Write Enable (WREN) The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input Fast Program (DIFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 8. Write Enable (WREN) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction DQ0 High Impedance DQ1 AI13731 23/65 Instructions 6.2 M25PX16 Write Disable (WRDI) The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write lo Lock Register (WRLR) instruction completion Page Program (PP) instruction completion Dual Input Fast Program (DIFP) instruction completion Program OTP (POTP) instruction completion Subsector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction DQ0 High Impedance DQ1 AI13732 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: Manufacturer identification (1 byte) Device identification (2 bytes) A Unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (71h), and the memory capacity of the device in the second byte (15h). The UID contains the length of the following data in the first byte (set to 10h) and 16 bytes of the optional Customized Factory Data (CFD) content. The CFD bytes are read-only and can be programmed with customers data upon their demand. If the customers do not make requests, the devices are shipped with all the CFD bytes programmed to zero (00h). 24/65 M25PX16 Instructions See Section 12: Ordering information on page 62 for CFD programmed devices. Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The Read Identification (RDID) instruction should not be issued while the device is in Deep Power-down mode. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. After this, the 24-bit device identification, stored in the memory, the 8-bit CFD length followed by 16 bytes of CFD content will be shifted out on Serial Data output (DQ1). Each bit is shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 10. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 6. Read Identification (RDID) data-out sequence Device identification UID Manufacturer identification Memory type Memory capacity CFD length CFD content 71h 15h 10h 16 bytes 20h Figure 10. Read Identification (RDID) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 C Instruction DQ0 Manufacturer identification UID Device identification High Impedance DQ1 15 14 13 MSB MSB 3 2 1 0 MSB AI06809d 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 11. 25/65 Instructions M25PX16 Table 7. Status Register format b7 SRWD b0 0 TB BP2 BP1 BP0 WEL WIP Status Register Write Protect Top/Bottom bit Block Protect bits Write Enable Latch bit Write In Progress bit The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. 6.4.2 WEL bit The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 6.4.3 BP2, BP1, BP0 bits The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0. 6.4.4 TB bit The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Register (WRSR) instruction provided that the Write Enable (WREN) instruction has been issued. The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP0, BP1, BP2) bits to determine if the protected area defined by the Block Protect bits starts from the top or the bottom of the memory array: When TB is reset to ‘0’ (default value), the area protected by the Block Protect bits starts from the top of the memory array (see Table 3: Protected area sizes) When TB is set to ‘1’, the area protected by the Block Protect bits starts from the bottom of the memory array (see Table 3: Protected area sizes) The TB bit cannot be written when the SRWD bit is set to ‘1’ and the W pin is driven Low. 26/65 M25PX16 6.4.5 Instructions SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and the Write Protect (W/VPP) signal allow the device to be put in the hardware protected mode (when the Status Register Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W/VPP) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction DQ0 Status Register Out Status Register Out High Impedance DQ1 7 6 5 4 MSB 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB AI13734 6.5 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial Data input (DQ0). The instruction sequence is shown in Figure 12. The Write Status Register (WRSR) instruction has no effect on b6, b1 and b0 of the Status Register. b6 is always read as ‘0’. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows the user to set and reset the Status Register Write Disable (SRWD) bit in accordance with 27/65 Instructions M25PX16 the Write Protect (W/VPP) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the hardware protected mode (HPM). The Write Status Register (WRSR) instruction is not executed once the hardware protected mode (HPM) is entered. Figure 12. Write Status Register (WRSR) instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction Status Register In 7 DQ0 High Impedance 6 5 4 3 2 1 0 MSB DQ1 AI13735 Table 8. Protection modes W/VPP signal SRWD bit 1 0 0 0 1 0 1 1 Mode Write Protection of the Status Register Memory content Protected area(1) Unprotected area(1) Status Register is Writable (if the WREN instruction Software has set the WEL protected bit) (SPM) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Protected against Page Program, Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions Status Register is hardware write Hardware protected protected The values in the (HPM) SRWD, BP2, BP1 and BP0 bits cannot be changed Protected against Page Program, Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 3. The protection features of the device are summarized in Table 8. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W/VPP) is driven High or Low. 28/65 M25PX16 Instructions When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W/VPP): If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W/VPP) Low or by driving Write Protect (W/VPP) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write Protect (W/VPP) High. If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can never be activated, and only the Software Protected mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. 6.6 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 29/65 Instructions M25PX16 Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 MSB Data Out 1 High Impedance DQ1 7 6 5 4 3 2 Data Out 2 1 0 7 MSB AI13736 1. Address bits A23 to A22 are Don’t care. 6.7 Read Data Bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on Serial Data output (DQ1) at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at higher speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at higher speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at higher speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 30/65 M25PX16 Instructions Figure 14. Read Data Bytes at higher speed (FAST_READ) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 High Impedance DQ1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte DQ0 7 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 DQ1 7 6 5 4 MSB 3 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB AI13737 1. Address bits A23 to A22 are Don’t care. 6.8 Dual Output Fast Read (DOFR) The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Read Data Bytes at higher speed (FAST_READ) instruction. The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, are shifted out on DQ0 and DQ1 at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 15. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0 and DQ1. The whole memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction. 31/65 Instructions M25PX16 When the highest address is reached, the address counter rolls over to 00 0000h, so that the read sequence can be continued indefinitely. Figure 15. Dual Output Fast Read instruction sequence S Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 Mode 2 Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 High Impedance DQ1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte DQ0 DQ1 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 DATA OUT 1 DATA OUT 2 DATA OUT 3 DATA OUT n 7 7 7 5 3 MSB 1 7 MSB 5 3 1 MSB 5 3 1 MSB 5 3 1 MSB ai13574 1. A23 to A22 are Don't care. 6.9 Read Lock Register (RDLR) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any location inside the concerned sector. Each address bit is latched-in during the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output (DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 16. The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at any time during data output. Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 32/65 M25PX16 Instructions Table 9. Bit Lock Register out(1) Bit name Value Function b7-b2 b1 b0 Reserved ‘1’ The Write Lock and Lock Down bits cannot be changed. Once a ‘1’ is written to the Lock Down bit it cannot be cleared to ‘0’, except by a power-up. ‘0’ The Write Lock and Lock Down bits can be changed by writing new values to them. ‘1’ Write, Program and Erase operations in this sector will not be executed. The memory contents will not be changed. ‘0’ Write, Program and Erase operations in this sector are executed and will modify the sector contents. Sector Lock Down Sector Write Lock 1. Values of (b1, b0) after power-up are defined in Section 7: Power-up and power-down. Figure 16. Read Lock Register (RDLR) instruction sequence and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 MSB Lock Register Out High Impedance DQ1 7 6 5 4 3 2 1 0 MSB AI13738 6.10 Read OTP (ROTP) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). Each bit is shifted out at the maximum frequency, fCmax, on the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 17. The address is automatically incremented to the next higher address after each byte of data is shifted out. There is no rollover mechanism with the Read OTP (ROTP) instruction. This means that the Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read, since once the 65th byte has been read, the same (65th) byte keeps being read on the DQ1 pin. The Read OTP (ROTP) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read OTP (ROTP) 33/65 Instructions M25PX16 instruction issued while an Erase, Program or Write cycle is in progress, is rejected without having any effect on the cycle that is in progress. Figure 17. Read OTP (ROTP) instruction and data-out sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 High Impedance DQ1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy byte DQ0 7 6 5 4 3 2 1 0 DATA OUT n DATA OUT 1 DQ1 7 6 5 4 3 MSB 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB AI13573 1. A23 to A7 are Don't care. 2. 1 ≤ n ≤ 65. 6.11 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. 34/65 M25PX16 Instructions If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Table 18: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed. Figure 18. Page Program (PP) instruction sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-bit address 23 22 21 DQ0 3 2 Data byte 1 1 0 7 6 5 4 3 2 1 0 MSB MSB 2078 2079 2077 2076 2075 2074 2073 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 S 1 0 C Data byte 2 DQ0 7 6 MSB 5 4 3 2 Data byte 3 1 0 7 MSB 6 5 4 3 2 Data byte 256 1 0 7 6 5 4 3 2 MSB AI13739 1. Address bits A23 to A22 are Don’t care. 35/65 Instructions 6.12 M25PX16 Dual Input Fast Program (DIFP) The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP) instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Page Program (PP) instruction. The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data input (DQ0). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 19. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes in the same page. For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP) instruction to program all consecutive targeted bytes in a single sequence rather to using several Dual Input Fast Program (DIFP) sequences each containing only a few bytes (see Table 18: AC characteristics). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 3) is not executed. 36/65 M25PX16 Instructions Figure 19. Dual Input Fast Program (DIFP) instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-bit address 23 22 21 DQ0 3 2 1 0 High Impedance DQ1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C DQ0 6 4 2 0 DATA IN 1 DQ1 7 MSB 5 3 6 4 2 0 DATA IN 2 1 7 MSB 5 3 6 4 2 0 6 DATA IN 3 1 7 MSB 5 3 4 2 0 6 DATA IN 4 1 7 MSB 5 3 4 2 0 DATA IN 5 1 7 MSB 5 3 6 4 2 0 DATA IN 256 1 7 5 3 1 MSB 1. A23 to A22 are Don't care. 6.13 Program OTP instruction (POTP) The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) bit. The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the instruction opcode, three address bytes and at least one data byte on Serial Data input (DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Program OTP instruction is not executed. There is no rollover mechanism with the Program OTP (POTP) instruction. This means that the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program, once all 65 bytes have been latched in, any following byte will be discarded. The instruction sequence is shown in Figure 20. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register 37/65 Instructions M25PX16 may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. To lock the OTP memory: Bit 0 of the OTP control byte, that is byte 64, (see Figure 21) is used to permanently lock the OTP memory array. When bits 3, 2, 1 and 0 of byte 64 = ’1’, the 64 bytes of the OTP memory array can be programmed. When bits 3, 2, 1, and 0 of byte 64 = ‘0’, the 64 bytes of the OTP memory array are read-only and cannot be programmed anymore. Once a bit of the OTP memory has been programmed to ‘0’, it can no longer be set to ‘1’. Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in progress is rejected without having any effect on the cycle that is in progress. Figure 20. Program OTP (POTP) instruction sequence S 0 1 2 3 4 5 6 7 8 28 29 30 31 32 33 34 35 36 37 38 39 9 10 C Instruction 24-bit address 23 22 21 DQ0 3 2 Data byte 1 1 0 7 6 5 4 3 2 0 1 MSB MSB S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data byte 2 DQ0 7 6 5 4 3 MSB 2 Data byte 3 1 0 7 MSB 6 5 4 3 2 Data byte n 1 0 7 6 5 4 3 2 1 0 MSB AI13575 1. A23 to A7 are Don't care. 2. 1 ≤ n ≤ 65 38/65 M25PX16 Instructions Figure 21. How to permanently lock the 64 OTP bytes 64 data bytes OTP Control byte Byte Byte Byte 0 1 2 Byte Byte 63 64 X X X X bit 3 bit 2 bit 1 bit 0 When bits 3, 2, 1, and 0 = 0, the 64 OTP bytes become READ only Bit 4 to bit 7 are NOT programmable ai13587 6.14 Write to Lock Register (WRLR) The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes (pointing to any address in the targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is shown in Figure 22. Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed. Lock Register bits are volatile, and therefore do not require time to be written. When the Write to Lock Register (WRLR) instruction has been successfully executed, the Write Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value. Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 22. Write to Lock Register (WRLR) instruction sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction DQ0 Lock Register In 24-Bit Address 23 22 21 MSB 3 2 1 0 7 6 5 4 3 2 1 0 MSB AI13740 39/65 Instructions M25PX16 Lock Register in(1) Table 10. Sector All sectors Bit Value b7-b2 ‘0’ b1 Sector Lock Down bit value (refer to Table 9) b0 Sector Write Lock bit value (refer to Table 9) 1. Values of (b1, b0) after power-up are defined in Section 7: Power-up and power-down. 6.15 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (DQ0). Any address inside the Subsector (see Table 4) is a valid address for the Subsector Erase (SSE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 23. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is tSSE) is initiated. While the Subsector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Subsector Erase (SSE) instruction issued to a sector that is hardware or software protected, is not executed. Any Subsector Erase (SSE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 23. Subsector Erase (SSE) instruction sequence S 0 1 2 3 4 5 6 7 8 9 29 30 31 C Instruction DQ0 24 Bit Address 23 22 2 1 0 MSB AI13741 1. Address bits A23 to A22 are Don’t care. 40/65 M25PX16 6.16 Instructions Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial Data input (DQ0). Any address inside the Sector (see Table 4) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 24. Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 3 and Table 4) is not executed. Figure 24. Sector Erase (SE) instruction sequence S 0 1 2 3 4 5 6 7 8 9 29 30 31 C Instruction 24 Bit Address 23 22 DQ1 2 1 0 MSB AI13742 1. Address bits A23 to A22 are Don’t care. 6.17 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 25. 41/65 Instructions M25PX16 Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Figure 25. Bulk Erase (BE) instruction sequence S 0 1 2 3 4 5 6 7 C Instruction DQ0 AI13743 6.18 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as a software protection mechanism, while the device is not in active use, as in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 17). To take the device out of Deep Power-down mode, the Release from Deep Power-down (RDP) instruction must be issued. No other instruction must be issued while the device is in Deep Power-down mode. The Deep Power-down mode automatically stops at power-down, and the device always powers up in the Standby Power mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 26. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as 42/65 M25PX16 Instructions Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 26. Deep Power-down (DP) instruction sequence S 0 1 2 3 4 5 6 7 tDP C Instruction DQ0 Standby mode Deep Power-down mode AI13744 6.19 Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 27. The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the instruction to be rejected, and not executed. After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the Standby mode. Chip Select (S) must remain High at least until this period is over. The device waits to be selected, so that it can receive, decode and execute instructions. Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. 43/65 Instructions M25PX16 Figure 27. Release from Deep Power-down (RDP) instruction sequence S 0 1 2 3 4 5 6 7 tRDP C Instruction DQ0 High Impedance DQ1 Deep Power-down mode Standby mode AI13745 44/65 M25PX16 7 Power-up and power-down Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC(min) at power-up, and then for a further delay of tVSL VSS at power-down A safe configuration is provided in Section 3: SPI modes. To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Dual Input Fast Program (DIFP), Program OTP (POTP), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR) and Write to Lock Register (WRLR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: tPUW after VCC has passed the VWI threshold tVSL after VCC has passed the VCC(min) level. These values are specified in Table 11. If the time, tVSL, has elapsed, after VCC rises above VCC(min), the device can be selected for READ instructions even if the tPUW delay has not yet fully elapsed. After power-up, the device is in the following state: The device is in the Standby Power mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. The Write In Progress (WIP) bit is reset. The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0) Normal precautions must be taken for supply line decoupling, to stabilize the VCC supply. Each device in a system should have the VCC line decoupled by a suitable capacitor close to the package pins (generally, this capacitor is of the order of 100 nF). At power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption may result.) VPPH must be applied only when VCC is stable and in the VCCmin to VCCmax voltage range. 45/65 Power-up and power-down M25PX16 Figure 28. Power-up timing VCC VCC(max) Program, Erase and Write commands are rejected by the device Chip Selection not allowed VCC(min) tVSL Reset state of the device Read Access allowed Device fully accessible VWI tPUW time AI04009C Table 11. Power-up timing and VWI threshold Symbol Parameter Max Unit tVSL(1) VCC(min) to S low 30 tPUW(1) Time delay to write instruction 1 10 ms VWI(1) Write Inhibit voltage 1.5 2.1 V 1. These parameters are characterized only. 46/65 Min µs M25PX16 8 Initial delivery state Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 47/65 Maximum rating 9 M25PX16 Maximum rating Stressing the device outside the ratings listed in Table 12: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE program and other relevant quality documents. Table 12. Absolute maximum ratings Symbol TSTG TLEAD Parameter Storage temperature Min Max Unit –65 150 °C (1) Lead temperature during soldering see °C VIO Input and output voltage (with respect to ground) –0.6 VCC+0.6 V VCC Supply voltage –0.6 4.0 V –0.2 10.0 V –2000 2000 V VPP VESD Fast Program/Erase voltage(2) Electrostatic discharge voltage (Human Body model)(3) 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. Avoid applying VPPH to the W/VPP pin during Bulk Erase. 3. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω). Table 13. Data Retention Parameter 48/65 Condition Min Max Unit Program/Erase Cycles Grade 3, Autograde 6, Grade 6 100000 Cycles per Sector Data Retention at 55°C 20 years M25PX16 10 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 14. Operating conditions Symbol Supply Voltage(*) Min Typ Max Unit VCC Supply Voltage 2.3 3.6 V VPPH Supply Voltage on Vpp 8.5 9.5 V TA Ambient operating temperature (device grade 6) -40 +85 V TA Ambient operating temperature (device grade 3) -40 +125 °C Table 15. AC measurement conditions Symbol Parameter Min Max Unit CL Load capacitance CL Input rise and fall times CL Input pulse voltages 0.2VCC to 0.8VCC V CL Input timing reference voltages 0.3VCC to 0.7VCC V CL Output timing reference voltages VCC / 2 V 30 pF 5 ns 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 29. AC measurement I/O waveform Input levels Input and output timing reference levels 0.8VCC 0.7VCC 0.5VCC 0.3VCC 0.2VCC AI07455 Table 16. Symbol CIN/OUT CIN Capacitance(1) Parameter Input/output capacitance (DQ0/DQ1) Input capacitance (other pins) Test condition Min Max Unit VOUT = 0 V 8 pF VIN = 0 V 6 pF 1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 33 MHz. 49/65 DC and AC parameters Table 17. M25PX16 DC characteristics Symbol Test condition (in addition to those in Table 14) Parameter Min Max Unit ILI Input leakage current ±2 µA ILO Output leakage current ±2 µA ICC1 Standby current S = VCC, VIN = VSS or VCC 50 µA ICC2 Deep Power-down current S = VCC, VIN = VSS or VCC 10 µA C = 0.1VCC / 0.9VCC at 75 MHz, DQ1 = open 12 mA C = 0.1VCC / 0.9VCC at 33 MHz, DQ1 = open 4 mA C = 0.1VCC / 0.9VCC at 75 MHz, DQ1 = open 15 mA Operating current (PP) S = VCC 15 mA Operating current (DIFP) S = VCC 15 mA ICC5 Operating current (WRSR) S = VCC 15 mA ICC6 Operating current (SE) S = VCC 15 mA ICC7 Operating current (BE) S = VCC 15 mA VIL Input low voltage – 0.5 0.3VCC V VIH Input high voltage 0.7VCC VCC+0.4 V VOL Output low voltage IOL = 1.6 mA 0.4 V VOH Output high voltage IOH = –100 µA Operating current (READ) ICC3 Operating current (DOFR) ICC4 Table 18. VCC–0.2 V AC characteristics(1) Test conditions specified in Table 14 and Table 15 Symbol fC Alt. Parameter Min fC Clock frequency for the following instructions: DOFR, DIFP, FAST_READ, SSE, SE, BE, DP, WREN, WRDI, RDID, RDSR, WRSR, ROTP, PP, POTP, WRLR, RDLR, RDP Clock frequency for READ instructions fR Typ(2) Max Unit D.C. 75 MHz D.C. 33 MHz tCH(3) tCLH Clock High time 6 ns tCL(2) tCLL Clock Low time 6 ns 0.1 V/ns 0.1 V/ns S active setup time (relative to C) 5 ns S not active hold time (relative to C) 5 ns tCLCH (4) tCHCL (4) tSLCH Clock rise Clock fall tCSS tCHSL time(5) time(5) (peak to peak) (peak to peak) tDVCH tDSU Data In setup time 2 ns tCHDX tDH Data In hold time 5 ns 50/65 M25PX16 Table 18. DC and AC parameters AC characteristics(1) (continued) Test conditions specified in Table 14 and Table 15 Symbol Alt. Parameter Min Typ(2) Max Unit tCHSH S active hold time (relative to C) 5 ns tSHCH S not active setup time (relative to C) 5 ns tCSH S deselect time 80 ns tDIS Output Disable time 8 ns Clock Low to Output valid under 30 pF 8 ns Clock Low to Output valid under 10 pF 6 ns tSHSL tSHQZ (4) tCLQV tV tCLQX tHO Output hold time 0 ns tHLCH HOLD setup time (relative to C) 5 ns tCHHH HOLD hold time (relative to C) 5 ns tHHCH HOLD setup time (relative to C) 5 ns tCHHL HOLD hold time (relative to C) 5 ns tHHQX(4) tLZ HOLD to Output Low-Z 8 ns tHLQZ(4) tHZ HOLD to Output High-Z 8 ns tWHSL(6) tSHWL (6) tVPPHSL(7) tDP(4) (4) tRDP tW tPP(8) Write Protect setup time 20 ns Write Protect hold time 100 ns Enhanced Program supply voltage High (VPPH) to Chip Select Low 200 ns S High to Deep Power-down mode 3 µs S High to Standby mode 30 µs 15 ms Write Status Register cycle time 1.3 Page Program cycle time (256 bytes) 0.8 ms Page Program cycle time (n bytes) int(n/8) × 0.025(9) Program OTP cycle time (64 bytes) 0.2 tSSE Subsector Erase cycle time 70 150 ms tSE Sector Erase cycle time 0.6 3 s tBE Bulk Erase cycle time 15 80 s 5 ms 1. 75 MHz operations are allowed only on the VCC range 2.7 V - 3.6 V. 2. Typical values given for TA = 25° C. 3. tCH + tCL must be greater than or equal to 1/ fC. 4. Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction when SRWD is set at ‘1’. 7. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure) is known. Avoid applying VPPH to the W/VPP pin during Bulk Erase. 8. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are obtained with one sequence including all the bytes versus several sequences of only a few bytes (1 ≤ n ≤ 256). 9. int(A) corresponds to the upper integer part of A. For example, int(12/8) = 2, int(32/8) = 4 int(15.3) =16. 51/65 DC and AC parameters Table 19. M25PX16 AC characteristics (50 MHz operation)(1) Test conditions specified in Table 14 and Table 15. Symbol fC Alt. fC fR Parameter Min Typ Max Unit Clock frequency(1) for the following instructions: DOFR, DIFP, FAST_READ, PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR D.C. 50 MHz Clock frequency for read instructions D.C. 25 MHz tCH(2) tCLH Clock high time 9 ns (2) tCLL Clock low time 9 ns 0.1 V/ns 0.1 V/ns S active setup time (relative to C) 5 ns S not active hold time (relative to C) 5 ns tCL tCLCH (3) Clock rise (peak to peak) Clock fall time(4) (peak to peak) tCHCL(3) tSLCH time(4) tCSS tCHSL tDVCH tDSU Data in setup time 2 ns tCHDX tDH Data in hold time 5 ns tCHSH S active hold time (relative to C) 5 ns tSHCH S not active setup time (relative to C) 5 ns 100 ns tSHSL tCSH S deselect time tSHQZ(3) tDIS Output disable time 8 ns tCLQV tV Clock Low to Output Valid 8 ns tCLQX tHO Output hold time 0 ns tHLCH HOLD setup time (relative to C) 5 ns tCHHH HOLD hold time (relative to C) 5 ns tHHCH HOLD setup time (relative to C) 5 ns tCHHL HOLD hold time (relative to C) 5 ns tHHQX(3) tLZ HOLD to Output Low-Z 8 ns tHLQZ(3) tHZ HOLD to Output High-Z 8 ns tWHSL (5) Write protect setup time 20 ns tSHWL (5) Write protect hold time 100 ns tDP(3) S High to deep power-down mode 3 µs tRDP(3) S High to standby mode 30 µs 1. 50 MHz operation is also available on VCC range 2.3 to 2.7 V. 2. tCH + tCL must be greater than or equal to 1/ fC. 3. Value guaranteed by characterization, not 100% tested in production. 4. Expressed as a slew-rate. 5. Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’. 52/65 M25PX16 DC and AC parameters Figure 30. Serial input timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX DQ0 DQ1 MSB IN tCLCH LSB IN High Impedance AI13728 Figure 31. Write Protect Setup and Hold timing during WRSR when SRWD=1 W/VPP tSHWL tWHSL S C DQ0 High Impedance DQ1 AI07439c 53/65 DC and AC parameters M25PX16 Figure 32. Hold timing S tHLCH tCHHL tHHCH C tCHHH tHLQZ tHHQX DQ1 DQ0 HOLD AI13746 Figure 33. Output timing S tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT DQ1 tQLQH tQHQL ADDR. DQ0 LSB IN AI13729 54/65 M25PX16 DC and AC parameters Figure 34. VPPH timing End of command (identi ed by WIP polling) S C DQ0 VPPH VPP tVPPHSL ai13726-b 55/65 Package mechanical 11 M25PX16 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in RoHS packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 35. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead, 6 × 5 mm, package outline A D aaa C A R1 D1 E1 E2 e bbb E M C A B B 2x b aaa C B 0.10 C B 0.10 C A D2 θ L A2 ddd A C A1 A3 70-ME 1. Drawing is not to scale. Table 20. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead, 6 × 5 mm, package mechanical data Millimeters Inches Symbol A Typ Min Max Typ Min Max 0.85 0.80 1.00 0.0335 0.0315 0.0394 0.00 0.05 0.0000 0.0020 0.0138 0.0189 0.1260 0.1417 A1 56/65 A2 0.65 0.0256 A3 0.20 0.0079 b 0.40 D 6.00 0.2362 D1 5.75 0.2264 D2 3.40 E 5.00 0.1969 E1 4.75 0.1870 E2 4.00 3.80 4.30 0.1575 0.1496 0.1693 e 1.27 – – 0.0500 – – R1 0.10 0.00 0.0039 0.0000 0.35 3.20 0.48 3.60 0.0157 0.1339 M25PX16 Package mechanical Table 20. VFQFPN8 (MLP8) 8-lead very thin fine pitch dual flat package no lead, 6 × 5 mm, package mechanical data Millimeters Inches Symbol L Typ Min Max Typ Min Max 0.60 0.50 0.75 0.0236 0.0197 0.0295 Θ 12° 12° aaa 0.15 0.0059 bbb 0.10 0.0039 ddd 0.05 0.0020 Figure 36. SO8W 8-lead plastic small outline, 208 mils body width, package outline A2 A c b CP e D N E E1 1 A1 k L 6L_ME 1. Drawing is not to scale. Table 21. SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data Millimeters Inches Symbol Typ Min A Max Typ Min 2.50 Max 0.098 A1 0.00 0.25 0.000 0.010 A2 1.51 2.00 0.059 0.079 b 0.40 0.35 0.51 0.016 0.014 0.020 c 0.20 0.10 0.35 0.008 0.004 0.014 CP 0.10 0.004 D 6.05 0.238 E 5.02 6.22 0.198 0.245 E1 7.62 8.89 0.300 0.350 57/65 Package mechanical M25PX16 Table 21. SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data Millimeters Inches Symbol Typ Min Max Typ Min Max 1.27 – – 0.050 – – k 0° 10° 0° 10° L 0.50 0.80 0.020 0.031 N 8 e 8 Figure 37. SO8N – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 22. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data millimeters inches Symbol Typ Min A Typ Min 1.75 Max 0.069 A1 0.10 A2 1.25 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 58/65 Max 0.25 0.004 0.010 0.049 0.10 0.004 D 4.90 4.80 5.00 0.193 0.189 0.197 E 6.00 5.80 6.20 0.236 0.228 0.244 E1 3.90 3.80 4.00 0.154 0.150 0.157 e 1.27 – – 0.050 – – M25PX16 Package mechanical Table 22. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data millimeters inches Symbol Typ Min Max h 0.25 k L L1 1.04 Typ Min Max 0.50 0.010 0.020 0° 8° 0° 8° 0.40 1.27 0.016 0.050 0.041 59/65 Package mechanical Figure 38. TBGA, 6x8 mm, 24 ball package outline 60/65 M25PX16 M25PX16 Package mechanical Table 23. TBGA 6x8 mm 24-ball package dimensions MIN NOM A A1 MAX 1.20 0.20 A2 0.79 Øb 0.35 0.40 0.45 D 5.90 6.00 6.10 D1 E 4.00 7.90 8.00 E1 4.00 eD 1.00 eE 1.00 FD 1.00 FE 2.00 MD 5 ME 5 n 24 balls 8.10 aaa 0.15 bbb 0.10 ddd 0.10 eee 0.15 fff 0.08 Control unit: mm 61/65 Ordering information 12 Ordering information Table 24. Ordering information scheme Example: M25PX16 M25PX16 – V MW 6 T P B Device type M25PX = serial Flash memory, 4-Kbyte and 64-Kbyte erasable sectors, dual input/output Device function 16 = 16 Mbit (2 Mbit × 8) Security features(1) – = no extra security SO = OTP configurable + CFD programmed with UID ST = OTP configurable + protection at power_up + CFD programmed with UID S– = CFD programmed with UID Operating voltage V = VCC = 2.3 V to 3.6 V (Automotive part available only in 2.7 - 3.6 V) Package MW = SO8W (208 mils width) MN = SO8N (150 mils width) MP = VFQFPN 6 × 5 mm (MLP8) ZM = TBGA24 6 x 8 mm ME = VDFPN8 8 × 6 mm (MLP8) Device grade 6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow] 3(2) = Automotive grade 3 temperature range, –40 to 125 °C. Device tested with High Reliability Certified Flow Option blank = Standard packing (Tube for SO8N, SO8W, SO16, and PDIP packages; Tray for MLP and BGA packages) T = Tape and reel packing Plating technology P or G = RoHS compliant Lithography B = 110 nm, Fab.2 Diffusion Plant (Automotive Only) blank = 110 nm Automotive grade A(2) = Automotive grade 6 temperature range, –40 to 85 °C Device tested with High Reliability Certified Flow blank = standard device temperature range, –40 to 85 °C 1. Secure options are available upon customer request. 2. Numonyx strongly recommends the use of the Automotive Grade devices (AutoGrade 6 and Grade 3) for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. 62/65 A M25PX16 Note: Ordering information For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. 63/65 Revision history M25PX16 13 Revision history Table 25. Document revision history Date Revision 12-Aug-2008 1 Initial release. 27-Aug-2008 2 Corrected bulk erase specifications on the cover page; Changed Vwi from 2.5 V to 2.1 V in Table 11: Power-up timing and VWI threshold on page 46 due to 2.3 V operations; Corrected the programmable bit range in Table 21: How to permanently lock the 64 OTP bytes on page 39. 24-Sept-2008 3 Added the following information regarding Bulk Erase: Avoid applying VPPH to the W/VPP pin during Bulk Erase. 04-February-2009 4 Added the TBGA package and accompanying informaiton. 16-February-2009 5 Added Notes to the TBGA package. 17-March-2009 6 Made the following changes: – Added “Automotive certified parts” information to cover page, and to Ordering Information; – Added Data Retention table; – Revised the Operating Condition table. 22-June-2009 7 Corrected data in Table 14.: Operating conditions. Revised and clarified ordering information. 10-March-2010 8 Removed SO16W package information from Ordering Information table. 64/65 Changes M25PX16 Please Read Carefully: INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2010, Numonyx, B.V., All Rights Reserved. 65/65