LINER LTC2283IUP-TR Dual 12-bit, 125msps low power 3v adc Datasheet

LTC2283
Dual 12-Bit, 125Msps
Low Power 3V ADC
FEATURES
DESCRIPTION
n
The LTC®2283 is a 12-bit 125Msps, low power dual 3V
A/D converter designed for digitizing high frequency,
wide dynamic range signals. The LTC2283 is perfect for
demanding imaging and communications applications
with AC performance that includes 70.1dB SNR and 82dB
SFDR for signals at the Nyquist frequency.
n
n
n
n
n
n
n
n
n
n
n
n
Integrated Dual 12-Bit ADCs
Sample Rate: 125Msps
Single 3V Supply (2.85V to 3.4V)
Low Power: 790mW
70.2dB SNR, 88dB SFDR
110dB Channel Isolation at 100MHz
Flexible Input: 1VP-P to 2VP-P Range
640MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
125Msps: LTC2283 (12-Bit), LTC2285 (14-Bit)
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
64-Pin (9mm × 9mm) QFN Package
Typical DC specs include ±0.4LSB INL, ±0.2LSB DNL. The
transition noise is a low 0.32LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic.
A single-ended CLK input controls converter operation.
An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
A data ready output clock (CLKOUT) can be used to latch
the output data.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
APPLICATIONS
n
n
n
n
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
TYPICAL APPLICATION
INPUT
S/H
–
CLK A
CLOCK/DUTY CYCLE
CONTROL
CLK B
CLOCK/DUTY CYCLE
CONTROL
OVDD
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
73
D11A
••
•
D0A
72
OGND
71
OF
MUX
CLKOUT
SNR (dBFS)
+
ANALOG
INPUT A
SNR vs Input Frequency,
–1dB, 2V Range
70
69
68
67
66
OVDD
+
ANALOG
INPUT B
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D11B
••
•
65
0
50
100 150 200 250 300 350
INPUT FREQUENCY (MHz) 2283 TA01b
D0B
OGND
2283 TA01
2283fb
1
LTC2283
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
OVDD = VDD (Notes 1, 2)
64 GND
63 VDD
62 SENSEA
61 VCMA
60 MODE
59 SHDNA
58 OEA
57 OF
56 DA11
55 DA10
54 DA9
53 DA8
52 DA7
51 DA6
50 OGND
49 OVDD
TOP VIEW
AINA+ 1
AINA– 2
REFHA 3
REFHA 4
REFLA 5
REFLA 6
VDD 7
CLKA 8
CLKB 9
VDD 10
REFLB 11
REFLB 12
REFHB 13
REFHB 14
AINB– 15
AINB+ 16
48 DA5
47 DA4
46 DA3
45 DA2
44 DA1
43 DA0
42 NC
41 NC
40 CLKOUT
39 DB11
38 DB10
37 DB9
36 DB8
35 DB7
34 DB6
33 DB5
65
GND 17
VDD 18
SENSEB 19
VCMB 20
MUX 21
SHDNB 22
OEB 23
NC 24
NC 25
DB0 26
DB1 27
DB2 28
DB3 29
DB4 30
OGND 31
OVDD 32
Supply Voltage (VDD) ..................................................4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Analog Input Voltage (Note 3) .......–0.3V to (VDD + 0.3V)
Digital Input Voltage......................–0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation .............................................1500mW
Operating Temperature Range
LTC2283C ................................................ 0°C to 70°C
LTC2283I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
UP PACKAGE
64-LEAD (9mm × 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND AND MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2283CUP#PBF
LTC2283CUP#TRPBF
LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2283IUP#PBF
LTC2283IUP#TRPBF
LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2283CUP
LTC2283CUP#TR
LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
0°C to 70°C
LTC2283IUP
LTC2283IUP#TR
LTC2283UP
64-Lead (9mm × 9mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
12
Differential Analog Input (Note 5)
●
–2
±0.4
2
LSB
Differential Linearity Error
Differential Analog Input
●
–0.9
±0.2
0.9
LSB
Offset Error
(Note 6)
●
–12
±2
12
mV
Gain Error
External Reference
●
–2.5
±0.5
2.5
%FS
Resolution (No Missing Codes)
Integral Linearity Error
Offset Drift
Full-Scale Drift
Gain Matching
Bits
±10
μV/°C
Internal Reference
±30
ppm/°C
External Reference
±5
ppm/°C
External Reference
±0.3
%FS
2283fb
2
LTC2283
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
MIN
TYP
Offset Matching
MAX
UNITS
±2
Transition Noise
SENSE = 1V
mV
0.32
LSBRMS
ANALOG INPUT
The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (AIN+ –AIN–)
2.85V < VDD < 3.4V (Note 7)
●
VIN,CM
Analog Input Common Mode (AIN+ +AIN–)/2
Differential Input Drive (Note 7)
Single Ended Input Drive (Note 7)
●
●
1
0.5
IIN
Analog Input Leakage Current
0V < AIN+, AIN– < VDD
●
ISENSE
SENSEA, SENSEB Input Leakage
0V < SENSEA, SENSEB < 1V
IMODE
MODE Input Leakage Current
0V < MODE < VDD
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0.2
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
640
MHz
Full Power Bandwidth
MIN
TYP
MAX
UNITS
±0.5V to ±1V
1.5
1.5
V
1.9
2
V
V
–1
1
μA
●
–3
3
μA
●
–3
3
μA
0
Figure 8 Test Circuit
ns
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
SNR
Signal-to-Noise Ratio
CONDITIONS
MIN
70.2
dB
70.1
dB
●
68
5MHz Input
30MHz Input
70MHz Input
●
70
140MHz Input
SFDR
Spurious Free Dynamic Range
4th Harmonic or Higher
dB
88
dB
85
dB
82
dB
78
dB
90
dB
90
dB
90
dB
90
dB
69.8
dB
●
77
5MHz Input
30MHz Input
70MHz Input
140MHz Input
IMD
dB
30MHz Input
70MHz Input
Signal-to-Noise Plus Distortion Ratio
70
69.6
5MHz Input
140MHz Input
S/(N+D)
UNITS
5MHz Input
70MHz Input
Spurious Free Dynamic Range
2nd or 3rd Harmonic
MAX
30MHz Input
140MHz Input
SFDR
TYP
Intermodulation Distortion
fIN = 40MHz, 41MHz
Crosstalk
fIN = 100MHz
●
67
69.7
dB
69.6
dB
69.5
dB
85
dB
–110
dB
2283fb
3
LTC2283
INTERNAL REFERENCE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.475
1.500
1.525
V
VCM Output Tempco
±25
ppm/°C
VCM Line Regulation
2.85V < VDD < 3.4V
3
mV/V
VCM Output Resistance
|IOUT| < 1mA
4
Ω
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, SHDN, MUX)
VIH
High Level Input Voltage
VDD = 3V
●
2
V
VIL
Low Level Input Voltage
VDD = 3V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10μA
IO = –200μA
●
IO = 10μA
IO = 1.6mA
●
–10
0.8
V
10
μA
3
pF
LOGIC OUTPUTS
OVDD = 3V
VOL
Low Level Output Voltage
2.7
2.995
2.99
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200μA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
VOH
High Level Output Voltage
IO = –200μA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
2283fb
4
LTC2283
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
VDD
Analog Supply Voltage
(Note 9)
●
2.85
3
3.4
0.5
UNITS
V
OVDD
Output Supply Voltage
(Note 9)
●
3
3.6
V
IVDD
Supply Current
Both ADCs at fS(MAX)
●
263
305
mA
PDISS
Power Dissipation
Both ADCs at fS(MAX)
●
790
915
mW
PSHDN
Shutdown Power (Each Channel)
SHDN = H, OE = H, No CLK
2
mW
PNAP
Nap Mode Power (Each Channel)
SHDN = H, OE = L, No CLK
15
mW
TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
fs
Sampling Frequency
(Note 9)
●
1
tL
CLK Low Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
3.8
3
tH
CLK High Time
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
3.8
3
tAP
Sample-and-Hold Aperture Delay
tD
CLK to DATA Delay
tC
tMD
MIN
TYP
MAX
UNITS
125
MHz
4
4
500
500
ns
ns
4
4
500
500
ns
ns
0
CL = 5pF (Note 7)
●
CLK to CLKOUT Delay
CL = 5pF (Note 7)
DATA to CLKOUT Skew
(tD – tC) (Note 7)
MUX to DATA Delay
Data Access Time After OE↓
BUS Relinquish Time
(Note 7)
ns
1.4
2.7
●
1.4
2.7
5.4
ns
●
–0.6
0
0.6
ns
CL = 5pF (Note 7)
●
1.4
2.7
5.4
ns
CL = 5pF (Note 7)
●
4.3
10
ns
●
3.3
8.5
ns
Pipeline Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 125MHz, input range = 2VP-P with differential
drive, unless otherwise noted.
5
5.4
ns
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 125MHz, input range = 1VP-P with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9: Recommended operating conditions.
2283fb
5
LTC2283
TYPICAL PERFORMANCE CHARACTERISTICS
Crosstalk vs Input Frequency
Typical INL, 2V Range, 125Msps
INL ERROR (LSB)
–110
–115
–120
–125
–130
0
20
40
60
80
INPUT FREQUENCY (MHz)
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0
–0.2
–0.4
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
100
–1.0
1024
0
2283 G01
8192 Point FFT, fIN = 5MHz,
–1dB, 2V Range, 125Msps
2048
CODE
3072
4096
0
0
–10
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dB)
0
–50
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–100
–100
–110
–110
–110
–120
–120
20
30
40
FREQUENCY (MHz)
50
60
0
–10
–20
–20
–30
–30
AMPLITUDE (dB)
AMPLITUDE (dB)
0
–40
–50
–60
–70
–80
–120
60
20
30
40
FREQUENCY (MHz)
60
50
2283 G06
70000
58717
60000
50000
–70
40000
30000
–80
–100
–110
–110
–120
–120
2283 G07
10
Grounded Input
Histogram, 125Msps
–60
–100
60
0
2283 G05
–50
–90
50
50
–40
–90
20
30
40
FREQUENCY (MHz)
20
30
40
FREQUENCY (MHz)
8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz,
–1dB, 2V Range, 125Msps
–10
10
10
2283 G04
8192 Point FFT, fIN = 140MHz,
–1dB, 2V Range, 125Msps
0
0
4096
2283 G03
–50
–90
10
3072
–40
–90
0
2048
CODE
8192 Point FFT, fIN = 70MHz,
–1dB, 2V Range, 125Msps
–10
–40
1024
0
2283 G02
8192 Point FFT, fIN = 30MHz,
–1dB, 2V Range, 125Msps
AMPLITUDE (dB)
AMPLITUDE (dB)
0.2
–0.6
COUNT
CROSSTALK (dB)
–105
Typical DNL, 2V Range, 125Msps
1.0
DNL ERROR (LSB)
–100
20000
10000
0
10
20
30
40
FREQUENCY (MHz)
50
60
2283 G08
0
4249
2562
0
2044
2045
2046
CODE
2047
0
2048
2283 G09
2283fb
6
LTC2283
TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency,
–1dB, 2V Range, 125Msps
SFDR vs Input Frequency,
–1dB, 2V Range, 125Msps
SNR and SFDR vs Sample Rate,
2V Range, fIN = 5MHz, –1dB
95
73
90
SFDR
72
90
69
68
SNR AND SFDR (dBFS)
70
SFDR (dBFS)
SNR (dBFS)
71
85
80
75
67
80
SNR
70
60
70
66
65
65
0
50
0
150 200 250 300 350
2283 G10
INPUT FREQUENCY (MHz)
100
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
50
350
0
40 60 80 100 120 140 160
SAMPLE RATE (Msps)
20
2283 G11
SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
SNR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
290
100
dBFS
SFDR (dBc AND dBFS)
60
50
dBc
40
30
20
10
–40
–20
–30
INPUT LEVEL (dBFS)
–10
0
270
80
260
70
dBc
60
50
40
210
10
200
190
0
–60
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
0
20
60
80 100
40
SAMPLE RATE (Msps)
120
140
2283 G15
SNR vs SENSE, fIN = 5MHz, –1dB
71
12
70
10
69
SNR (dBFS)
14
8
6
68
67
4
66
2
65
0
80 100
60
SAMPLE RATE (Msps)
0
2283 G14
72
40
1V RANGE
230
20
16
20
2V RANGE
240
220
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB, 0VDD = 1.8V
0
250
30
2283 G13
IOVDD (mA)
–50
280
dBFS
90
IVDD (mA)
70
SNR (dBc AND dBFS)
IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
110
80
0
–60
2283 G12
120
140
2283 G16
64
0.4
0.5
0.6
0.7 0.8 0.9
SENSE PIN (V)
1.0
1.1
2283 G17
2283fb
7
LTC2283
PIN FUNCTIONS
AINA+ (Pin 1): Channel A Positive Differential Analog
Input.
AINA– (Pin 2): Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4): Channel A High Reference. Short together and bypass to Pins 5, 6 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
REFLA (Pins 5, 6): Channel A Low Reference. Short together and bypass to Pins 3, 4 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
VDD (Pins 7, 10, 18, 63): Analog 3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
CLKA (Pin 8): Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9): Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12): Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also bypass to Pins 13, 14 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.
REFHB (Pins 13, 14): Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also bypass to Pins 11, 12 with an additional 2.2μF ceramic
chip capacitor and to ground with a 1μF ceramic chip
capacitor.
AINB– (Pin 15): Channel B Negative Differential Analog
Input.
AINB+ (Pin 16): Channel B Positive Differential Analog
Input.
GND (Pins 17, 64): ADC Power Ground.
SENSEB (Pin 19): Channel B Reference Programming Pin.
Connecting SENSEB to VCMB selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±VSENSEB. ±1V is the largest valid input range.
VCMB (Pin 20): Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2μF ceramic chip
capacitor. Do not connect to VCMA.
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA11; Channel B
comes out on DB0-DB11. If MUX is Low, the output busses are swapped and Channel A comes out on DB0-DB11;
Channel B comes out on DA0-DA11. To multiplex both
channels onto a single output bus, connect MUX, CLKA
and CLKB together. (This is not recommended at clock
frequencies above 80Msps.)
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal operation
with the outputs at high impedance. Connecting SHDNB
to VDD and OEB to GND results in nap mode with the
outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs
at high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42): Do not connect these pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital
Outputs. DB11 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Drivers.
Bypass to ground with 0.1μF ceramic chip capacitor.
CLKOUT (Pin 40): Data Ready Clock Output. Latch data
on the falling edge of CLKOUT. CLKOUT is derived from
CLKB. Tie CLKA to CLKB for simultaneous operation.
DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital
Outputs. DA11 is the MSB.
OF (Pin 57): Overflow/Underflow Output. High when an
overflow or underflow has occurred on either Channel A
or Channel B.
2283fb
8
LTC2283
PIN FUNCTIONS
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer
on. VDD selects 2’s complement output format and turns
the clock duty cycle stabilizer off.
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal operation
with the outputs at high impedance. Connecting SHDNA
to VDD and OEA to GND results in nap mode with the
outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs
at high impedance.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2μF ceramic chip
capacitor. Do not connect to VCMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to VCMA selects the internal reference
and a ±0.5V input range. VDD selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±VSENSEA. ±1V is the largest valid input range.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
FUNCTIONAL BLOCK DIAGRAM
AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
1.5V
REFERENCE
SIXTH PIPELINED
ADC STAGE
SHIFT REGISTER
AND CORRECTION
2.2μF
RANGE
SELECT
REFH
SENSE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
OF*
D11
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
•
•
•
OUTPUT
DRIVERS
D0
CLKOUT*
REFH
0.1μF
2283 F01
REFL
OGND
CLK
MODE
SHDN
OE
2.2μF
*OF AND CLKOUT ARE SHARED BETWEEN BOTH CHANNELS.
1μF
1μF
Figure 1. Functional Block Diagram (Only One Channel is Shown)
2283fb
9
LTC2283
TIMING DIAGRAMS
Dual Digital Output Bus Timing
(Only One Channel is Shown)
tAP
ANALOG
INPUT
N+4
N+2
N
N+1
tH
N+3
N+5
tL
CLKA = CLKB
tD
N–4
N–5
D0-D11, OF
N–3
N–2
N–1
N
2283 TD01
tC
CLKOUT
Multiplexed Digital Output Bus Timing
tAPA
ANALOG
INPUT A
A+4
A+2
A
A+1
A+3
tAPB
ANALOG
INPUT B
B+4
B+2
B
B+1
tH
tL
A–5
B–5
B+3
CLKA = CLKB = MUX
D0A-D11A
A–4
tD
D0B-D11B
B–5
tC
B–4
A–3
B–3
A–2
B–2
B–3
A–3
B–2
A–2
A–1
tMD
A–5
B–4
A–4
B–1
2283 TD02
CLKOUT
2283fb
10
LTC2283
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding
the input signal and DC. This value is expressed in decibels
relative to the RMS value of a full-scale input signal.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Input Bandwidth
Total Harmonic Distortion
Aperture Delay Time
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
The time from when CLK reaches midsupply to the instant that the input signal is held by the sample and hold
circuit.
THD = 20log (V22 + V32 + V42 + ...Vn2 )/V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
Crosstalk
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
CONVERTER OPERATION
As shown in Figure 1, the LTC2283 is a dual CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
2283fb
11
LTC2283
APPLICATIONS INFORMATION
worse harmonic distortion. The CLK input is single-ended.
The LTC2283 has two phases of operation, determined by
the state of the CLK input pin.
third stage. An identical process is repeated for the third,
fourth and fifth stages, resulting in a fifth stage residue
that is sent to the sixth stage ADC for final evaluation.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Block Diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the
first stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back to
acquiring the analog input. When CLK goes back high, the
second stage produces its residue which is acquired by the
Figure 2 shows an equivalent circuit for the LTC2283 CMOS
differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS
transistors. The capacitors shown attached to each input
(CPARASITIC) are the summation of all other capacitance
associated with each input.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
LTC2283
VDD
AIN+
CSAMPLE
3.5pF
15Ω
CPARASITIC
1pF
VDD
AIN–
CSAMPLE
3.5pF
15Ω
CPARASITIC
1pF
VDD
CLK
2283 F02
Figure 2. Equivalent Input Circuit
2283fb
12
LTC2283
APPLICATIONS INFORMATION
from the input and the held voltage is passed to the ADC
core for processing. As CLK transitions from high to low,
the inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small, the charging glitch seen at the input will
be small. If the input change is large, such as the change
seen with input frequencies near Nyquist, then a larger
charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for the
2V range or ±0.25V for the 1V range, around a common
mode voltage of 1.5V. The VCM output pin may be used
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The VCM pin must be bypassed to ground
close to the ADC with a 2.2μF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the dynamic
performance of the LTC2283 can be influenced by the input
drive circuitry, particularly the second and third harmonics.
Source impedance and reactance can influence SFDR. At
the falling edge of CLK, the sample-and-hold circuit will
connect the 3.5pF sampling capacitor to the input pin and
start the sampling period. The sampling period ends when
CLK rises, holding the sampled input on the sampling
capacitor. Ideally the input circuitry should be fast enough
to fully charge the sampling capacitor during the sampling
period 1/(2FENCODE); however, this is not always possible
and the incomplete settling may degrade the SFDR. The
sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2283 being driven by an RF transformer with a center tapped secondary. The secondary
center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100Ω for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
VCM
2.2μF
0.1μF
ANALOG
INPUT
T1
1:1
25Ω
25Ω
AIN+
LTC2283
0.1μF
12pF
25Ω
AIN–
T1 = MA/COM ETC1-1T 25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2283 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
2283fb
13
LTC2283
APPLICATIONS INFORMATION
VCM
VCM
HIGH SPEED
DIFFERENTIAL
25Ω
AMPLIFIER
ANALOG
INPUT
+
AIN+
0.1μF
LTC2283
12Ω
ANALOG
INPUT
25Ω
+
CM
–
2.2μF
2.2μF
–
25Ω
0.1μF
AIN–
LTC2283
0.1μF
T1
12pF
AIN+
8pF
25Ω
12Ω
AIN–
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2283 F04
2283 F06
Figure 4. Differential Drive with an Amplifier
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
VCM
0.1μF
ANALOG
INPUT
1k
2.2μF
1k
25Ω
AIN+
LTC2283
VCM
2.2μF
12pF
25Ω
0.1μF
0.1μF
AIN+
ANALOG
INPUT
AIN–
25Ω
T1
2283 F05
0.1μF
Figure 5 shows a single-ended input circuit. The impedance
seen by the analog inputs should be matched. This circuit
is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer
gives better high frequency response than a flux coupled
center tapped transformer. The coupling capacitors allow
the analog inputs to be DC biased at 1.5V. In Figure 8, the
series inductors are impedance matching elements that
maximize the ADC bandwidth.
25Ω
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 5. Single-Ended Drive
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
LTC2283
0.1μF
AIN–
2283 F07
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
VCM
2.2μF
0.1μF
8.2nH
ANALOG
INPUT
25Ω
AIN+
LTC2283
0.1μF
T1
0.1μF
25Ω
8.2nH
–
AIN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
2283 F08
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
2283fb
14
LTC2283
APPLICATIONS INFORMATION
Reference Operation
Figure 9 shows the LTC2283 reference circuitry consisting
of a 1.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference
can be configured for two pin selectable input ranges of
2V (±1V differential) or 1V (±0.5V differential). Tying the
SENSE pin to VDD selects the 2V range; tying the SENSE
pin to VCM selects the 1V range.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required
for the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
LTC2283
1.5V
VCM
4Ω
The difference amplifier generates the high and low
reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9. Each
ADC channel has an independent reference with its own
bypass capacitors. The two channels can be used with the
same or different input ranges.
Other voltage ranges between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying its output directly or through a resistor divider to
SENSE. It is not recommended to drive the SENSE pin
with a logic device. The SENSE pin should be tied to the
appropriate level as close to the converter as possible. If
the SENSE pin is driven externally, it should be bypassed
to ground as close to the device as possible with a 1μF
ceramic capacitor. For the best channel matching, connect
an external reference to SENSEA and SENSEB.
1.5V BANDGAP
REFERENCE
1.5V
2.2μF
1V
0.5V
VCM
2.2μF
12k
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
RANGE
DETECT
AND
CONTROL
0.75V
12k
1μF
SENSE
2283 F10
BUFFER
Figure 10. 1.5V Range ADC
INTERNAL ADC
HIGH REFERENCE
1μF
REFH
2.2μF
LTC2283
SENSE
0.1μF
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 4dB. See the Typical Performance
Characteristics section.
DIFF AMP
1μF
REFL
INTERNAL ADC
LOW REFERENCE
2283 F09
Figure 9. Equivalent Reference Circuit
Driving the Clock Input
The CLK inputs can be driven directly with a CMOS or
TTL level signal. A sinusoidal clock can also be used
along with a low jitter squaring circuit before the CLK pin
(Figure 11).
2283fb
15
LTC2283
APPLICATIONS INFORMATION
CLEAN
SUPPLY
4.7μF
SINUSOIDAL
CLOCK
INPUT
FERRITE
BEAD
FERRITE
BEAD
0.1μF
0.1μF
1k
0.1μF
CLEAN
SUPPLY
4.7μF
CLK
LTC2283
CLK
LTC2283
100Ω
50Ω
1k
NC7SVU04
2283 F11
2283 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 11. Sinusoidal Single-Ended CLK Drive
The noise performance of the LTC2283 can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude
as possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time
delay is desired between when the two channels sample
the analog inputs, CLKA and CLKB can be driven by two
different signals. If this delay exceeds 1ns, the performance
of the part may degrade. CLKA and CLKB should not be
driven by asynchronous signals.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use
of a transformer provides no incremental contribution
to phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz will
degrade the SNR compared to the transformer solution.
The nature of the received signals also has a large bearing on how much SNR degradation will be experienced.
For high crest factor signals such as WCDMA or OFDM,
where the nominal power level must be at least 6dB to
8dB below full scale, the use of these translators will have
a lesser impact.
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
ETC1-1T
CLK
LTC2283
5pF-30pF
DIFFERENTIAL
CLOCK
INPUT
2283 F13
0.1μF
FERRITE
BEAD
VCM
Figure 13. LVDS or PECL CLK Drive Using a Transformer
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending
on transmission line length may require a 10Ω to 20Ω
ohm series resistor to act as both a low pass filter for
high frequency noise that may be induced into the clock
line by neighboring digital signals, as well as a damping
mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2283 is 125Msps.
The lower limit of the LTC2283 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
2283fb
16
LTC2283
APPLICATIONS INFORMATION
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2283 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures high
performance even if the input clock has a non 50% duty
cycle. Using the clock duty cycle stabilizer is recommended
for most applications. To use the clock duty cycle stabilizer,
the MODE pin should be connected to 1/3VDD or 2/3VDD
using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and
the internal falling edge is generated by a phase-locked
loop. The input clock duty cycle can vary from 40% to
60% and the clock duty cycle stabilizer will maintain a
constant 50% internal duty cycle. If the clock is turned off
for a long period of time, the duty cycle stabilizer circuit
will require a hundred clock cycles for the PLL to lock
onto the input clock.
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated
from the ADC power and ground. The additional N-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2283 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. For full speed
operation the capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
LTC2283
OVDD
VDD
0.5V
TO 3.6V
VDD
0.1μF
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50% (±5%) duty cycle.
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit. Note that
OF is high when an overflow or underflow has occurred
on either Channel A or Channel B.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D11 – D0
(Offset Binary)
D11 – D0
(2’s Complement)
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
2283 F14
Figure 14. Digital Output Buffer
Data Format
Using the MODE pin, the LTC2283 parallel digital output
can be selected for offset binary or 2’s complement format.
Connecting MODE to GND or 1/3VDD selects offset binary
output format. Connecting MODE to 2/3VDD or VDD selects
2’s complement output format. An external resistor divider
can be used to set the 1/3VDD or 2/3VDD logic values.
Table 2 shows the logic states for the MODE pin.
2283fb
17
LTC2283
APPLICATIONS INFORMATION
Sleep and Nap Modes
Table 2. MODE Pin Function
OUTPUT FORMAT
CLOCK DUTY
CYCLE STABILIZER
0
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
MODE PIN
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged on channel A or channel B.
Note that both channels share a common OF pin, which
is not the case for slower pin compatible parts such as
the LTC2282 or LTC2294. OF is disabled when channel A
is in sleep or nap mode.
Output Clock
The ADC has a delayed version of the CLKB input available
as a digital output, CLKOUT. The falling edge of the CLKOUT
pin can be used to latch the digital output data. CLKOUT
is disabled when channel B is in sleep or nap mode.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OVDD should be tied to that same
1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND
up to 1V and must be less than OVDD. The logic outputs
will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE high disables all data outputs including OF. The
data access and bus relinquish times are too slow to
allow the outputs to be enabled and disabled during full
speed operation. The output Hi-Z state is intended for use
during long periods of inactivity. Channels A and B have
independent output enable pins (OEA, OEB).
The converter may be placed in shutdown or nap modes to
conserve power. Connecting SHDN to GND results in normal
operation. Connecting SHDN to VDD and OE to VDD results
in sleep mode, which powers down all circuitry including
the reference and typically dissipates 1mW. When exiting
sleep mode it will take milliseconds for the output data
to become valid because the reference capacitors have to
recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
30mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that
from sleep mode, typically taking 100 clock cycles. In both
sleep and nap modes, all digital outputs are disabled and
enter the Hi-Z state.
Channels A and B have independent SHDN pins (SHDNA,
SHDNB). Channel A is controlled by SHDNA and OEA,
and channel B is controlled by SHDNB and OEB. The
nap, sleep and output enable modes of the two channels
are completely independent, so it is possible to have one
channel operating while the other channel is in nap or
sleep mode.
Digital Output Multiplexer
The digital outputs of the LTC2283 can be multiplexed onto
a single data bus if the sample rate is 80Msps or less. The
MUX pin is a digital input that swaps the two data busses. If MUX is High, channel A comes out on DA0-DA11;
channel B comes out on DB0-DB11. If MUX is Low, the
output busses are swapped and channel A comes out
on DB0-DB11; channel B comes out on DA0-DA11. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together (see the Timing Diagram
for the multiplexed mode). The multiplexed data is available on either data bus — the unused data bus can be
disabled with its OE pin.
Grounding and Bypassing
The LTC2283 requires a printed circuit board with a clean,
unbroken ground plane. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
2283fb
18
LTC2283
APPLICATIONS INFORMATION
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of
particular importance is the 0.1μF capacitor between REFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2μF capacitor between REFH and REFL can be somewhat further away. The
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC2283 differential inputs should run parallel and
close to each other. The input traces should be as short
as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2283 is transferred
from the die through the bottom-side Exposed Pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the Exposed Pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to
a ground plane of sufficient area.
Clock Sources for Undersampling
Undersampling is especially demanding on the clock
source, and the higher the input frequency, the greater the
sensitivity to clock jitter or phase noise. A clock source that
degrades SNR of a full-scale signal by 1dB at 70MHz will
degrade SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix
or Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable.
You must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If the circuit is sensitive to closein phase noise, the power supply for oscillators and any
buffers must be very stable, or propagation delay variation
with supply will translate into phase noise. Even though
these clock sources may be regarded as digital devices, do
not operate them on a digital supply. If your clock is also
used to drive digital devices such as an FPGA, you should
locate the oscillator, and any clock fan-out devices close to
the ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination at
the driver to prevent high frequency noise from the FPGA
disturbing the substrate of the clock fan-out device. If you
use an FPGA as a programmable divider, you must re-time
the signal using the original oscillator, and the re-timing
flip-flop as well as the oscillator should be close to the
ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3x the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
2283fb
19
C19
0.1μF
5
BITS
10
12
14
10
12
14
+
VCM
4
2
VCMA
C7
0.1μF
Msps
125
125
125
125
125
125
C45
100μF
6.3V
OPT
4
5
5
4
•
E5
PWR
GND
E3
VDD
3V
C52
0.1μF
C40
0.1μF
C6, C31
12pF
12pF
12pF
8pF
8pF
8pF
C34
0.1μF
R24
*
E2
EXT
REF B
VCMB
VDD
OVDD
C53
0.1μF
QDVDD
C41
0.1μF
VDD
VCM
VDD
4
2
C54
0.1μF
U1
LTC2283
E4
GND
C35
0.1μF
C28
2.2μF
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
CLKOUT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
U13
VDD LT1761ES5-BYP
1
5
OUT
IN
3
C51
BYP
1μF
4
ADJ
GND
2
C25
0.1μF
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
C5
0.1μF
C49
0.01μF
OVDD
C37
10μF
6.3V
R41
100k
R40
105k
C50
10μF
6.3V
QDVDD
R25
105k
R25
105k
OVDD
C38
0.01μF
OVDD
U12
VDD LT1761ES5-BYP
1
5
OUT
IN
3
C39
BYP
1μF
4
ADJ
GND
2
INPUT FREQUENCY
1MHz < AIN < 70MHz
1MHz < AIN < 70MHz
1MHz < AIN < 70MHz
70MHz < AIN < 140MHz
70MHz < AIN < 140MHz
70MHz < AIN < 140MHz
C55
0.1μF
C48
0.1μF
EXT REF
5
6
3
1
C2
2.2μF
C27
0.1μF
JP3 SENSEB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AINA+
AINA–
REFHA
REFHA
REFLA
REFLA
VDD
CLKA
CLKB
VDD
REFLB
REFLB
REFHB
REFHB
AINB–
AINB+
C1
0.1μF
VDD
C47
0.1μF
C21
0.1μF
C11
0.1μF
C4
0.1μF
VCMB
8
6
4
2
T1, T2
MABAES0060
MABAES0060
MABAES0060
MABA-007159-000000
MABA-007159-000000
MABA-007159-000000
C31
*
C23 1μF
R22
24.9Ω
GND
1/3VDD
2/3VDD
C20
2.2μF
C18 1μF
R20
24.9Ω
2
7
5
3
VDD
JP1 MODE
1
C10
2.2μF
C9 1μF
R3
1k
R2
1k
R1
1k
C13 1μF
•3
R18
*
R39
1k
VDD
C6
*
1
R23
51Ω
T2
*
VDD
R5, R9, R18, R24
24.9Ω
24.9Ω
24.9Ω
12.4Ω
12.4Ω
12.4Ω
C36
4.7μF
VCMB
C33
0.1μF
C29
0.1μF
R32
OPT
C17
0.1μF
C14
0.1μF
C8
0.1μF
VDD
R9
*
R7
24.9Ω
•3
2
R6
24.9Ω
R5
*
C44
0.1μF
1
R8
51Ω
VDD
•
T1
*
EXT REF
5
6
3
1
C3
0.1μF
J4
R17
ANALOG OPT
INPUT B
4
C15
0.1μF
C12
4.7μF
6.3V
R15 3
1k
U3
NC7SVU04
2
R10
1k
U1
LTC2281IUP
LTC2283IUP
LTC2285IUP
LTC2281IUP
LTC2283IUP
LTC2285IUP
R14
49.9Ω
ASSEMBLY TYPE
DC1098A-A
DC1098A-B
DC1098A-C
DC1098A-D
DC1098A-E
DC1098A-F
*VERSION TABLE
J3
CLOCK
INPUT
VDD
L1
BEAD
J2
ANALOG R4
INPUT A OPT
VCMA
E1
EXT
REF A
VDD
VDD
JP2 SENSEA
VDD
GND
VDD
SENSEA
VCMA
MODE
SHDNA
OEA
OF
DA13
DA12
DA11
DA10
DA9
DA8
OGND
OVDD
GND
VDD
SENSEB
VCMB
MUX
SHDNB
OEB
DB0
DB1
DB2
DB3
DB4
DB5
DB6
OGND
OVDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
20
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
22
10
9
7
8
6
5
3
4
22
10
9
7
8
5
6
4
3
22
10
9
7
8
6
5
3
4
22
10
9
7
8
6
5
3
4
12
QDVDD
13 25
11
12
13 25
GND GND GND GND
4
U4
NC7SV86P5X
U11
1 24 23 FXLH42245MPX
VCCA VCCB VCCB
21
B0
A0
20
B1
A1
19
A2
B2
18
B3
A3
EXPOSED
17
A4
B4
PAD
16
B5
A5
15
B6
A6
14
B7
A7
2
T/R
OE
OVDD
11
GND GND GND GND
QDVDD
13 25
U10
1 24 23 FXLH42245MPX
VCCA VCCB VCCB
21
B0
A0
20
B1
A1
19
A2
B2
18
B3
A3
EXPOSED
17
A4
B4
PAD
16
B5
A5
15
B6
A6
14
B7
A7
2
T/R
OE
12
OVDD
11
QDVDD
13 25
U9
1 24 23 FXLH42245MPX
VCCA VCCB VCCB
21
B0
A0
20
B1
A1
19
A2
B2
18
B3
A3
EXPOSED
17
A4
B4
PAD
16
B5
A5
15
B6
A6
14
B7
A7
2
T/R
OE
GND GND GND GND
12
OVDD
11
QDVDD
OVDD
U2
1 24 23 FXLH42245MPX
R42
VCCA VCCB VCCB
1k
21
B0
A0
20
B1
A1
19
A2
B2
18
B3
A3
EXPOSED
17
A4
B4
PAD
16
B5
A5
15
B6
A6
14
B7
A7
2
T/R
OE
GND GND GND GND
OVDD
Evaluation Circuit Schematic of the LTC2283
3
5
1
2
QDVDD
C24
0.1μF
R35
100k
U5
24LC025
25
27
29
31
30
32
53
54
61
1
A0
2
A1
3
A2
4
A3
C46
0.1μF
R34
4.7k
100
98
94
96
92
84
86
88
90
76
78
80
82
72
74
68
70
8
VCC
7
WP
6
SCL
5
SDA
R36
4.99k
99
97
93
95
91
83
85
87
89
75
77
79
81
71
73
67
69
63
65
59
62
64
66
60
55
57
45
47
49
51
46
48
50
52
56
58
37
39
41
43
38
40
42
44
33
35
23
34
36
21
26
28
17
19
18
20
24
15
16
22
7
9
11
13
1
3
5
J1
EDGE-CON-100
8
10
12
14
2
4
6
ENABLE
SDA
VCCIN
SCL
VSS
R38
4.99k
R37
4.99k
R33 QDVDD
4.7k
2283 AI01
SDA
SCL
VSS
VCCIN
LTC2283
APPLICATIONS INFORMATION
2283fb
LTC2283
APPLICATIONS INFORMATION
Silkscreen Top
Top Side
2283fb
21
LTC2283
APPLICATIONS INFORMATION
Inner Layer 2 GND
Inner Layer 3 Power
Bottom Side
2283fb
22
LTC2283
PACKAGE DESCRIPTION
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705)
0.70 ±0.05
7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
7.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9 .00 ± 0.10
(4 SIDES)
0.75 ± 0.05
R = 0.10
TYP
R = 0.115
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 ± 0.10
7.50 REF
(4-SIDES)
7.15 ± 0.10
(UP64) QFN 0406 REV C
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
2283fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2283
TYPICAL APPLICATION
PART NUMBER
DESCRIPTION
COMMENTS
LTC1748
14-Bit, 80Msps, 5V ADC
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1750
14-Bit, 80Msps, 5V Wideband ADC
Up to 500MHz IF Undersampling, 90dB SFDR
LTC1993-2
High Speed Differential Op Amp
800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC1994
Low Noise, Low Distortion Fully Differential Input/Output
Amplifier/Driver
Low Distortion: –94dB at 1MHz
LTC2208
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
1250mW, 77.1dB SNR, 100dB SFDR, 64-Pin QFN Package
LTC2220
12-Bit, 170Msps, 3.3V ADC, LVDS Outputs
890mW, 67.7dB SNR, 84dB SFDR, 64-Pin QFN Package
LTC2224
12-Bit, 135Msps, 3.3V ADC, High IF Sampling
630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN Package
LTC2242-12
12-Bit, 250Msps, 2.5V ADC, LVDS Outputs
740mW, 65.4dB SNR, 84dB SFDR, 64-Pin QFN Package
LTC2254
14-Bit, 105Msps, 3V ADC, Lowest Power
320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN Package
LTC2255
14-Bit, 125Msps ADC, 3V ADC, Lowest Power
395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN Package
LTC2280
10-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
320mW, 61.6dB SNR, 85dB SFDR, 64-Pin QFN Package
LTC2282
12-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
540mW, 70.1dB SNR, 88dB SFDR, 64-Pin QFN Package
LTC2284
14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk
540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN Package
LTC2286
10-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk
150mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package
LTC2287
10-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk
235mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package
LTC2288
10-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk
400mW, 61.8dB SNR, 85dB SFDR, 64-Pin QFN Package
LTC2289
10-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk
422mW, 61.6dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2290
12-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk
120mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2291
12-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk
150mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2292
12-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk
235mW, 71.4dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2293
12-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk
400mW, 71.3dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2294
12-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk
422mW, 70.6dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2295
14-Bit, Dual, 10Msps, 3V ADC, Low Crosstalk
120mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2296
14-Bit, Dual, 25Msps, 3V ADC, Low Crosstalk
150mW, 74.5dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2297
14-Bit, Dual, 40Msps, 3V ADC, Low Crosstalk
235mW, 74.4dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2298
14-Bit, Dual, 65Msps, 3V ADC, Low Crosstalk
400mW, 74.3dB SNR, 90dB SFDR, 64-Pin QFN Package
LTC2299
14-Bit, Dual, 80Msps, 3V ADC, Low Crosstalk
444mW, 73dB SNR, 90dB SFDR, 64-Pin QFN Package
LT5512
DC-3GHz High Signal Level Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
450MHz to 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
LT5515
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator
High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator
LT5516
800MHz to 1.5GHz Direct Conversion Quadrature Demodulator
High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator
LT5517
40MHz to 900MHz Direct Conversion Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5522
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single Ended RF and LO Ports
2283fb
24 Linear Technology Corporation
LT 1207 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006