LINER LTC1147-3.3 High efficiency step-down switching regulator controller Datasheet

LTC1147-3.3
LTC1147-5/LTC1147L
High Efficiency Step-Down
Switching Regulator Controllers
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DESCRIPTIO
FEATURES
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Very High Efficiency: Over 95% Possible
Wide VIN Range: 3.5V* to 16V
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained Over Three Decades of
Output Current
Low 160µA Standby Current at Light Loads
Logic Controlled Micropower Shutdown: IQ < 20µA
Short-Circuit Protection
Very Low Dropout Operation: 100% Duty Cycle
High Efficiency in a Small Amount of Board Space
Output Can Be Externally Held High in Shutdown
Available in 8-Pin SO Package
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APPLICATIO S
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The LTC®1147 series are step-down switching regulator
controllers featuring automatic Burst ModeTM operation to
maintain high efficiencies at low output currents. These
devices drive an external P-channel power MOSFET at
switching frequencies exceeding 400kHz using a constant
off-time current mode architecture providing constant
ripple current in the inductor.
The operating current level is user-programmable via an
external current sense resistor. Wide input supply range
allows operation from 3.5V* to 14V (16V maximum).
Constant off-time architecture provides low dropout regulation limited by only the RDS(ON) of the external MOSFET
and resistance of the inductor and current sense resistor.
The LTC1147 series incorporates automatic power saving
Burst Mode operation to reduce switching losses when
load currents drop below the level required for continuous
operation. Standby power is reduced to only 2mW at
VIN = 10V (at IOUT = 0). Load currents in Burst Mode
operation are typically 0mA to 300mA.
Notebook and Palmtop Computers
Portable Instruments
Battery-Operated Digital Devices
Cellular Telephones
DC Power Distribution Systems
GPS Systems
For applications where even higher efficiency is required,
refer to the LTC1148 data sheet and Application Note 54.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
*LTC1147L and LTC1147L-3.3 only.
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TYPICAL APPLICATI
LTC1147-5 Efficiency
VIN (5.2V TO 14V)
+
1µF
VIN
PDRIVE
LTC1147-5
SHDN
SENSE +
ITH
SENSE –
CT
0V = NORMAL
>1.5V = SHUTDOWN
RC
1k
CC
3300pF
CT
470pF
GND
P-CHANNEL
Si4431DY
L*
50µH
CIN
100µF
RSENSE**
0.05Ω
95
VOUT
5V/2A
1000pF
+
D1
MBRD330
COUT
390µF
EFFICIENCY (%)
+
100
VIN = 6V
90
VIN = 10V
85
80
75
LT1147 • F01
*COILTRONICS CTX50-2-MP
**KRL SL-1-C1-0R050J
70
0.001
0.01
0.1
1
LOAD CURRENT (A)
LT1147 • TA01
Figure 1. High Efficiency Step-Down Converter
sn1147 1147fds
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LTC1147-3.3
LTC1147-5/LTC1147L
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ABSOLUTE
AXI U RATI GS
Input Supply Voltage (Pin 1) .................... 16V to – 0.3V
Continuous Output Current (Pin 8) ...................... 50mA
Sense Voltages (Pins 4, 5)
VIN ≥ 12.7V ...........................................13V to – 0.3V
VIN < 12.7V ............................... (VIN + 0.3V) to – 0.3V
Operating Ambient Temperature Range
LTC1147C ............................................... 0°C to 70°C
LTC1147I ............................................. –40°C to 85°C
Extended Commercial
Temperature Range (Note 4) ................. – 40°C to 85°C
Junction Temperature (Note 1) ............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART NUMBER
TOP VIEW
VIN 1
8
PDRIVE
CT 2
7
ITH 3
6
SENSE – 4
5
GND
SHDN
(VFB*)
SENSE +
N8 PACKAGE
S8 PACKAGE
8-LEAD PLASTIC DIP 8-LEAD PLASTIC SO
* ADJUSTABLE OUTPUT VERSION
LTC1147CN8-3.3
LTC1147CN8-5
LTC1147CS8-3.3
LTC1147CS8-5
LTC1147IS8-3.3
S8 PART MARKING
LTC1147IS8-5
LTC1147LCS8
LTC1147LCS8-3.3
LTC1147LIS8
11473
11475
1147I3
1147I5
1147L
1147L3
1147LI
TJMAX = 125°C, θJA = 110°C/W (N)
TJMAX = 125°C, θJA = 150°C/W (S)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
TA = 25°C, VIN = 10V, VSHDN = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V6
Feedback Voltage (LTC1147L)
VIN = 9V
I6
Feedback Current (LTC1147L)
VOUT
Regulated Output Voltage
LTC1147-3.3, LTC1147L-3.3
LTC1147-5
VIN = 9V
ILOAD = 700mA
ILOAD = 700mA
Output Voltage Line Regulation
VIN = 7V to 12V, ILOAD = 50mA
Output Voltage Load Regulation
LTC1147-3.3, LTC1147L-3.3
LTC1147-5
5mA < ILOAD < 2A
5mA < ILOAD < 2A
∆VOUT
IQ
●
MIN
TYP
MAX
UNITS
1.21
1.25
1.29
V
0.2
1
µA
3.23
4.90
3.33
5.05
3.43
5.20
V
V
– 40
0
40
mV
40
60
65
100
mV
mV
●
Burst Mode Output Ripple
ILOAD = 0A
Input DC Supply Current (Note 2)
LTC1147 Series
Normal Mode
Sleep Mode
Sleep Mode (LTC1147-5)
Shutdown
LTC1147L Series
Normal Mode
Sleep Mode
Shutdown (LTC1147L-3.3)
(Note 5)
●
●
●
●
50
mVP-P
4V < VIN < 12V
4V < VIN < 12V
5V < VIN < 12V
VSHDN = 2.1V, 4V < VIN < 12V
1.6
160
160
10
2.1
230
230
20
mA
µA
µA
µA
3.5V < VIN < 12V
3.5V < VIN < 12V
VSHDN = 2.1V, 3.5V < VIN < 12V
1.6
160
10
2.1
230
20
mA
µA
µA
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LTC1147-3.3
LTC1147-5/LTC1147L
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
V5 – V 4
Current Sense Threshold Voltage (Note 6)
LTC1147-3.3, LTC1147L-3.3
LTC1147–5
LTC1147L
V6
SHDN Pin Threshold
LTC1147-3.3/LTC1147-5/LTC1147L-3.3
I6
SHDN Pin Input Current
LTC1147-3.3/LTC1147-5/LTC1147L-3.3
TA = 25°C, VIN = 10V, VSHDN = 0V, unless otherwise noted.
CONDITIONS
MIN
VSENSE– = VOUT + 100mV (Forced)
VSENSE– = VOUT – 100mV (Forced)
VSENSE– = VOUT + 100mV (Forced)
VSENSE– = VOUT – 100mV (Forced)
VSENSE– = 5V, V6 = VOUT/4 + 25mV (Forced)
VSENSE– = 5V, V6 = VOUT/4 – 25mV (Forced)
I2
CT Pin Discharge Current
VOUT in Regulation, VSENSE
VOUT = 0V
tOFF
Off-Time (Note 3)
CT = 390pF, ILOAD = 700mA
tr, tf
Driver Output Transition Times
CL = 3000pF (Pin 8), VIN = 6V
UNITS
130
0.5
0.8
2
V
1.2
5
µA
70
2
90
10
µA
µA
130
50
OUT
MAX
25
150
25
150
25
150
130
0V < VSHDN < 8V, VIN = 16V
–=V
TYP
4
170
170
170
mV
mV
mV
mV
mV
mV
5
6
µs
100
200
ns
– 40°C ≤ TA ≤ 85°C (Note 4), VIN = 10V, unless otherwise noted.
SYMBOL
PARAMETER
V6
Feedback Voltage (LTC1147L)
VIN = 9V
VOUT
Regulated Output Voltage
LTC1147-3.3/LTC1147L-3.3
LTC1147-5
VIN = 9V
ILOAD = 700mA
ILOAD = 700mA
Input DC Supply Current (Note 2)
LTC1147 Series
Normal Mode
Sleep Mode
Sleep Mode (LTC1147-5)
Shutdown
LTC1147L Series
Normal Mode
Sleep Mode
Shutdown (LTC1147L-3.3)
(Note 5)
IQ
V 5 – V4
Current Sense Threshold Voltage (Note 6)
LTC1147-3.3
LTC1147-5
LTC1147L
V6
tOFF
CONDITIONS
MIN
TYP
MAX
UNITS
●
1.20
1.25
1.30
V
●
●
3.17
4.85
3.33
5.05
3.43
5.20
V
V
4V < VIN < 12V
4V < VIN < 12V
5V < VIN < 12V
VSHDN = 2.1V, 4V < VIN < 12V
1.6
160
160
10
2.4
260
260
22
mA
µA
µA
µA
3.5V < VIN < 12V
3.5V < VIN < 12V
VSHDN = 2.1V, 3.5V < VIN < 12V
1.6
160
10
2.4
260
22
mA
µA
µA
VSENSE – = VOUT + 100mV (Forced)
VSENSE – = VOUT – 100mV (Forced)
VSENSE – = VOUT + 100mV (Forced)
VSENSE – = VOUT – 100mV (Forced)
VSENSE– = 5V, 6V = VOUT/4 + 25mV (Forced)
VSENSE– = 5V, 6V = VOUT/4 – 25mV (Forced)
125
25
150
25
150
25
150
●
125
●
125
185
185
185
mV
mV
mV
mV
mV
mV
SHDN Pin Threshold
LTC1147-3.3/LTC1147-5/LTC1147L-3.3
0V < VSHDN < 8V, VIN = 16V
0.5
0.8
2
V
Off-Time (Note 3)
CT = 390pF, ILOAD = 700mA
3.8
5
6.5
µs
The ● denotes specifications which apply over the full specified
temperature range.
Note 1: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC1147CN8-3.3/LTC1147CN8-5: TJ = TA + (PD)(110°C/W)
LTC1147LIS/LTC1147IS8/LTC1147LCS/
LTC1147CS8-3.3/LTC1147CS8-5: TJ = TA + (PD)(150°C/W)
Note 2: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 3: In applications where RSENSE is placed at ground potential, the offtime increases approximately 40%.
Note 4: The LTC1147C is guaranteed to meet specified performance from
0°C to 70°C and is designed, characterized and expected to meet these
extended temperature limits, but is not tested at – 40°C and 85°C. The
LTC1147I is guaranteed to meet the extended temperature limits.
Note 5: The LTC1147L/LTC1147L-3.3 allow operation to VIN = 3.5V.
Note 6: The LTC1147L is tested with external feedback resistors resulting
in a nominal output voltage of 2.5V.
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LTC1147-3.3
LTC1147-5/LTC1147L
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
Line Regulation
100
FIGURE 1 CIRCUIT
98
Load Regulation
40
20
FIGURE 1 CIRCUIT
ILOAD = 1A
30
20
ILOAD = 1A
92
90
88
ILOAD = 100mA
86
–20
10
∆VOUT (mV)
94
∆VOUT (mV)
EFFICIENCY (%)
96
0
–10
–40
VIN = 12V
–60
–80
–30
82
80
–40
4
0
16
12
8
INPUT VOLTAGE (V)
–100
0
8
4
12
20
1.6
VSHUTDOWN = 2V
(NOT AVAILABLE ON LTC1147L)
18
VOUT = 5V
1.4
1.2
0.9
0.6
NORMALIZED FREQUENCY
SUPPLY CURRENT (µA)
ACTIVE MODE
14
12
10
8
6
4
0.3
SLEEP MODE
0
0
2
4
8 10 12 14
6
INPUT VOLTAGE (V)
16
0
18
2
4
6
8 10 12 14
INPUT VOLTAGE (V)
Gate Charge Supply Current
10
60
4
16
2
260
80
200
140
OPERATING FREQUENCY (kHz)
LTC1147 • G07
2
4
10
8
6
(VIN – VOUT) VOLTAGE (V)
Current Sense Threshold Voltage
MAXIMUM
THRESHOLD
150
50
40
30
0
1
2
125
100
75
50
MINIMUM
THRESHOLD
25
LTC1147-5
0
12
175
LTC1147-3.3
20
0
LTC1148 • G06
VSENSE – = VOUT
10
0
0.4
0
20
QP = 29nC
0.6
18
SENSE VOLTAGE (mV)
12
70
OFF-TIME (µs)
80
6
25°C
0.8
Off-Time vs VOUT
14
QP = 50nC
70°C
1.0
LTC1147 • G05
LTC1147 • G04
8
0°C
1.2
0.2
2
0
2.5
2.0
Operating Frequency
vs (VIN – VOUT)
16
1.5
1.0
1.5
LOAD CURRENT (A)
LTC1147 • G03
Supply Current in Shutdown
NOT INCLUDING
GATE CHARGE CURRENT
1.8
0.5
LTC1147 • G02
DC Supply Current
2.1
0
16
INPUT VOLTAGE (V)
LTC1147 • G01
SUPPLY CURRENT (mA)
VIN = 6V
–20
84
GATE CHARGE CURRENT (mA)
FIGURE 1 CIRCUIT
RSENSE = 0.05Ω
0
0
3
4
5
OUTPUT VOLTAGE (V)
LTC1147 • G08
0
20
60
40
TEMPERATURE (°C)
80
100
LTC1147 • G09
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LTC1147-3.3
LTC1147-5/LTC1147L
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PI FU CTIO S
VIN (Pin 1): Main Supply Pin. Must be closely decoupled
to ground Pin 7.
CT (Pin 2): External capacitor CT from Pin 2 to ground sets
the operating frequency. The actual frequency is also
dependent upon the input voltage.
ITH (Pin 3): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 3 voltage.
SENSE – (Pin 4): Connects to internal resistive divider
which sets the output voltage. Pin 4 is also the (–) input for
the current comparator.
SENSE + (Pin 5): The (+) input to the current comparator.
A built-in offset between Pins 4 and 5 in conjunction with
RSENSE sets the current trip threshold.
SHDN/VFB (Pin 6): When grounded, the fixed output
versions of the LTC1147 family operate normally. Pulling
Pin 6 high holds the P-channel MOSFET off and puts the
LTC1147 in micropower shutdown mode. Requires CMOS
logic signal with tr, tf < 1µs. Do not leave this pin floating.
On the LTC1147L this pin serves as the feedback pin from
an external resistive divider used to set the output voltage.
GND (Pin 7): Two independent ground lines must be
routed separately to: 1) the (–) terminal of COUT, and 2) the
cathode of the Schottky diode and (–) terminal of CIN.
PDRIVE (Pin 8): High current drive for the P-channel
MOSFET. Voltage swing at this pin is from VIN to ground.
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FU CTIO AL DIAGRA Pin 6 Connection Shown For LTC1147-3.3 and LTC1147-5; Changes Create LTC1147L.
1 VIN
SENSE+
SENSE –
5
4
VFB
8 PDRIVE
6
7 GND
–
V
+
SLEEP
–
R
S
+
+
VTH2
VTH1
+
5pF
VOS
–
+
13k
T
ITH 3
G
+
–
–
–
S
25mV TO 150mV
C
Q
1.25V
100k
2
CT
OFF-TIME
CONTROL
VIN
SENSE –
SHDN 6
REFERENCE
LTC1147 • FD
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LTC1147-3.3
LTC1147-5/LTC1147L
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OPERATIO (Refer to Functional Diagram)
The LTC1147 series uses a current mode, constant offtime architecture to switch an external P-channel power
MOSFET. Operating frequency is set by an external capacitor at CT (Pin 2).
The output voltage is sensed by an internal voltage divider
connected to SENSE– (Pin 4). A voltage comparator V, and
a gain block G, compare the divided output voltage with a
reference voltage of 1.25V. To optimize efficiency, the
LTC1147 series automatically switchs between two modes
of operation, burst and continuous. The voltage comparator is the primary control element when the device is in
Burst Mode operation, while the gain block controls the
output voltage in continuous mode.
During the switch “on” cycle in continuous mode, current
comparator C monitors the voltage between Pins 4 and 5
connected across an external shunt in series with the
inductor. When the voltage across the shunt reaches its
threshold value, the PDRIVE output is switched to VIN,
turning off the P-channel MOSFET. The timing capacitor
connected to Pin 2 is now allowed to discharge at a rate
determined by the off-time controller. The discharge current is made proportional to the output voltage (measured
by Pin 4) to model the inductor current, which decays at
a rate which is also proportional to the output voltage.
When the voltage on the timing capacitor has discharged
past VTH1, comparator T trips, setting the flip-flop. This
causes the PDRIVE output to go low turning the P-channel
MOSFET back on. The cycle then repeats.
As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage
(Pin 3) to increase the current comparator threshold, thus
tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel MOSFET is held off by comparator V and the timing capacitor
continues to discharge below VTH1. When the timing
capacitor discharges past VTH2, voltage comparator S
trips, causing the internal sleep line to go low.
The circuit now enters sleep mode with the power MOSFET turned off. In sleep mode, a majority of the circuitry is
turned off, dropping the quiescent current from 1.6mA to
160µA. The load current is now being supplied from the
output capacitor. When the output voltage has dropped by
the amount of hysteresis in comparator V, the P-channel
MOSFET is again turned on and this process repeats.
To avoid the operation of the current loop interfering with
Burst Mode operation, a built-in offset VOS is incorporated
in the gain stage. This prevents the current comparator
threshold from increasing until the output voltage has
dropped below a minimum threshold.
Using constant off-time architecture, the operating frequency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the discharge current as VIN drops
below VOUT + 1.5V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle), providing low
dropout operation with VOUT ≈ VIN.
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APPLICATIO S I FOR ATIO
LTC1147L Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1147L adjustable version is used with an external
resistive divider from VOUT to VFB (Pin 6) (see Figure 7).
The regulated voltage is determined by:
)
VOUT = 1.25 1 +
R2
R1
)
To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1147L.
For Figure 1 applications with VOUT below 2V, or when
RSENSE is moved to ground, the current sense comparator
inputs operate near ground. When the current comparator
is operated at less than 2V common mode, the off-time
increases approximately 40%, requiring the use of a
smaller timing capacitor CT.
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LTC1147-3.3
LTC1147-5/LTC1147L
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APPLICATIO S I FOR ATIO
The basic LTC1147 application circuit is shown in Figure
1. External component selection is driven by the load
requirement and begins with the selection of RSENSE. Once
RSENSE is known, CT and L can be chosen. Next, the power
MOSFET and D1 are selected. Finally, CIN and COUT are
selected and the loop is compensated. The circuit shown
in Figure 1 can be configured for operation up to an input
voltage of 16V. If the application requires higher input
voltage, then the synchronous switched LTC1149 should
be used. Consult factory for lower minimum input voltage
version.
0.20
RSENSE (Ω)
0.15
0.05
0
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for
Operating Frequency). Solving for RSENSE and allowing
a margin for variations in the LTC1147 series and
external component values yields:
RSENSE = 100mV
IMAX
A graph for selecting RSENSE versus maximum output
current is given in Figure 2.
The load current below in which Burst Mode operation
commences, IBURST and the peak short-circuit current
ISC(PK), both track IMAX. Once RSENSE has been chosen,
IBURST and ISC(PK) can be predicted from the following:
IBURST ≈ 15mV
RSENSE
ISC(PK) = 150mV
RSENSE
0
1
3
4
2
MAXIMUM OUTPUT CURRENT (A)
5
LTC1147 • F02
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current.
The LTC1147 series current comparator has a threshold range which extends from a minimum of 25mV/
RSENSE to a maximum of 150mV/RSENSE. The current
comparator threshold sets the peak of the inductor
ripple current, yielding a maximum output current IMAX
equal to the peak value less half the peak-to-peak ripple
current. For proper Burst Mode operation, IRIPPLE(P-P)
must be less than or equal to the minimum current
comparator threshold.
0.10
Figure 2. Selecting RSENSE
The LTC1147 series automatically extend tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
ripple current causes the average short-circuit current
ISC(AVG) to be reduced to approximately IMAX.
L and CT Selection for Operating Frequency
The LTC1147 series use a constant off-time architecture
with tOFF determined by an external timing capacitor CT.
Each time the P-channel MOSFET switch turns on, the
voltage on CT is reset to approximately 3.3V. During the
off-time, CT is discharged by a current which is proportional to VOUT. The voltage on CT is analogous to the
current in inductor L, which likewise decays at a rate
proportional to VOUT. Thus the inductor value must track
the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency:
CT =
)
)
VIN – VOUT
1
(1.3)(104)(f) VIN + VD
Where VD is the drop across the Schottky diode.
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
As the operating frequency is increased the gate charge
losses will reduce efficiency (see Efficiency Considerations). The complete expression for operating frequency
sn1147 1147fds
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LTC1147-3.3
LTC1147-5/LTC1147L
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APPLICATIO S I FOR ATIO
1000
VSENSE – = VOUT = 5V
CAPACITANCE (pF)
800
Inductor Core Selection
600
400
VIN = 12V
200
VIN = 7V
VIN = 10V
0
0
200
100
FREQUENCY (kHz)
300
LTC1147 • F03
Figure 3. Timing Capacitor Value
is given by:
f≈
1
tOFF
series will delay entering Burst Mode operation and efficiency will be degraded at low currents.
)
1–
VOUT
VIN
)
where:
) )
V
tOFF = (1.3)(104)(CT) REG
VOUT
VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT is
the measured output voltage. Thus VREG/VOUT = 1 in
regulation.
Note that as VIN decreases, the frequency decreases.
When the input to output voltage differential drops
below 1.5V, the LTC1147 reduces tOFF by increasing the
discharge current in CT. This prevents audible operation prior to dropout.
Once the frequency has been set by CT, the inductor L
must be chosen to provide no more than 25mV/RSENSE
of peak-to-peak inductor ripple current. This results in
a minimum required inductor value of:
LMIN = (5.1)(105)(RSENSE)(CT)(VREG)
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor
are eased at the expense of efficiency. If too small an
inductor is used, the inductor current will become
discontinuous before the LTC1147 series enters Burst
Mode operation. A consequence of this is that the LTC1147
Once the minimum value for L is known, the type of
inductor must be selected. Highest efficiency will be
obtained using ferrite, Kool Mµ® (from Magnetics, Inc.) or
molypermalloy (MPP) cores. Lower cost powdered iron
cores provide suitable performance but cut efficiency by
3% to 5%. Actual core loss is independent of core size for
a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode operation to be
falsely triggered in the LTC1147. Do not allow the core
to saturate!
Kool Mµ is a very good, low loss core material for toroids
with a “soft” saturation characteristic. Molypermalloy is
slightly more efficient at high (>200kHz) switching frequencies but quite a bit more expensive. Toroids are very
space efficient, especially when you can use several
layers of wire. Because they generally lack a bobbin,
mounting is more difficult. However, new designs for
surface mount are available from Coiltronics, Sumida and
Beckman Industrial Corp. which do not increase the
height significantly.
Power MOSFET Selection
An external P-channel power MOSFET must be selected
for use with the LTC1147 series. The main selection
criteria for the power MOSFET are the threshold voltage
VGS(TH) and “on” resistance RDS(ON).
The minimum input voltage determines whether a standard threshold or logic-level threshold MOSFET must be
Kool Mµ is a registered trademark of Magnetics, Inc.
sn1147 1147fds
8
LTC1147-3.3
LTC1147-5/LTC1147L
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APPLICATIO S I FOR ATIO
used. For VIN > 8V, a standard threshold MOSFET (VGS(TH)
< 4V) may be used. If VIN is expected to drop below 8V,
a logic-level threshold MOSFET (VGS(TH) < 2.5V) is
strongly recommended. When a logic-level MOSFET is
used, the LTC1147 supply voltage must be less than the
absolute maximum VGS ratings for the MOSFET.
The maximum output current IMAX determines the RDS(ON)
requirement for the power MOSFET. When the LTC1147
series is operating in continuous mode, the simplifying
assumption can be made that either the MOSFET or
Schottky diode is always conducting the average load
current. The duty cycles for the MOSFET and diode are
given by:
V
P-Ch Duty Cycle = OUT
VIN
(V – VOUT + VD)
Schottky Diode Duty Cycle = IN
VIN
From the duty cycle the required RDS(ON) for the MOSFET
can be derived:
P-Ch RDS(ON) =
(VIN)(PP)
(VOUT)(IMAX2)(1 + δP)
where PP is the allowable power dissipation and δP is the
temperature dependency of RDS(ON). PP will be determined by efficiency and/or thermal requirements (see
Efficiency Considerations). (1 + δ) is generally given for a
MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.007/°C can be used as an approximation for low voltage MOSFETs.
Output Diode Selection (D1)
The Schottky diode D1 shown in Figure 1 only conducts
during the off-time. It is important to adequately specify
the diode peak current and average power dissipation so
as not to exceed the diode ratings.
The most stressful condition for the output diode is under
short circuit (VOUT = 0V). Under this condition the diode
must safely handle ISC(PK) at close to 100% duty cycle.
Under normal load conditions the average current conducted by the diode is:
ID1 =
(VIN – VOUT + VD)
(ILOAD)
VIN
Remember to keep lead lengths short and observe proper
grounding (see Board Layout Checklist) to avoid ringing
and increased dissipation.
The forward voltage drop allowable in the diode is calculated from the maximum short-circuit current as:
VF ≈
PD
ISC(PK)
where PD is the allowable power dissipation and will be
determined by efficiency and/or thermal requirements
(see Efficiency Considerations).
CIN and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈ IMAX
[VOUT(VIN – VOUT)]1/2
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor
manufacturer’s ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor, or to choose a capacitor rated at a
higher temperature than required. Several capacitors
may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if
there is any question. An additional 0.1µF to 1µF ceramic
decoupling capacitor is also required on VIN (Pin 1) for
high frequency decoupling.
The selection of COUT is driven by the required effective
series resistance (ESR). The ESR of COUT must be less
than twice the value of RSENSE for proper operation of the
LTC1147:
COUT Required ESR < 2RSENSE
sn1147 1147fds
9
LTC1147-3.3
LTC1147-5/LTC1147L
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APPLICATIO S I FOR ATIO
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RSENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RSENSE, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
from Sanyo has the lowest ESR/size ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for COUT has been met, the RMS current
rating generally far exceeds the IRIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice
is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For
example, if 200µF/10V is called for in an application
requiring 3mm height, two AVX 100µF/10V (P/N TPSD
107K010) could be used. Consult the manufacturer for
other specific recommendations.
At low supply voltages, a minimum capacitance at COUT is
needed to prevent an abnormal low frequency operating
1000
L = 50µH
RSENSE = 0.02Ω
COUT (µF)
800
L = 25µH
RSENSE = 0.02Ω
600
200
L = 50µH
RSENSE = 0.05Ω
0
1
3
4
2
(VIN – VOUT) VOLTAGE (V)
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD(ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to
charge or discharge COUT until the regulator loop adapts
to the current change and returns VOUT to its steady
state value. During this recovery time VOUT can be
monitored for overshoot or ringing which would indicate a stability problem. The external components shown
in the Figure 1 circuit will prove adequate compensation
for most applications.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive so
that the load rise time is limited to approximately
(25)CLOAD. Thus a 10µF capacitor would require a 250µs
rise time, limiting the charging current to about 200mA.
Efficiency Considerations
400
0
mode (see Figure 4). When COUT is made too small, the
output ripple at low frequencies will be large enough to trip
the voltage comparator. This causes Burst Mode operation to be activated when the LTC1147 series would
normally be in continuous operation. The effect is most
pronounced with low values of RSENSE and can be improved by operating at higher frequencies with lower
values of L. The output remains in regulation at all times.
5
LTC1147 • F04
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
Figure 4. Minimum Value of COUT
sn1147 1147fds
10
LTC1147-3.3
LTC1147-5/LTC1147L
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APPLICATIO S I FOR ATIO
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1147 circuits: 1) LTC1147 DC bias current,
2) MOSFET gate charge current, 3) I2R losses, and 4)
voltage drop of the Schottky diode.
1. The DC supply current is the current which flows into
VIN (Pin 1) less the gate charge current. For VIN = 10V
the LTC1147 series DC supply current is 160µA for no
load, and increases proportionally with load up to a
constant 1.6mA after the LTC1147 series has entered
continuous mode. Because the DC bias current is
drawn from VIN, the resulting loss increases with
input voltage. For VIN = 10V the DC bias losses are
generally less than 1% for load currents over 30mA.
However, at very low load currents the DC bias current
accounts for nearly all of the loss.
2. MOSFET gate charge current results from switching
the gate capacitance of the power MOSFET. Each time
a MOSFET gate is switched from low to high to low
again, a packet of charge dQ moves from VIN to
ground. The resulting dQ/dt is a current out of VIN
which is typically much larger than the DC supply
current. In continuous mode, IGATECHG = f(QP). The
typical gate charge for a 0.135Ω P-channel power
MOSFET is 40nC. This results in IGATECHG = 4mA in
100kHz continuous operation for a 2% to 3% typical
midcurrent loss with VIN = 10V.
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it argues against using a larger MOSFET than necessary to
control I2R losses, since overkill can cost efficiency as
well as money!
3. I2R losses are easily predicted from the DC resistances of the MOSFET, inductor and current shunt. In
continuous mode the average output current flows
through L and RSENSE, but is “chopped” between the
P-channel and Schottky diode. The MOSFET RDS(ON)
multiplied by the P-channel duty cycle can be summed
with the resistances of L and RSENSE to obtain I2R
losses. For example, if RDS(ON) = 0.1Ω, RL = 0.15Ω,
and RSENSE = 0.05Ω, then the total resistance is 0.3Ω
at VIN ≈ 2VOUT. This results in losses ranging from 3%
to 10% as the output current increases from 0.5A to
2A. I2R losses cause the efficiency to roll off at high
output currents.
4. The Schottky diode is a major source of power loss at
high currents and gets worse at high input voltages.
The diode loss is calculated by multiplying the forward
voltage drop times the Schottky diode duty cycle
multiplied by the load current. For example, assuming
a duty cycle of 50% with a Schottky diode forward
voltage drop of 0.4V, the loss increases from 0.5% to
8% as the load current increases from 0.5A to 2A.
Figure 5 shows how the efficiency losses in a typical
LTC1147 series regulator end up being apportioned.
The gate charge loss is responsible for the majority of
the efficiency lost in the midcurrent region. If Burst
Mode operation was not employed at low currents,
the gate charge loss alone would cause efficiency to
drop to unacceptable levels. With Burst Mode operation, the DC supply current represents the lone (and
unavoidable) loss component which continues to
become a higher percentage as output current is
reduced. As expected, the I2R losses and Schottky
diode loss dominate at high load currents.
100
I2R
GATE CHARGE
EFFICIENCY/LOSS (%)
where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
95
LTC1147 IQ
SCHOTTKY
DIODE
90
85
80
0.01
0.03
0.3
1
0.1
OUTPUT CURRENT (A)
3
LTC1147 • F05
Figure 5. Efficiency Loss
sn1147 1147fds
11
LTC1147-3.3
LTC1147-5/LTC1147L
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APPLICATIO S I FOR ATIO
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses, and inductor core losses,
generally account for less than 2% total additional loss.
fMIN =
Design Example
PP =
As a design example, assume VIN = 5V (nominal), VOUT =
3.3V, IMAX = 1A, and f = 130kHz; RSENSE, CT and L can
immediately be calculated:
RSENSE = 100mV/1A = 0.1Ω
tOFF = (1/130kHz)[1 – (3.3/5)] = 2.61µs
CT = 2.61µs/(1.3)(104) = 220pF
L = (5.1)(105)(0.1Ω)(220pF)(3.3V) = 33µH
Assume that the MOSFET dissipation is to be limited to
PP = 250mW.
If TA = 50°C and the thermal resistance of the MOSFET is
50°C/ W, then the junction temperatures will be 63°C and
δP = 0.007(63 – 25) = 0.27. The required RDS(ON) for the
MOSFET can now be calculated:
P-Ch RDS(ON) =
5(0.25)
= 0.3Ω
3.3(1)2 (1.27)
The P-channel requirement can be met by a Si9430DY.
Note that the most stringent requirement for the Schottky
diode is with VOUT = 0 (i.e., short circuit). During a
continuous short circuit, the worst-case Schottky diode
dissipation rises to:
)
)
1
3.3
= 102kHz
1–
2.61µs
4.5
3.3(0.125Ω)(1A)2(1.27)
= 116mW
4.5
This last step is necessary to assure that the power
dissipation and junction temperature of the P-channel are
not exceeded.
Troubleshooting Hints
Since efficiency is critical to LTC1147 series applications,
it is very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the timing
capacitor Pin 2.
In continuous mode (ILOAD > IBURST) the voltage on the CT
pin should be a sawtooth with a 0.9VP-P swing. This
voltage should never dip below 2V as shown in Figure 6a.
When load currents are low (ILOAD < IBURST) Burst Mode
operation occurs. The voltage on the CT pin now falls to
ground for periods of time as shown in Figure 6b. During
this time the LTC1147 series are in sleep mode with the
quiescent current reduced to 160µA.
The inductor current should also be monitored. Look to
verify that the peak-to-peak ripple current in continuous
mode operation is approximately the same as in Burst
Mode operation.
PD = ISC(AVG)(VD)
3.3V
With the 0.1Ω sense resistor ISC(AVG) = 1A will result,
increasing the 0.4V Schottky diode dissipation to 0.4W.
CIN will require an RMS current rating of at least 0.5A at
temperature, and COUT will require an ESR of 0.1Ω for
optimum efficiency.
Now allow VIN to drop to its minimum value. At lower input
voltages the operating frequency will decrease and the
P-channel will be conducting most of the time, causing the
power dissipation to increase. At VIN(MIN) = 4.5V, the
frequency will decrease and the P-channel will be conducting most of the time causing its power dissipation to
increase. At VIN(MIN) = 4.5V:
0V
Figure 6a. Continuous Mode Operation CT Waveform
3.3V
0V
LTC1147 • F06
Figure 6b. Burst Mode Operation CT Waveform
If Pin 2 is observed falling to ground at high output
currents, it indicates poor decoupling or improper grounding. Refer to the Board Layout Checklist.
sn1147 1147fds
12
LTC1147-3.3
LTC1147-5/LTC1147L
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Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1147 series. These items are also illustrated graphically in the layout diagram of Figure 7. Check the following
in your layout:
1. Are the signal and power grounds segregated? The
LTC1147 ground (Pin 7) must return separately to a)
the power and b) signal grounds. The power ground
(a) returns to the source anode of the Schottky diode
and (–) plate of CIN, which should have lead lengths
as short as possible. The signal ground (b) connects
to the (–) plate of COUT.
3. Are the SENSE – and SENSE + leads routed together with
minimum PC trace spacing? The 1000pF capacitor
between Pins 4 and 5 should be as close as possible to
the LTC1147.
4. Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? This capacitor provides the AC current to the P-channel MOSFET.
5. Is the input decoupling capacitor (0.1µF/1µF) connected closely between VIN (Pin 1) and ground (Pin 7)?
This capacitor carries the MOSFET driver peak currents.
6. On fixed output versions, is the SHDN (Pin 6) actively
pulled to ground during normal operation? The SHDN
pin is high impedance and must not be allowed to float.
2. Does the LTC1147 SENSE – (Pin 4) connect to a point
close to RSENSE and the (+) plate of COUT?
+
BOLD LINES INDICATE HIGH CURRENT PATHS
P-CH
L
+
VIN
RSENSE
D1
CIN
+
+
COUT
–
VOUT
–
1µF
+
LTC1147-3.3
LTC1147-5
(LTC1147L)
1
2
3
390pF
3300pF
4
VIN
CT
ITH
SENSE –
PDRIVE
8
GND
7
SHDN
(VFB)
6
SENSE +
5
R1
R2
100pF
OUTPUT DIVIDER
REQUIRED WITH
ADJUSTABLE
VERSION ONLY
1k
1000pF
SHUTDOWN
LTC1147 • F07
Figure 7. LTC1147 Layout Diagram (See Board Layout Checklist)
For additional High Efficiency application circuits see Application Note 54.
sn1147 1147fds
13
LTC1147-3.3
LTC1147-5/LTC1147L
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TYPICAL APPLICATIO S
3.3V Low Dropout High Efficiency Regulator
VIN
3.5V TO 12V
+
CIN
47µF
16V
Si9433DY
D1
MBRS130LT3
0.1µF
L*
10µH
LTC1147L-3.3
1
2
3
CT
120pF
CC
3300pF
4
RC
1k
PDRIVE
VIN
CT
GND
ITH
SHDN
SENSE –
SENSE +
8
7
6
SHUTDOWN
5
+
RSENSE**
0.068Ω
0.01µF
COUT
100µF
10V
AVX
VOUT
3.3V/1.25A
*SUMIDA CDR74B-100LC
**IRC LRC-LR2010-01-R068-F
LTC1147 • F08
Precision Constant Current Source
VIN
10V TO 14V
+
Si3455DV
D1
MBRS130LT3
0.1µF
3
CC
3300pF 4
RC
1k
8
7
CT
GND
ITH
SHDN
(VFB)
6
SENSE +
5
SENSE –
0.01µF
100pF
R1
1.2k
RSENSE**
0.22Ω
R2
6.8k
+
COUT
100µF
16V
AVX
VOUT
*SUMIDA CDR74-221
**IRC LRC-LR2010-01-R068-F
VIN = 12.6V
0.8
IOUT (A)
2
CT
300pF
PDRIVE
VIN
1.0
L*
220µH
LTC1147L
1
IOUT vs VOUT For Figure 9
CIN
33µF
25V
0.6
0.4
0.2
0
0
2
6
4
VOUT (V)
8
10
LTC1147 F10
LTC1147 • F09
sn1147 1147fds
14
LTC1147-3.3
LTC1147-5/LTC1147L
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TYPICAL APPLICATIO S
2.5V/2A Regulator
VIN
3.5V TO 12V
+
Si9433DY
CIN
15µF
25V × 2
D1
MBRD330
0.1µF
L*
10µH
LTC1147L
1
2
3
CT
120pF
CC
3300pF
4
RC
1k
PDRIVE
VIN
8
7
CT
GND
ITH
SHDN
(VFB)
6
SENSE +
5
SENSE –
R1
49.9k
1%
I00pF
RSENSE**
0.05Ω
0.01µF
R2
49.9k
1%
+
COUT
220µF
10V × 2
AVX
2.5V/2A
*COILTRONICS CTX10-4
**IRC LR2512-01-0R050-G
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PACKAGE DESCRIPTIO
LTC1147 • F11
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.100 ± 0.010
(2.540 ± 0.254)
0.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.125
(3.175) 0.020
MIN (0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
sn1147 1147fds
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1147-3.3
LTC1147-5/LTC1147L
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TYPICAL APPLICATION
3.3V/2A Output High Efficiency Regulator
VIN
4V TO 14V
+
Si4431DY
0.1µF
1
2
3
CT
220pF
CC
3300pF
4
RC
1k
PDRIVE
VIN
GND
LTC1147-3.3
SHDN
ITH
CT
SENSE +
SENSE –
L*
D1
20µH MBRS130LT3
8
7
6
SHUTDOWN
COUT
220µF
10V
AVX
5
+
0.01µF
RSENSE**
0.05Ω
*COILTRONICS CTX20-4
**KRL SP-1/2-A1-OR050
LTC1147 • F12
U
PACKAGE DESCRIPTIO
CIN
22µF
25V × 2
VOUT
3.3V/2A
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
8
0.004 – 0.010
(0.101 – 0.254)
7
6
5
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
0.050
(1.270)
TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
1
2
3
4
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Dual Version of LTC1148
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Dual High Efficiency Step-Down Switching Regulator Controller
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LTC1147
High Efficiency Step-Down Switching Regulator Controller
Nonsynchronous, 8-Lead, VIN ≤ 16V
LTC1148
High Efficiency Step-Down Switching Regulator Controller
Synchronous, VIN ≤ 20V
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High Efficiency Step-Down Switching Regulator
Synchronous, VIN ≤ 48V, for Standard Threshold FETs
LTC1159
High Efficiency Step-Down Switching Regulator
Synchronous, VIN ≤ 40V for Logic Level MOSFETS
LTC1174
High Efficiency Step-Down and Inverting DC/DC Converter
0.5A Switch, VIN ≤ 18.5V, Comparator
LTC1265
High Efficiency Step-Down DC/DC Converter
1.2A Switch, VIN ≤ 13V, Comparator
LTC1267
Dual High Efficiency Synchronous Step-Down Switching Regulators
Dual Version of LTC1159
LTC1435
High Efficiency Low Noise Synchronous Step-Down Switching Regulator
16-Pin Narrow SO/SSOP; Constant Frequency
sn1147 1147fds
16 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
LT/TP 0698 REV D 2K • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 1993