POINN BULD50 Npn silicon transistor with integrated diode Datasheet

BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
Copyright © 1997, Power Innovations Limited, UK
●
Designed Specifically for High Frequency
Electronic Ballasts
●
Integrated Fast trr Anti-Parallel Diode,
Enhancing Reliability
●
Diode trr Typically 1 µs
●
New Low-Height SL Power Package,
TO220 Pin-Compatible
●
Tightly Controlled Transistor Storage Times
●
Voltage Matched Integrated Transistor and
Diode
●
Characteristics Optimised for Cool Running
●
Diode-Transistor Charge Coupling
Minimised to Enhance Frequency Stability
FEBRUARY 1994 - REVISED SEPTEMBER 1997
TO-220 PACKAGE
(TOP VIEW)
B
1
C
2
E
3
Pin 2 is in electrical contact with the mounting base.
MDTRACA
SL PACKAGE
(TOP VIEW)
B
1
C
2
E
3
description
The new BULDxx range of transistors have been
designed specifically for use in High Frequency
Electronic Ballasts (HFEB’s). This range of
switching transistors has tightly controlled
storage times and an integrated fast trr antiparallel diode. The revolutionary design ensures
that the diode has both fast forward and reverse
recovery times, achieving the same performance
as a discrete anti-parallel diode plus transistor.
The integrated diode has minimal charge
coupling with the transistor, increasing frequency
stability, especially in lower power circuits where
the circulating currents are low. By design, this
new device offers a voltage matched integrated
transistor and anti-parallel diode.
device symbol
C
B
E
absolute maximum ratings at 25°C ✝ (unless otherwise noted)
SYMBOL
VALUE
UNIT
Collector-emitter voltage (V BE = 0)
RATING
VCES
600
V
Collector-base voltage (IE = 0)
VCBO
600
V
Collector-emitter voltage (IB = 0)
VCEO
400
V
Emitter-base voltage
V EBO
9
V
IC
3.5
A
ICM
6
A
IB
1.5
A
IBM
2.5
A
Continuous collector current
BULD50KC
BULD50SL (see Note 1)
Peak collector current (see Note 2)
BULD50KC
Continuous base current
BULD50SL (see Note 1)
Peak base current (see Note 2)
NOTES: 1. This value applies for tp = 1 s.
2. This value applies for tp = 10 ms, duty cycle ≤ 2%.
✝ ≤ 25°C case temperature for BULD50KC, and ≤ 25°C ambient temperature for BULD50SL
PRODUCT
INFORMATION
Information is current as of publication date. Products conform to specifications in accordance
with the terms of Power Innovations standard warranty. Production processing does not
necessarily include testing of all parameters.
1
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
absolute maximum ratings at 25°C ✝ (unless otherwise noted) (continued)
RATING
SYMBOL
BULD50KC
Continuous device dissipation
50
Ptot
BULD50SL
Maximum average continuous diode forward current
VALUE
see Figure 11
UNIT
W
IE(av)
0.5
A
Tj
-65 to +150
°C
Tstg
-65 to +150
°C
Operating junction temperature range
Storage temperature range
electrical characteristics at 25°C case temperature
PARAMETER
V CEO(sus)
ICES
IEBO
V BE(sat)
VCE(sat)
hFE
V EC
trr
Collector-emitter
sustaining voltage
Collector-emitter
cut-off current
Emitter cut-off
current
Base-emitter
saturation voltage
TEST CONDITIONS
MIN
IC = 100 mA
L = 25 mH
400
VCE = 600 V
VBE = 0
10
µA
VEB =
IC = 0
1
mA
0.9
1.1
V
0.2
0.5
0.4
1
9V
IB = 150 mA
IC = 750 mA
Collector-emitter
IB = 150 mA
IC = 750 mA
saturation voltage
IB = 300 mA
IC = 1.5 A
Forward current
transfer ratio
Anti-parallel diode
forward voltage
VCE = 10 V
IC = 10 mA
VCE =
1V
IC = 750 mA
VCE =
5V
IC = 1.5 A
IE =
1A
(see Notes 3 and 4)
(see Notes 3 and 4)
(see Notes 3 and 4)
UNIT
V
17
10
15
20
10
15
20
1.25
1.5
(see Note 5)
reverse recovery time
MAX
10
(see Notes 3 and 4)
Anti-parallel diode
TYP
1
V
V
µs
NOTES: 3. These parameters must be measured using pulse techniques, tp = 300 µs, duty cycle ≤ 2%.
4. These parameters must be measured using voltage-sensing contacts, separate from the current carrying contacts, and located
within 3.2 mm from the device body.
5. Tested in a typical High Frequency Electronic Ballast.
thermal characteristics
PARAMETER
RθJA
Junction to free air thermal resistance
RθJC
Junction to case thermal resistance
MIN
TYP
MAX
UNIT
BULD50KC
62.5
BULD50SL
115
BULD50KC
2.5
°C/W
TYP
MAX
UNIT
3.35
4.5
µs
TYP
MAX
UNIT
150
250
ns
°C/W
inductive-load switching characteristics at 25°C case temperature
PARAMETER
tsv
TEST CONDITIONS
Storage time
MIN
IC = 750 mA
IB(on) = 150 mA
VCC = 40 V
L = 1 mH
IB(off) = 150 mA
V CLAMP = 300 V
resistive-load switching characteristics at 25°C case temperature
PARAMETER
tfi
Current fall time
PRODUCT
2
TEST CONDITIONS
IC = 750 mA
IB(on) = 150 mA
V CC = 300 V
IB(off) = 150 mA
INFORMATION
MIN
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
TYPICAL CHARACTERISTICS
ANTI-PARALLEL DIODE
INSTANTANEOUS FORWARD CURRENT
vs
INSTANTANEOUS FORWARD VOLTAGE
FORWARD CURRENT TRANSFER RATIO
vs
COLLECTOR CURRENT
LDX50SHF
30
LDX50SVF
10
TC = 25°C
IE - Instantaneous Forward Current - A
hFE - Forward Current Transfer Ratio
TC = 25°C
10
VCE = 1 V
VCE = 5 V
VCE = 10 V
1·0
0·01
1·0
0·1
0·01
0·1
1·0
10
0
IC - Collector Current - A
0·5
1·0
1·5
2·0
2·5
3·0
VEC - Instantaneous Forward Voltage - V
Figure 1.
Figure 2.
BASE-EMITTER SATURATION VOLTAGE
vs
CASE TEMPERATURE
LDX50SVB
VBE(sat) - Base-Emitter Saturation Voltage - V
1.0
IC = 750 mA
IB = 150 mA
0.9
0.8
0.7
0.6
0
25
50
75
100
TC - Case Temperature - °C
Figure 3.
PRODUCT
INFORMATION
3
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
MAXIMUM SAFE OPERATING REGIONS
MAXIMUM FORWARD-BIAS
SAFE OPERATING AREA
LDX50CFB
10
IC - Collector Current - A
IC - Collector Current - A
10
MAXIMUM FORWARD-BIAS
SAFE OPERATING AREA
1·0
0·1
BULD50KC
TC = 25°C
tp = 100 µs
tp = 1 ms
tp = 10 ms
DC Operation
0·01
1·0
10
100
1·0
0·1
BULD50SL
TA = 25°C
tp = 100 µs
tp = 10 ms
tp = 1 s
0·01
1·0
1000
10
VCE - Collector-Emitter Voltage - V
100
VCE - Collector-Emitter Voltage - V
Figure 4.
Figure 5.
MAXIMUM REVERSE-BIAS
SAFE OPERATING AREA
LDX50SRB
8
IC - Collector Current - A
IB(on) = IC / 5
VBE(off) = -5 V
TA
= 25°C
6
4
2
0
0
100
200
300
400
500
600
VCE - Collector-Emitter Voltage - V
Figure 6.
PRODUCT
4
INFORMATION
LDX50SFB
700
800
1000
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
THERMAL INFORMATION
ZθJA/R θJA - Normalised Transient Thermal Impedance
THERMAL RESPONSE JUNCTION TO AMBIENT
vs
POWER PULSE DURATION
LDX50CZA
1·0
60%
40%
BULD50KC
TA = 25°C
20%
10%
0·1
t1
0%
0·01
duty cycle = t1/t2
Read time at end of t1,
t2
Z

T J ( max ) – T A = P D ( peak) •  θ JA  • R θ JA ( max )
R
 θ JA 
0·001
10-4
10-3
10-2
10-1
10 0
101
102
103
t1 - Power Pulse Duration - s
Figure 7.
ZθJA/R θJA - Normalised Transient Thermal Impedance
THERMAL RESPONSE JUNCTION TO AMBIENT
vs
POWER PULSE DURATION
LDX50SZA
0·1
BULD50SL
TA = 25°C
60%
40%
20%
10%
0·01
t1
duty cycle = t1/t2
Read time at end of t1,
Z

T J ( max ) – T A = P D ( peak) •  θ JA  • R θ JA ( max )
R
 θ JA 
0%
0·001
10-4
t2
10-3
10-2
10 -1
100
101
102
103
t1 - Power Pulse Duration - s
Figure 8.
PRODUCT
INFORMATION
5
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
THERMAL INFORMATION
Zθ JC/R θJC - Normalised Transient Thermal Impedance
THERMAL RESPONSE JUNCTION TO CASE
vs
POWER PULSE DURATION
LDX50CZC
1·0
BULD50KC
TC = 25°C
60%
40%
20%
10%
0%
0·1
t1
duty cycle = t1/t2
Read time at end of t1,
t2
Z

T J ( max) – T C = P D ( peak ) •  θ JC  • R θ JC ( max)
R
 θ JC 
0·01
10-4
10-3
10-2
10-1
100
10 1
t1 - Power Pulse Duration - s
Figure 9.
MAXIMUM POWER DISSIPATION JUNCTION TO AMBIENT
vs
POWER PULSE DURATION
Ptot - Maximum Power Dissipation - W
1000
BULD50KC
TA = 25°C
0%
100
10%
10
20%
40%
60%
1·0
10-4
10-3
10-2
10-1
10 0
t1 - Power Pulse Duration - s
Figure 10.
PRODUCT
6
LDX50CPA
INFORMATION
101
102
103
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
THERMAL INFORMATION
MAXIMUM POWER DISSIPATION JUNCTION TO AMBIENT
vs
POWER PULSE DURATION
Ptot - Maximum Power Dissipation - W
100
10
0%
LDX50SPA
BULD50SL
TA = 25°C
10%
20%
40%
60%
1·0
10-4
10-3
10 -2
10-1
10 0
101
10 2
103
t1 - Power Pulse Duration - s
Figure 11.
MAXIMUM POWER DISSIPATION JUNCTION TO CASE
vs
POWER PULSE DURATION
1000
BULD50KC
TC = 25°C
0%
Ptot - Maximum Power Dissipation - W
LDX50CPC
10%
20%
40%
100
60%
10
10-4
10-3
10-2
10-1
100
101
t1 - Power Pulse Duration - s
Figure 12.
PRODUCT
INFORMATION
7
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
MECHANICAL DATA
TO-220
3-pin plastic flange-mount package
This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
TO220
4,70
4,20
ø
10,4
10,0
3,96
3,71
1,32
1,23
2,95
2,54
see Note B
6,6
6,0
15,90
14,55
see Note C
6,1
3,5
1,70
1,07
0,97
0,61
1
2
14,1
12,7
3
2,74
2,34
5,28
4,88
VERSION 1
0,64
0,41
2,90
2,40
VERSION 2
ALL LINEAR DIMENSIONS IN MILLIMETERS
NOTES: A. The centre pin is in electrical contact with the mounting tab.
B. Mounting tab corner profile according to package version.
C. Typical fixing hole centre stand off height according to package version.
Version 1, 18.0 mm. Version 2, 17.6 mm.
PRODUCT
8
INFORMATION
MDXXBE
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
MECHANICAL DATA
SL003
3-pin plastic single-in-line package
This single-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
SL003
4,57 (0.180)
MAX
10,2 (0.400) MAX
6,60 (0.260)
6,10 (0.240)
8,31 (0.327)
MAX
Index
Dot
12,9 (0.492)
MAX
4,267 (0.168)
MIN
1
1,854 (0.073) MAX
2
3
Pin Spacing
2,54 (0.100) T.P.
(see Note A)
2 Places
0,356 (0.014)
0,203 (0.008)
3 Places
0,711 (0.028)
0,559 (0.022)
3 Places
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. Body molding flash of up to 0,15 (0.006) may occur in the package lead plane.
PRODUCT
MDXXAD
INFORMATION
9
BULD50KC, BULD50SL
NPN SILICON TRANSISTOR WITH INTEGRATED DIODE
FEBRUARY 1994 - REVISED SEPTEMBER 1997
IMPORTANT NOTICE
Power Innovations Limited (PI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to verify, before placing orders, that the
information being relied on is current.
PI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with PI's standard warranty. Testing and other quality control techniques are utilized to the extent PI
deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except as mandated by government requirements.
PI accepts no liability for applications assistance, customer product design, software performance, or infringement
of patents or services described herein. Nor is any license, either express or implied, granted under any patent
right, copyright, design right, or other intellectual property right of PI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
PI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS.
Copyright © 1997, Power Innovations Limited
PRODUCT
10
INFORMATION
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