MOTOROLA MCM67D709FN20 128k x 9 bit synchronous dual i/o fast static ram Datasheet

MOTOROLA
Order this document
by MCM67D709/D
SEMICONDUCTOR TECHNICAL DATA
MCM67D709
128K x 9 Bit Synchronous
Dual I/O Fast Static RAM
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
88110/88410 Compatibility: –16/60 MHz, –20/50 MHz
Self–Timed Write Cycles
Clock Controlled Output Latches
Address and Data Input Registers
Common Data Inputs and Data Outputs
Dual I/O for Separate Processor and Memory Buses
Separate Output Enable Controlled Three–State Outputs
3.3 V I/O Compatible
High Board Density 52 Lead PLCC Package
Can be used as Separate I/O x9 SRAM
FN PACKAGE
PLASTIC
CASE 778–02
SIE
PIE
SOE
POE
WE
K
VCC
VSS
NC
A6
A4
A2
A0
PIN ASSIGNMENTS
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
A8
A7
A5
A3
A1
A16
A15
PDQ7
SDQ7
VSS
PDQ5
SDQ5
VCC
PDQ3
SDQ3
VSS
PDQ1
SDQ1
A14
A13
A12
A11
A10
VSS
VCC
A9
The MCM67D709 is a 1,179,648 bit synchronous static random access
memory organized as 131,072 words of 9 bits, fabricated using Motorola’s
high–performance silicon–gate BiCMOS technology. The device integrates a
128K x 9 SRAM core with advanced peripheral circuitry consisting of address
registers, two sets of input data registers and two sets of output latches. This
device has increased output drive capability supported by multiple power pins.
Asynchronous inputs include the processor output enable (POE) and the
system output enable (SOE).
The address inputs (A0 – A16) are synchronous and are registered on the
falling edge of clock (K). Write enable (W), processor input enable (PIE) and
system input enable (SIE) are registered on the rising edge of clock (K). Writes
to the RAM are self–timed.
All data inputs/outputs, PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, and SDQP
have input data registers triggered by the rising edge of the clock. These pins also
have three–state output latches which are transparent during the high
level of the clock and latched during the low level of the clock.
This device has a special feature which allows data to be passed through the
RAM between the system and processor ports in either direction. This streaming
is accomplished by latching in data from one port and asynchronously output
enabling the other port. It is also possible to write to the RAM while streaming.
The MCM67D709’s dual I/Os can be used in x9 separate I/O applications.
Common I/Os PDQ0 – 7, PDQP and SDQ0 – 7, SDQP can be treated as either
inputs (D) or outputs (Q) depending on the state of the control pins. In order to
dedicate PDQ0 – 7, PDQP as data (D) inputs and SDQ0 – 7, SDQP as outputs
(Q), tie SIE and POE high. SOE becomes the asynchronous G for the outputs.
PIE will need to track W for proper write/read operations.
This device is ideally suited for pipelined systems and systems with multiple
data buses and multi–processing systems, where a local processor has a bus
isolated from a common system bus.
PIN NAMES
A0 – A16 . . . . . . . . . . . . . . . Address Inputs
K . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
PIE . . . . . . . . . . . . . Processor Input Enable
SIE . . . . . . . . . . . . . . . System Input Enable
POE . . . . . . . . . . Processor Output Enable
SOE . . . . . . . . . . . . . System Output Enable
PDQ0 – PDQ7 . . . . . . . Processor Data I/O
PDQP . . . . . . . . . . . Processor Data Parity
SDQ0 – SDQ7 . . . . . . . . . System Data I/O
SDQP . . . . . . . . . . . . . System Data Parity
VCC . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . No Connection
All power supply and ground pins must be
connected for proper operation of the
device.
REV2
5/95
 Motorola, Inc. 1994
MOTOROLA
FAST SRAM
MCM67D709
1
PDQP
SDQP
VSS
PDQ6
SDQ6
VCC
PDQ4
SDQ4
PDQ2
SDQ2
VSS
PDQ0
SDQ0
BLOCK DIAGRAM
POE
PDQ0 – PDQ7, PDQP
9
K
DATA
REGISTER
DATA
LATCH
REGISTER
128K x 9 ARRAY
WRITE
DRIVER
SENSE
AMPLIFIER
CONTROL
A0 – A16
9
DATA
REGISTER
DATA
LATCH
9
W
PIE
SOE
SDQ0 – SDQ7, SDQP
SIE
FUNCTIONAL TRUTH TABLE (See Notes 1 and 2)
W
PIE
SIE
POE
SOE
Mode
Memory Subsystem
Cycle
PDQ0 – PDQ7,
PDQP Output
SDQ0 – SDQ7,
SDQP Output
Notes
1
1
1
0
1
Read
Processor Read
Data Out
High–Z
3
1
1
1
1
0
Read
Copy Back
High–Z
Data Out
3
1
1
1
0
0
Read
Dual Bus Read
Data Out
Data Out
3
1
X
X
1
1
Read
NOP
High–Z
High–Z
X
0
0
X
X
N/A
NOP
High–Z
High–Z
2, 4
0
0
1
1
1
Write
Processor Write Hit
Data In
High–Z
2, 5
0
1
0
1
1
Write
Allocate
High–Z
Data In
2, 5
0
0
1
1
0
Write
Write Through
Data In
Stream Data
2, 6
0
1
0
0
1
Write
Allocate With Stream
Stream Data
Data In
2, 6
1
0
1
1
0
N/A
Cache Inhibit Write
Data In
Stream Data
2, 6
1
1
0
0
1
N/A
Cache Inhibit Read
Stream Data
Data In
2, 6
0
1
1
X
X
N/A
NOP
High–Z
High–Z
4
X
0
1
0
0
N/A
Invalid
Data In
Stream
2, 7
X
0
1
0
1
N/A
Invalid
Data In
High–Z
2, 7
X
1
0
0
0
N/A
Invalid
Stream
Data In
2, 7
X
1
0
1
0
N/A
Invalid
High–Z
Data In
2, 7
NOTES:
1. A ‘0’ represents an input voltage ≤ VIL and a ‘1’ represents an input voltage ≥ VIH. All inputs must satisfy the specified setup and hold times
for the falling or rising edge of K. Some entries in this truth table represent latched values. Other possible combinations of control inputs not
covered by this note or the table above are not supported and the RAMs behavior is not specified.
2. If either IE signal is sampled low on the rising edge of clock, the corresponding OE is a don’t care, and the corresponding outputs are
High–Z.
3. A read cycle is defined as a cycle where data is driven on the internal data bus by the RAM.
4. No RAM cycle is performed.
5. A write cycle is defined as a cycle where data is driven onto the internal data bus through one of the data I/O ports (PDQ0 – PDQ7 and
PDQP or SDQ0 – SDQ7 and SPDQ), and written into the RAM.
6. Data is driven on the internal data bus by one I/O port through its data input register and latched into the data output latch of the other
I/O port.
7. Data contention will occur.
MCM67D709
2
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current (per I/O)
Iout
± 30
mA
Power Dissipation
PD
2.0
W
Temperature Under Bias
Tbias
– 10 to + 85
°C
Operating Temperature
TA
0 to +70
°C
Rating
Power Supply
Voltage Relative to VSS for Any Pin
Except VCC
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
Tstg
– 55 to + 125
°C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Storage Temperature
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS (Voltages referenced to VSS = 0 V)
Parameter
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.75
5.25
V
Input High Voltage
VIH
2.2
VCC + 0.3**
V
Input Low Voltage
VIL
– 0.5*
0.8
V
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (POE, SOE = VIH)
Ilkg(O)
—
± 1.0
µA
—
—
280
260
AC Supply Current (All Inputs = VIL or VIH,VIL = 0.0 V and VIH ≥ 3.0 V,
Iout = 0 mA, Cycle Time ≥ tKHKH min)
MCM67D709–16: tKHKH = 16 ns
MCM67D709–20: tKHKH = 20 ns
ICCA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
3.3
V
mA
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance (All Pins Except I/Os)
Input/Output Capacitance (PDQ0 – PDQ7, SDQ0 – SDQ7, PDQP, SDQP)
MOTOROLA FAST SRAM
Symbol
Typ
Max
Unit
Cin
5
6
pF
Cout
6
7
pF
MCM67D709
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
READ CYCLE (See Note 1)
Processor Frequency
Parameter
60 MHz
50 MHz
MCM67D709–16
MCM67D709–20
Symbol
Min
Max
Min
Max
Unit
Notes
Read Cycle Time Clock High to Clock High
tKHKH
16
—
20
—
ns
1, 2
Clock Low Pulse Width
tKLKH
5
—
5
—
ns
Clock High Pulse Width
tKHKL
7
—
7
—
ns
Clock High to Output Valid
tKHQV
—
6
—
7.5
ns
Clock (K) High to Output Low Z After Write
tKHQX1
0
—
0
—
ns
Output Hold from Clock High
tKHQX2
2
—
3
—
ns
3
3, 4
Setup Times:
A
W
PIE
SIE
tAVKL
tWHKH
tPIEHKH
tSIEHKH
2
2
2
2
—
2
2
2
2
—
ns
Hold Times:
A
W
PIE
SIE
tKLAX
tKHWX
tKHPIEX
tKHSIEX
2
2
2
2
—
2
2
2
2
—
ns
Output Enable High to Q High–Z
tPOEHQZ
tSOEHQZ
0
6
0
8
ns
4
Output Hold from Output Enable High
tPOEHQX
tSOEHQX
2
—
5
—
ns
4
Output Enable Low to Q Active
tPOELQX
tSOELQX
0
—
0
—
ns
4
Output Enable Low to Output Valid
tPOELQV
tSOELQV
—
5
—
6
ns
NOTES:
1. A read is defined by W high for the setup and hold times.
2. All read cycle timing is referenced from K, SOE, or POE.
3. K must be at a high level for outputs to transition.
4. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for
a given device.
AC SPEC LOADS
+5V
RL = 50 Ω
OUTPUT
480 Ω
OUTPUT
Z0 = 50 Ω
255 Ω
5 pF
VL = 1.5 V
Figure 1A
MCM67D709
4
Figure 1B
MOTOROLA FAST SRAM
READ CYCLE (See Note)
tKHKH
tKLKH
tKHKL
K
tKLAX
tAVKL
A0 – A16
An
An + 1
An + 2
tKHPIEX
tPIEHKH
PIE
tKHSIEX
tSIEHKH
SIE
tKHWX
tWHKH
W
POE
tPOELQV
tPOELQX
tPOEHQZ
tPOEHQX
SOE
tSOELQV
Qn
PDQ0 – PDQ7, PDQP
tKHQX1
tKHQV
SDQ0 – SDQ7, SDQP
Qn
Qn + 1
tKHQX2
MOTOROLA FAST SRAM
MCM67D709
5
WRITE THROUGH – READ – WRITE (See Note 1)
60 MHz
50 MHz
MCM67D709–16
MCM67D709–20
Processor Frequency
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write Cycle Times
tKHKH
16
—
20
—
ns
1, 2
Clock Low Pulse Width
tKLKH
5
—
5
—
ns
Clock High Pulse Width
tKHKL
7
—
7
—
ns
Clock High to Output High–Z (W = VIL and
SIE = PIE = VIH)
tKHQZ
—
8
—
8
ns
3, 4
Setup Times:
A
W
PIE
SIE
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
tAVKL
tWLKH
tPIEVKH
tSIEVKH
tDVKH
2
2
2
2
2
—
2
2
2
2
2
—
ns
Hold Times:
A
W
PIE
SIE
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
tKLAX
tKHWX
tKHPIEX
tKHSIEX
tKHDX
2
2
2
2
2
—
2
2
2
2
2
—
ns
tKHQV
—
5
—
7
ns
5
Output Enable High to Q High–Z
tPOEHQZ
tSOEHQZ
0
6
0
8
ns
6
Output Hold from Output Enable High
tPOEHQX
tSOEHQX
2
—
5
—
ns
6
Output Enable Low to Q Active
tPOELQX
tSOELQX
0
—
0
—
ns
6
Output Enable Low to Output Valid
tPOELQV
tSOELQV
—
5
—
6
ns
Write with Streaming (PIE = SOE = VIL or
SIE = POE = VIL) Clock High to Output Valid
NOTES:
1. A write is performed with W = VIL for the specified setup and hold times and either PIE = VIL or SIE = VIL. If both PIE = VIL and SIE = VIL or
PIE = VIH and SIE = VIH, then this is treated like a NOP and no write is performed.
2. All write cycle timings are referenced from K.
3. K must be at a high level for the outputs to transition.
4. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
5. A write with streaming is defined as a write cycle which writes data from one data bus to the array and outputs the same data onto the
other data bus.
6. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tPOEHQZ is less than tPOELQX for a given device, and tSOEHQZ is less than tSOELQX for
a given device.
MCM67D709
6
MOTOROLA FAST SRAM
WRITE THROUGH — READ — WRITE
tKHKH
tKLKH
tKHKL
K
tKLAX
tAVKL
A0 – A16
An
An + 1
An + 2
tKHPIEX
tPIEVKH
tPIEHKH
tKHPIEX
tSIEVKH
tSIEHKH
tKHSIEX
tWLKH
tWHKH
tKHWX
PIE
tKHSIEX
SIE
tKHWX
W
POE
tPOEHQZ
SOE
tPOEHQX
tDVKH
tKHDX
Qn – 1
Qn
+1
Dn
tKHQV
SDQ0 – SDQ7, SDQP
MOTOROLA FAST SRAM
tPOEHQZ
tDVKH
tPOELQV
tSOEHQX
tSOELQV
PDQ0 – PDQ7, PDQP
tKHDX
tSOEHQZ
Qn – 1
Dn + 2
tPOELQX
Qn
(STREAMED)
MCM67D709
7
STREAM CYCLE (See Note 1)
60 MHz
50 MHz
MCM67D709–16
MCM67D709–20
Processor Frequency
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Stream Cycle Time
tKHKH
16
—
20
—
ns
1, 2
Clock Low Pulse Width
tKLKH
5
—
5
—
ns
Clock High Pulse Width
tKHKL
7
—
7
—
ns
Stream Access Time
tKHQV
—
6
—
7
ns
Setup Times:
A
W
PIE
SIE
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
tAVKL
tWHKH
tPIEVKH
tSIEVKH
tDVKH
2
2
2
2
2
—
2
2
2
2
2
—
ns
Hold Times:
A
W
PIE
SIE
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
tKLAX
tKHWX
tKHPIEX
tKHSIEX
tKHDX
2
2
2
2
2
—
2
2
2
2
2
—
ns
Output Enable High to Q High–Z
tPOEHQZ
tSOEHQZ
0
6
0
8
ns
3
Output Enable Low to Q Active
tPOELQX
tSOELQX
0
—
0
—
ns
3
Output Enable Low to Output Valid
tPOELQV
tSOELQV
—
5
—
6
ns
NOTES:
1. A stream cycle is defined as a cycle where data is passed from one data bus to the other data bus.
2. All stream cycle timing is referenced from K.
3. Transition is measured ± 500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tPOEHQZ is less than tPOELQX, tSOEHQZ is less than tSOELQX, for a given device.
MCM67D709
8
MOTOROLA FAST SRAM
STREAM CYCLE
tKHKH
tKLKH
tKHKL
K
tKLAX
tAVKL
An
A0 – A16
An + 1
tKHPIEX
An + 2
tPIEVKH
PIE
tKHSIEX
tSIEVKH
SIE
tKHWX
tWHKH
W
POE
tPOEHQZ
SOE
tSOEHQZ
tDVKH
PDQ0 – PDQ7, PDQP
Qn – 1
tKHQV
tKHDX
Dn
Qn + 1 (STREAMED)
tKHQV
SDQ0 – SDQ7, SDQP
MOTOROLA FAST SRAM
Qn – 1
Qn
(STREAMED)
Dn + 1
MCM67D709
9
ORDERING INFORMATION
(Order by Full Part Number)
MCM
67D709
FN
Motorola Memory Prefix
XX
Speed (16 = 16 ns (60 MHz),
20 = 20 ns (50 MHz))
Part Number
Package (FN = PLCC)
Full Part Numbers — MCM67D709FN16
MCM67D709FN20
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MCM67D709
10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
FN PACKAGE
52–LEAD PLCC
CASE 778–02
B
Y BRK
-N-
0.007 (0.180)
M
T L –M
0.007 (0.180)
U
M
S
N
T L –M
S
N
S
0.010 (0.250)
S
S
D
-L-
-M-
52
LEADS
ACTUAL
(NOTE 1)
52
Z
W
D
1
G1
X
VIEW D-D
V
A
0.007 (0.180)
M
T L –M
S
N
S
R
0.007 (0.180)
M
T L –M
S
N
S
T L –M
N
S
S
Z
C
H
0.004 (0.100)
G
J
-T-
F
S
N
S
0.007 (0.180)
M
T L –M
S
N
S
VIEW S
G1
0.010 (0.250)
T L –M
K
SEATING
PLANE
VIEW S
S
M
K1
E
(NOTE 1)
52
0.007 (0.180)
T L –M
S
N
S
NOTES:
1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
REPRESENTED BY A GENERAL (SMALLER) CASE
OUTLINE DRAWING RATHER THAN SHOWING ALL 52
LEADS.
2. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF
LEAD SHOULDER EXITS PLASTIC BODY AT MOLD
PARTING LINE.
3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
4. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
6. CONTROLLING DIMENSION: INCH.
7. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS
R AND U ARE DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
8. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037 (0.940). THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025 (0.635).
MOTOROLA FAST SRAM
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.785 0.795
0.785 0.795
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
—
0.020
—
0.025
0.750 0.756
0.750 0.756
0.042 0.048
0.042 0.048
0.042 0.056
0.020
—
10°
2°
0.710 0.730
0.040
—
MILLIMETERS
MIN
MAX
19.94 20.19
19.94 20.19
4.20
4.57
2.79
2.29
0.48
0.33
1.27 BSC
0.81
0.66
—
0.51
—
0.64
19.05 19.20
19.05 19.20
1.07
1.21
1.07
1.21
1.07
1.42
—
0.50
10°
2°
18.04 18.54
1.02
—
MCM67D709
11
Literature Distribution Centers:
USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
MCM67D709
12
◊
CODELINE TO BE PLACED HERE
*MCM67D709/D*
MCM67D709/D
MOTOROLA FAST
SRAM