Lattice GAL20XV10B-10LP High-speed e2cmos pld generic array logic Datasheet

GAL20XV10
High-Speed E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS ® TECHNOLOGY
— 10 ns Maximum Propagation Delay
— Fmax = 100 MHz
— 7 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS® Advanced CMOS Technology
I/CLK
4
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
OLMC
I/O/Q
I
4
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 90mA Maximum Icc
— 75mA Typical Icc
I
• ACTIVE PULL-UPS ON ALL PINS
I
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100 ms)
— 20 Year Data Retention
PROGRAMMABLE
AND-ARRAY
(40 X 40)
4
I
I
I
• TEN OUTPUT LOGIC MACROCELLS
— XOR Gate Capability on all Outputs
— Full Function and Parametric Compatibility with
PAL12L10, 20L10, 20X10, 20X8, 20X4
— Registered or Combinatorial with Polarity
I
I
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
• APPLICATIONS INCLUDE:
— High Speed Counters
— Graphics Processing
— Comparators
4
4
4
4
4
I
4
I
4
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
I/OE
The GAL20XV10 combines a high performance CMOS process
with electrically erasable (E2) floating gate technology to provide
the highest speed Exclusive-OR PLD available in the market. At
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides
a substantial savings in power when compared to bipolar counterparts. E2CMOS technology offers high speed (<100ms) erase
times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently.
Pin Configuration
DIP
PLCC
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20XV10 are the PAL® architectures
listed in the macrocell description section of this document. The
GAL20XV10 is capable of emulating these PAL architectures with
full function and parametric compatibility.
4
I
2
I/O/Q
5
25
I
7
NC
I
GAL20XV10
Top View
9
23
I/OE
I/O/Q
NC
GND
I
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
16
I/O/Q
I
I/O/Q
I
GAL
20XV10
6
I/O/Q
I/O/Q
I/O/Q
18
I/O/Q
I
I/O/Q
I
I/O/Q
18
I
I/O/Q
I
I/O/Q
19
14
I/O/Q
I/O/Q
21
11
12
I/O/Q
NC
I
I
I/O/Q
I
Vcc
I/O/Q
I
24
I
26
28
1
I
I/O/Q
Vcc
I/CLK
NC
I
I
I/CLK
I/O/Q
I
GND
I/O/Q
12
13
I/OE
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com
20xv10_02
1
July 1997
Specifications GAL20XV10
GAL20XV10 Ordering Information
Commercial Grade Specifications
Tpd (ns)
Tsu (ns)
Tco (ns)
Icc (mA)
10
6
7
90
15
20
8
10
8
10
90
90
Ordering #
Package
GAL20XV10B-10LP
24-Pin Plastic DIP
GAL20XV10B-10LJ
28-Lead PLCC
GAL20XV10B-15LP
24-Pin Plastic DIP
GAL20XV10B-15LJ
28-Lead PLCC
GAL20XV10B-20LP
24-Pin Plastic DIP
GAL20XV10B-20LJ
28-Lead PLCC
Part Number Description
XXXXXXXX _ XX
GAL20XV10B
X X X
Device Name
Grade
Speed (ns)
L = Low Power Power
Blank = Commercial
Package P = Plastic DIP
J = PLCC
2
Specifications GAL20XV10
Output Logic Macrocell (OLMC)
Exclusive-OR macrocells. In Feedback mode, the state of the
register is available to the AND array via an internal feedback
path on all macrocells. In Input mode, the state of the register
is available to the AND array via an internal feedback path on
macrocells 2 through 9 only, macrocells 1 and 10 have no feedback
into the AND array.
The following discussion pertains to configuring the Output Logic
Macrocell. It should be noted that actual implementation is
accomplished by development software/hardware and is completely transparent to the user.
The GAL20XV10 has two global architecture configurations that
allow it to emulate PAL architectures. The Input mode emulates
combinatorial PAL devices, with the I/CLK and I/OE pins used as
inputs. The Feedback mode emulates registered PAL devices with
the I/CLK pin used as the register clock and the I/OE pin as an
output enable for all registers. The following is a list of PAL architectures that the GAL20XV10 can emulate. It also shows the
global architecture mode used to emulate the PAL architecture.
PAL Architectures Emulated by
GAL20XV10
PAL12L10
PAL20L10
PAL20X10
PAL20X8
PAL20X4
REGISTERED CONFIGURATION
The Macrocell is set to Registered configuration when AC0 = 1 and
AC1 = 0. Three of the four product terms are used as sum-ofproduct terms for the D input of the register. The inverting output
buffer is enabled by the fourth product term. The output is enabled while this product term is true. The XOR bit controls the polarity of the output. The register is clocked by the low-to-high transition of the I/CLK. In Feedback mode, the state of the register
is available to the AND array via an internal feedback path on
all macrocells. In Input mode, the state of the register is available
to the AND array via an internal feedback path on macrocells
2 through 9 only, macrocells 1 and 10 have no feedback into the
AND array.
GAL20XV10 Global
OLMC Mode
Input Mode
Input Mode
Feedback Mode
Feedback Mode
Feedback Mode
XOR COMBINATORIAL CONFIGURATION
The Macrocell is set to the Exclusive-OR Combinatorial configuration when AC0 = 0 and AC1 = 1. The four product terms are segmented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed to an output
buffer. The inverting output buffer is enabled by the I/OE pin,
which is an active low output enable that is common to all XOR
macrocells. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available to
the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
INPUT MODE
The Input mode architecture is defined when the global
architecture bit SYN = 1. In this mode, the I/CLK pin becomes an
input to the AND array and also provides the clock source for
all registers. The I/OE pin becomes an input into the AND array
and provides the output enable control for any macrocell configured as an Exclusive-OR function. Feedback into the AND array
is provided from macrocells 2 through 9 only. In this mode,
macrocells 1 and 10 have no feedback into the AND array.
FEEDBACK MODE
The Feedback mode architecture is defined when the global
architecture bit SYN = 0. In this mode the I/CLK pin becomes a
dedicated clock source for all registers. The I/OE pin is a dedicated output enable control for any macrocell configured as an
Exclusive-OR function. The I/CLK and I/OE pins are not available to the AND array in this mode. Feedback into the AND array
is provided on all macrocells 1 through 10.
COMBINATORIAL CONFIGURATION
The Macrocell is set to Combinatorial mode when AC0 = 1 and
AC1 = 1. Three of the four product terms are used as sum-ofproduct terms for the combinatorial output. The XOR bit controls
the polarity of the output. The inverting output buffer is enabled
by the fourth product term. The output is enabled while this product
term is true. In Feedback mode, the state of the I/O pin is available to the AND array via an internal feedback path on all
macrocells. In Input mode, the state of the I/O pin is available
to the AND array via an input buffer path on macrocells 2 through
9 only, macrocells 1 and 10 have no input into the AND array.
FEATURES
Each Output Logic Macrocell has four possible logic function
configurations controlled by architecture control bits AC0 and AC1.
Four product terms are fed into each macrocell.
XOR REGISTERED CONFIGURATION
The Macrocell is set to the Exclusive-OR Registered configuration
when AC0 = 0 and AC1 = 0. The four product terms are segmented into two OR-sums of two product terms each, which are
then combined by an Exclusive-OR gate and fed into a D-type
register. The register is clocked by the low-to-high transition of the
I/CLK pin. The inverting output buffer is enabled by the
I/OE pin, which is an active low output enable common to all
3
Specifications GAL20XV10
Input Mode
OE
D
XOR Registered Configuration
- SYN = 1.
- AC0 = 0.
- AC1 = 0.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- Pin 13(16) can be OE and/or Input.
Q
Q
CLK
D
XOR
Registered Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 0.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 1(2) can be CLK and/or Input.
- OE controlled by product term.
Q
Q
CLK
OE
XOR Combinatorial Configuration
- SYN = 1.
- AC0 = 0.
- AC1 = 1.
- OLMC 1 and OLMC10 do not have the
feedback path.
- Pin 13(16) can be OE and/or Input.
Combinatorial Configuration
- SYN = 1.
- AC0 = 1.
- AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OLMC 1 and OLMC10 do not have the
feedback path.
- OE controlled by product term.
XOR
4
Specifications GAL20XV10
Input Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
0
4
8
12
16
20
24
28
32
36
0
OLMC
XOR - 1600
AC0 - 1610
AC1 - 1620
120
23(27)
2(3)
OLMC
160
XOR - 1601
AC0 - 1611
AC1 - 1621
280
3(4)
22(26)
OLMC
320
XOR - 1602
AC0 - 1612
AC1 - 1622
440
4(5)
21(25)
OLMC
480
XOR - 1603
AC0 - 1613
AC1 - 1623
600
5(6)
20(24)
OLMC
640
XOR - 1604
AC0 - 1614
AC1 - 1624
760
6(7)
19(23)
OLMC
800
XOR - 1605
AC0 - 1615
AC1 - 1625
920
7(9)
18(21)
OLMC
960
XOR - 1606
AC0 - 1616
AC1 - 1626
1080
8(10)
17(20)
OLMC
1120
XOR - 1607
AC0 - 1617
AC1 - 1627
1240
9(11)
16(19)
OLMC
1280
XOR - 1608
AC0 - 1618
AC1 - 1628
1400
10(12)
15(18)
OLMC
1440
XOR - 1609
AC0 - 1619
AC1 - 1629
1560
14(17)
13(16)
11(13)
40-USER ELECTRONIC SIGNATURE FUSES
1631, 1632, ....
.... 1669, 1670
Byte4 Byte3 ....
.... Byte1 Byte0
5
SYN - 1630
Specifications GAL20XV10
Feedback Mode
OE
D
XOR Registered Configuration
- SYN = 0.
- AC0 = 0.
- AC1 = 0.
- Dedicated CLK input on Pin 1(2).
- Dedicated OE input on Pin 13(16).
Q
Q
CLK
D
XOR
Registered Configuration
- SYN = 0.
- AC0 = 1.
- AC1 = 0.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- Dedicated CLK input on Pin 1(2).
- OE controlled by product term.
- Pin 13(16) is not connected to this configuration.
Q
Q
CLK
OE
XOR Combinatorial Configuration
- SYN = 0.
- AC0 = 0.
- AC1 = 1.
- Dedicated OE input on Pin 13(16).
- Pin 1(2) is not connected to this configuration.
Combinatorial Configuration
- SYN = 0.
- AC0 = 1.
- AC1 = 1.
- XOR = 1 defines Active Low Output.
- XOR = 0 defines Active High Output.
- OE controlled by product term.
- Both pin1(2) and pin 13(16) are not con nected to this configuration.
XOR
6
Specifications GAL20XV10
Feedback Mode Logic Diagram
DIP (PLCC) Package Pinouts
1(2)
0
4
8
12
16
20
24
28
32
36
0
OLMC
XOR - 1600
AC0 - 1610
AC1 - 1620
120
2(3)
OLMC
160
XOR - 1601
AC0 - 1611
AC1 - 1621
280
3(4)
OLMC
320
XOR - 1602
AC0 - 1612
AC1 - 1622
440
4(5)
23(27)
22(26)
21(25)
OLMC
480
XOR - 1603
AC0 - 1613
AC1 - 1623
600
5(6)
OLMC
640
XOR - 1604
AC0 - 1614
AC1 - 1624
760
6(7)
OLMC
800
XOR - 1605
AC0 - 1615
AC1 - 1625
920
7(9)
OLMC
960
XOR - 1606
AC0 - 1616
AC1 - 1626
1080
8(10)
OLMC
1120
XOR - 1607
AC0 - 1617
AC1 - 1627
1240
9(11)
OLMC
1280
XOR - 1608
AC0 - 1618
AC1 - 1628
1400
10(12)
OLMC
1440
XOR - 1609
AC0 - 1619
AC1 - 1629
1560
11(13)
20(24)
19(23)
18(21)
17(20)
16(19)
15(18)
14(17)
13(16)
40-USER ELECTRONIC SIGNATURE FUSES
1631, 1632, ....
.... 1669, 1670
Byte4 Byte3 ....
.... Byte1 Byte0
7
SYN - 1630
Specifications GAL20XV10
Recommended Operating Conditions
Absolute Maximum Ratings(1)
Commercial Devices:
Ambient Temperature (TA) ............................. 0 to +75°C
Supply voltage (VCC)
with Respect to Ground ..................... +4.75 to +5.25V
Supply voltage Vcc ....................................... –0.5 to+7V
Input voltage applied .......................... –2.5 to VCC +1.0V
Off-state output voltage applied ......... –2.5 to VCC +1.0V
Storage Temperature ............................... –65 to 150°C
Ambient Temperature with
Power Applied .......................................... –55 to 125°C
1.Stresses above those listed under the “Absolute Maximum
Ratings” may cause permanent damage to the device. These
are stress only ratings and functional operation of the device at
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Electrical Characteristics
Over Recommended Operating Conditions (Unless Otherwise Specified)
SYMBOL
VIL
VIH
IIL1
IIH
VOL
VOH
IOL
IOH
IOS2
MIN.
TYP.3
MAX.
UNITS
Input Low Voltage
VSS – 0.5
—
0.8
V
Input High Voltage
2.0
—
VCC+1
V
PARAMETER
CONDITION
Input or I/O Low Leakage Current
0V ≤ VIN ≤ VIL (MAX.)
—
—
–100
µA
Input or I/O High Leakage Current
3.5V ≤ VIN ≤ VCC
—
—
10
µA
Output Low Voltage
IOL = MAX. Vin = VIL or VIH
—
—
0.5
V
Output High Voltage
IOH = MAX. Vin = VIL or VIH
2.4
—
—
V
Low Level Output Current
—
—
16
mA
High Level Output Current
—
—
–3.2
mA
–50
—
–150
mA
—
75
90
mA
Output Short Circuit Current
COMMERCIAL
ICC
Operating Power
Supply Current
VCC = 5V
VOUT = 0.5V TA= 25°C
VIL = 0.5V VIH = 3.0V
L -10/-15/-20
ftoggle = 15MHz Outputs Open
1) The leakage current is due to the internal pull-up on all input and I/O pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at VCC = 5V and TA = 25 °C
8
Specifications GAL20XV10
AC Switching Characteristics
Over Recommended Operating Conditions
PARAMETER
tpd
tco
tcf2
tsu
th
fmax3
twh
twl
ten
tdis
TEST
COND.1
COM
COM
COM
-10
-15
-20
MIN. MAX.
MIN. MAX.
MIN. MAX.
DESCRIPTION
UNITS
A
Input or I/O to Combinatorial Output
3
10
3
15
3
20
ns
A
Clock to Output Delay
2
7
2
8
2
10
ns
—
Clock to Feedback Delay
—
4
—
4
—
4
ns
—
Setup Time, Input or Feedback before Clock↑
6
—
8
—
10
—
ns
—
Hold Time, Input or Feedback after Clock↑
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
76.9
—
62.5
—
50
—
MHz
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
100
—
83.3
—
71.4
—
MHz
A
Maximum Clock Frequency with
No Feedback
100
—
83.3
—
71.4
—
MHz
—
Clock Pulse Duration, High
4
—
6
—
7
—
ns
—
Clock Pulse Duration, Low
4
—
6
—
7
—
ns
B
Input or I/O to Output Enabled
3
10
3
15
3
20
ns
B
OE to Output Enabled
2
9
2
10
2
15
ns
C
Input or I/O to Output Disabled
3
9
3
15
3
20
ns
C
OE to Output Disabled
2
9
2
10
2
15
ns
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
Capacitance (TA = 25°C, f = 1.0 MHz)
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
CI
Input Capacitance
8
pF
VCC = 5.0V, VI = 2.0V
CI/O
I/O Capacitance
8
pF
VCC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested
9
Specifications GAL20XV10
Switching Waveforms
INPUT or
I/O FEEDBACK
INPUT or
I/O FEEDBACK
VALID INPUT
VALID INPUT
ts u
t pd
th
CLK
tc o
COMBINATORIAL
OUTPUT
REGISTERED
OUTPUT
1 / fm a x
Combinatorial Output
(external fdbk)
Registered Output
INPUT or
I/O FEEDBACK
OE
t dis
tdis
t en
ten
OUTPUT
OUTPUT
Input or I/O Feedback to Enable/Disable
OE to Output Enable/Disable
CLK
tw l
tw h
1/ fmax (internal fdbk)
CLK
t cf
1 / fm a x
tsu
REGISTERED
FEEDBACK
(w/o fdbk)
Clock Width
fmax with Feedback
Input/Output Equivalent Schematics
PIN
PIN
Feedback
Active Pull-up
Circuit
Vcc
(Vref Typical = 3.2V)
Active Pull-up
Circuit
Vcc
Vref
Tri-State
Control
Vcc
Vcc
(Vref Typical = 3.2V)
Vref
ESD
Protection
Circuit
Data
Output
PIN
PIN
ESD
Protection
Circuit
Feedback
(To Input Buffer)
Typical Input
Typical Output
10
Specifications GAL20XV10
fmax Descriptions
CLK
LOGIC
ARRAY
REGISTER
CLK
LOGIC
ARRAY
tsu
tco
REGISTER
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured
tsu and tco.
t cf
t pd
CLK
fmax with Internal Feedback 1/(tsu+tcf)
LOGIC
ARRAY
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
REGISTER
tsu + th
fmax with No Feedback
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
+5V
GND to 3.0V
3ns 10% – 90%
1.5V
1.5V
Output Load
R1
See Figure
3-state levels are measured 0.5V from steady-state active
level.
FROM OUTPUT (O/Q)
UNDER TEST
Output Load Conditions (see figure)
Test Condition
A
B
C
Active High
Active Low
Active High
Active Low
TEST POINT
R2
R1
R2
CL
300Ω
∞
300Ω
∞
300Ω
390Ω
390Ω
390Ω
390Ω
390Ω
50pF
50pF
50pF
5pF
5pF
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
11
Specifications GAL20XV10
Electronic Signature
Latch-Up Protection
An electronic signature word is provided in every GAL20XV10
device. It contains 40 bits of reprogrammable memory that contains user defined data. Some uses include user ID codes, revision numbers, pattern identification or inventory control codes. The
signature data is always available to the user independent of the
state of the security cell.
GAL20XV10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch. Additionally, outputs are designed with n-channel pullups
instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching.
NOTE: The electronic signature bits, if programmed to any value
other then zero(0) will alter the checksum of the device.
Input Buffers
GAL20XV10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.
Security Cell
A security cell is provided in every GAL20XV10 device as a deterrent to unauthorized copying of the device pattern. Once programmed, this cell prevents further read access of the device
pattern information. This cell can be only be reset by reprogramming the device. The original pattern can never be examined once
this cell is programmed. The Electronic Signature is always available regardless of the security cell state.
GAL20XV10 input buffers have active pull-ups within their input
structure. This pull-up will cause any un-terminated input or
I/O to float to a TTL high (logical 1). Lattice Semiconductor
recommends that all unused inputs and tri-stated I/O pins be
connected to another active input, Vcc, or GND. Doing this will tend
to improve noise immunity and reduce Icc for the device.
Device Programming
Typical Input Pull-up Characteristic
GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers. Complete programming of the device takes less than a
second. Erasing of the device is transparent to the user, and is done
automatically as part of the programming cycle.
Input Current (µA)
0
-20
-40
-60
0
1.0
2.0
3.0
4.0
5.0
Input Voltage (Volts)
Power-Up Reset
of system power-up, some conditions must be met to provide a valid
power-up reset of the GAL20XV10. First, the VCC rise must be
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of tpr time. As in normal system operation, avoid
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Circuitry within the GAL20XV10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs
set low after a specified time (tpr, 1µs MAX). As a result, the state
on the registered output pins (if they are enabled) will always be
high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown below. Because of the asynchronous nature
Vcc
Vcc (min.)
t su
t wl
CLK
t pr
INTERNAL REGISTER
Q - OUTPUT
Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
12
Specifications GAL20XV10
Typical AC and DC Characteristic Diagrams
Normalized Tpd vs Vcc
1.2
1.2
1.1
PT L->H
1
0.9
0.8
RISE
1.1
Normalized Tsu
PT H->L
Normalized Tco
FALL
1
0.9
4.75
5.00
5.25
5.50
4.50
4.75
Supply Voltage (V)
Normalized Tpd vs Temp
5.00
5.25
1.1
PT L->H
1
0.9
0.8
0
25
50
75
100
RISE
1.1
FALL
1
0.9
0.8
1.3
PT H->L
1.2
PT L->H
1.1
1
0.9
0.8
0.7
-55
-25
0
25
50
75
100
125
-55
-25
Temperature (deg. C)
0
Delta Tco vs # of Outputs
Switching
-0.5
-1
RISE
-1.5
FALL
-2
-0.5
-1
RISE
-1.5
FALL
-2
4
5
6
7
8
9
10
1
Number of Outputs Switching
2
3
4
5
6
7
8
9
10
Number of Outputs Switching
Delta Tpd vs Output Loading
Delta Tco vs Output Loading
12
12
8
Delta Tco (ns)
RISE
10
FALL
6
4
2
10
RISE
8
FALL
6
4
2
0
0
-2
-2
0
50
100
150
200
250
0
300
50
100
150
200
250
Output Loading (pF)
Output Loading (pF)
13
25
50
75
100
Temperature (deg. C)
0
3
5.50
1.4
0
2
5.25
Normalized Tsu vs Temp
Delta Tpd vs # of Outputs
Switching
1
5.00
Normalized Tco vs Temp
1.2
125
4.75
Supply Voltage (V)
Temperature (deg. C)
Delta Tpd (ns)
-25
Delta Tpd (ns)
-55
0.9
4.50
0.7
0.7
1
Supply Voltage (V)
Normalized Tsu
PT H->L
Normalized Tco
1.2
PT L->H
5.50
1.3
1.3
PT H->L
1.1
0.8
0.8
4.50
Delta Tco (ns)
Normalized Tpd
1.2
Normalized Tpd
Normalized Tsu vs Vcc
Normalized Tco vs Vcc
300
125
Specifications GAL20XV10
Typical AC and DC Characteristic Diagrams
Vol vs Iol
Voh vs Ioh
5
3
2.5
4.5
4
1.5
1
4.25
Voh (V)
2
Voh (V)
Vol (V)
Voh vs Ioh
3
2
3.75
1
0.5
0
0
0.00
20.00
40.00
60.00
80.00
3.5
0.00
100.00
10.00
20.00
Iol (mA)
Normalized Icc vs Vcc
1.20
4
30.00 40.00
50.00 60.00
0.00
1.00
2.00
3.00
Ioh(mA)
Ioh(mA)
Normalized Icc vs Temp
Normalized Icc vs Freq.
4.00
1.70
1.2
1.00
0.90
Normalized Icc
Normalized Icc
Normalized Icc
1.60
1.10
1.1
1
0.9
1.50
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.80
0.8
4.50
4.75
5.00
5.25
5.50
0.70
-55
Supply Voltage (V)
0
25
50
75
100
125
Temperature (deg. C)
0
10
20
Iik (mA)
8
6
4
2
40
60
80
100
120
0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Vin (V)
-2.00
-1.50
-1.00
Vik (V)
14
-0.50
0
25
50
75
Frequency (MHz)
Input Clamp (Vik)
Delta Icc vs Vin (1 input)
Delta Icc (mA)
-25
0.00
100